1/* 2 * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <common/bl_common.h> 9#include <common/debug.h> 10#include <cortex_a53.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include <lib/cpus/errata.h> 14 15cpu_reset_prologue cortex_a53 16 17 /* --------------------------------------------- 18 * Disable intra-cluster coherency 19 * --------------------------------------------- 20 */ 21func cortex_a53_disable_smp 22 sysreg_bit_clear CORTEX_A53_ECTLR_EL1, CORTEX_A53_ECTLR_SMP_BIT 23 isb 24 dsb sy 25 ret 26endfunc cortex_a53_disable_smp 27 28/* Due to the nature of the errata it is applied unconditionally when chosen */ 29check_erratum_ls cortex_a53, ERRATUM(819472), CPU_REV(0, 1) 30/* erratum workaround is interleaved with generic code */ 31add_erratum_entry cortex_a53, ERRATUM(819472), ERRATUM_ALWAYS_CHOSEN 32 33/* Due to the nature of the errata it is applied unconditionally when chosen */ 34check_erratum_ls cortex_a53, ERRATUM(824069), CPU_REV(0, 2) 35/* erratum workaround is interleaved with generic code */ 36add_erratum_entry cortex_a53, ERRATUM(824069), ERRATUM_ALWAYS_CHOSEN 37 38workaround_reset_start cortex_a53, ERRATUM(826319), ERRATA_A53_826319 39 mrs x1, CORTEX_A53_L2ACTLR_EL1 40 bic x1, x1, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN 41 orr x1, x1, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH 42 msr CORTEX_A53_L2ACTLR_EL1, x1 43workaround_reset_end cortex_a53, ERRATUM(826319) 44 45check_erratum_ls cortex_a53, ERRATUM(826319), CPU_REV(0, 2) 46 47/* Due to the nature of the errata it is applied unconditionally when chosen */ 48check_erratum_ls cortex_a53, ERRATUM(827319), CPU_REV(0, 2) 49/* erratum workaround is interleaved with generic code */ 50add_erratum_entry cortex_a53, ERRATUM(827319), ERRATUM_ALWAYS_CHOSEN 51 52check_erratum_custom_start cortex_a53, ERRATUM(835769) 53 cmp x0, CPU_REV(0, 4) 54 b.hi errata_not_applies 55 /* 56 * Fix potentially available for revisions r0p2, r0p3 and r0p4. 57 * If r0p2, r0p3 or r0p4; check for fix in REVIDR, else exit. 58 */ 59 cmp x0, #0x01 60 mov x0, #ERRATA_APPLIES 61 b.ls exit_check_errata_835769 62 /* Load REVIDR. */ 63 mrs x1, revidr_el1 64 /* If REVIDR[7] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */ 65 tbz x1, #7, exit_check_errata_835769 66errata_not_applies: 67 mov x0, #ERRATA_NOT_APPLIES 68exit_check_errata_835769: 69 ret 70check_erratum_custom_end cortex_a53, ERRATUM(835769) 71 72/* workaround at build time */ 73add_erratum_entry cortex_a53, ERRATUM(835769), ERRATA_A53_835769 74 75 /* 76 * Disable the cache non-temporal hint. 77 * 78 * This ignores the Transient allocation hint in the MAIR and treats 79 * allocations the same as non-transient allocation types. As a result, 80 * the LDNP and STNP instructions in AArch64 behave the same as the 81 * equivalent LDP and STP instructions. 82 */ 83workaround_reset_start cortex_a53, ERRATUM(836870), ERRATA_A53_836870 | A53_DISABLE_NON_TEMPORAL_HINT 84 sysreg_bit_set CORTEX_A53_CPUACTLR_EL1, CORTEX_A53_CPUACTLR_EL1_DTAH 85workaround_reset_end cortex_a53, ERRATUM(836870) 86 87check_erratum_ls cortex_a53, ERRATUM(836870), CPU_REV(0, 3) 88 89check_erratum_custom_start cortex_a53, ERRATUM(843419) 90 mov x1, #ERRATA_APPLIES 91 mov x2, #ERRATA_NOT_APPLIES 92 cmp x0, CPU_REV(0, 4) 93 csel x0, x1, x2, ls 94 /* 95 * Fix potentially available for revision r0p4. 96 * If r0p4 check for fix in REVIDR, else exit. 97 */ 98 b.ne exit_check_errata_843419 99 /* Load REVIDR. */ 100 mrs x3, revidr_el1 101 /* If REVIDR[8] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */ 102 tbz x3, #8, exit_check_errata_843419 103 mov x0, x2 104exit_check_errata_843419: 105 ret 106check_erratum_custom_end cortex_a53, ERRATUM(843419) 107 108/* workaround at build time */ 109add_erratum_entry cortex_a53, ERRATUM(843419), ERRATA_A53_843419 110 111 /* 112 * Earlier revisions of the core are affected as well, but don't 113 * have the chicken bit in the CPUACTLR register. It is expected that 114 * the rich OS takes care of that, especially as the workaround is 115 * shared with other erratas in those revisions of the CPU. 116 */ 117workaround_reset_start cortex_a53, ERRATUM(855873), ERRATA_A53_855873 118 sysreg_bit_set CORTEX_A53_CPUACTLR_EL1, CORTEX_A53_CPUACTLR_EL1_ENDCCASCI 119workaround_reset_end cortex_a53, ERRATUM(855873) 120 121check_erratum_hs cortex_a53, ERRATUM(855873), CPU_REV(0, 3) 122 123check_erratum_chosen cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924 124 125/* erratum has no workaround in the cpu. Generic code must take care */ 126add_erratum_entry cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924 127 128cpu_reset_func_start cortex_a53 129 /* Enable the SMP bit. */ 130 sysreg_bit_set CORTEX_A53_ECTLR_EL1, CORTEX_A53_ECTLR_SMP_BIT 131cpu_reset_func_end cortex_a53 132 133func cortex_a53_core_pwr_dwn 134 mov x18, x30 135 136 /* --------------------------------------------- 137 * Flush L1 caches. 138 * --------------------------------------------- 139 */ 140 mov x0, #DCCISW 141 bl dcsw_op_level1 142 143 /* --------------------------------------------- 144 * Come out of intra cluster coherency 145 * --------------------------------------------- 146 */ 147 mov x30, x18 148 b cortex_a53_disable_smp 149endfunc cortex_a53_core_pwr_dwn 150 151func cortex_a53_cluster_pwr_dwn 152 mov x18, x30 153 154 /* --------------------------------------------- 155 * Flush L1 caches. 156 * --------------------------------------------- 157 */ 158 mov x0, #DCCISW 159 bl dcsw_op_level1 160 161 /* --------------------------------------------- 162 * Disable the optional ACP. 163 * --------------------------------------------- 164 */ 165 bl plat_disable_acp 166 167 /* --------------------------------------------- 168 * Flush L2 caches. 169 * --------------------------------------------- 170 */ 171 mov x0, #DCCISW 172 bl dcsw_op_level2 173 174 /* --------------------------------------------- 175 * Come out of intra cluster coherency 176 * --------------------------------------------- 177 */ 178 mov x30, x18 179 b cortex_a53_disable_smp 180endfunc cortex_a53_cluster_pwr_dwn 181 182 /* --------------------------------------------- 183 * This function provides cortex_a53 specific 184 * register information for crash reporting. 185 * It needs to return with x6 pointing to 186 * a list of register names in ascii and 187 * x8 - x15 having values of registers to be 188 * reported. 189 * --------------------------------------------- 190 */ 191.section .rodata.cortex_a53_regs, "aS" 192cortex_a53_regs: /* The ascii list of register names to be reported */ 193 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", \ 194 "cpuactlr_el1", "" 195 196func cortex_a53_cpu_reg_dump 197 adr x6, cortex_a53_regs 198 mrs x8, CORTEX_A53_ECTLR_EL1 199 mrs x9, CORTEX_A53_MERRSR_EL1 200 mrs x10, CORTEX_A53_L2MERRSR_EL1 201 mrs x11, CORTEX_A53_CPUACTLR_EL1 202 ret 203endfunc cortex_a53_cpu_reg_dump 204 205declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \ 206 cortex_a53_reset_func, \ 207 cortex_a53_core_pwr_dwn, \ 208 cortex_a53_cluster_pwr_dwn 209