1/* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30#include <arch.h> 31#include <asm_macros.S> 32#include <bl_common.h> 33#include <cortex_a53.h> 34#include <cpu_macros.S> 35#include <plat_macros.S> 36 37 /* --------------------------------------------- 38 * Disable L1 data cache and unified L2 cache 39 * --------------------------------------------- 40 */ 41func cortex_a53_disable_dcache 42 mrs x1, sctlr_el3 43 bic x1, x1, #SCTLR_C_BIT 44 msr sctlr_el3, x1 45 isb 46 ret 47endfunc cortex_a53_disable_dcache 48 49 /* --------------------------------------------- 50 * Disable intra-cluster coherency 51 * --------------------------------------------- 52 */ 53func cortex_a53_disable_smp 54 mrs x0, CPUECTLR_EL1 55 bic x0, x0, #CPUECTLR_SMP_BIT 56 msr CPUECTLR_EL1, x0 57 isb 58 dsb sy 59 ret 60endfunc cortex_a53_disable_smp 61 62 /* -------------------------------------------------- 63 * Errata Workaround for Cortex A53 Errata #826319. 64 * This applies only to revision <= r0p2 of Cortex A53. 65 * Inputs: 66 * x0: variant[4:7] and revision[0:3] of current cpu. 67 * Clobbers : x0 - x5 68 * -------------------------------------------------- 69 */ 70func errata_a53_826319_wa 71 /* 72 * Compare x0 against revision r0p2 73 */ 74 cmp x0, #2 75 b.ls apply_826319 76#if DEBUG 77 b print_revision_warning 78#else 79 ret 80#endif 81apply_826319: 82 mrs x1, L2ACTLR_EL1 83 bic x1, x1, #L2ACTLR_ENABLE_UNIQUECLEAN 84 orr x1, x1, #L2ACTLR_DISABLE_CLEAN_PUSH 85 msr L2ACTLR_EL1, x1 86 ret 87endfunc errata_a53_826319_wa 88 89 /* --------------------------------------------------------------------- 90 * Disable the cache non-temporal hint. 91 * 92 * This ignores the Transient allocation hint in the MAIR and treats 93 * allocations the same as non-transient allocation types. As a result, 94 * the LDNP and STNP instructions in AArch64 behave the same as the 95 * equivalent LDP and STP instructions. 96 * 97 * This is relevant only for revisions <= r0p3 of Cortex-A53. 98 * From r0p4 and onwards, the bit to disable the hint is enabled by 99 * default at reset. 100 * 101 * Inputs: 102 * x0: variant[4:7] and revision[0:3] of current cpu. 103 * Clobbers : x0 - x5 104 * --------------------------------------------------------------------- 105 */ 106func a53_disable_non_temporal_hint 107 /* 108 * Compare x0 against revision r0p3 109 */ 110 cmp x0, #3 111 b.ls disable_hint 112#if DEBUG 113 b print_revision_warning 114#else 115 ret 116#endif 117disable_hint: 118 mrs x1, CPUACTLR_EL1 119 orr x1, x1, #CPUACTLR_DTAH 120 msr CPUACTLR_EL1, x1 121 ret 122endfunc a53_disable_non_temporal_hint 123 124 /* ------------------------------------------------- 125 * The CPU Ops reset function for Cortex-A53. 126 * Clobbers: x0-x5, x15, x19, x30 127 * ------------------------------------------------- 128 */ 129func cortex_a53_reset_func 130 mov x19, x30 131 mrs x0, midr_el1 132 133 /* 134 * Extract the variant[20:23] and revision[0:3] from x0 135 * and pack it in x15[0:7] as variant[4:7] and revision[0:3]. 136 * First extract x0[16:23] to x15[0:7] and zero fill the rest. 137 * Then extract x0[0:3] into x15[0:3] retaining other bits. 138 */ 139 ubfx x15, x0, #(MIDR_VAR_SHIFT - MIDR_REV_BITS), \ 140 #(MIDR_REV_BITS + MIDR_VAR_BITS) 141 bfxil x15, x0, #MIDR_REV_SHIFT, #MIDR_REV_BITS 142 143#if ERRATA_A53_826319 144 mov x0, x15 145 bl errata_a53_826319_wa 146#endif 147 148#if ERRATA_A53_836870 || A53_DISABLE_NON_TEMPORAL_HINT 149 mov x0, x15 150 bl a53_disable_non_temporal_hint 151#endif 152 153 /* --------------------------------------------- 154 * Enable the SMP bit. 155 * --------------------------------------------- 156 */ 157 mrs x0, CPUECTLR_EL1 158 orr x0, x0, #CPUECTLR_SMP_BIT 159 msr CPUECTLR_EL1, x0 160 isb 161 ret x19 162endfunc cortex_a53_reset_func 163 164func cortex_a53_core_pwr_dwn 165 mov x18, x30 166 167 /* --------------------------------------------- 168 * Turn off caches. 169 * --------------------------------------------- 170 */ 171 bl cortex_a53_disable_dcache 172 173 /* --------------------------------------------- 174 * Flush L1 caches. 175 * --------------------------------------------- 176 */ 177 mov x0, #DCCISW 178 bl dcsw_op_level1 179 180 /* --------------------------------------------- 181 * Come out of intra cluster coherency 182 * --------------------------------------------- 183 */ 184 mov x30, x18 185 b cortex_a53_disable_smp 186endfunc cortex_a53_core_pwr_dwn 187 188func cortex_a53_cluster_pwr_dwn 189 mov x18, x30 190 191 /* --------------------------------------------- 192 * Turn off caches. 193 * --------------------------------------------- 194 */ 195 bl cortex_a53_disable_dcache 196 197 /* --------------------------------------------- 198 * Flush L1 caches. 199 * --------------------------------------------- 200 */ 201 mov x0, #DCCISW 202 bl dcsw_op_level1 203 204 /* --------------------------------------------- 205 * Disable the optional ACP. 206 * --------------------------------------------- 207 */ 208 bl plat_disable_acp 209 210 /* --------------------------------------------- 211 * Flush L2 caches. 212 * --------------------------------------------- 213 */ 214 mov x0, #DCCISW 215 bl dcsw_op_level2 216 217 /* --------------------------------------------- 218 * Come out of intra cluster coherency 219 * --------------------------------------------- 220 */ 221 mov x30, x18 222 b cortex_a53_disable_smp 223endfunc cortex_a53_cluster_pwr_dwn 224 225 /* --------------------------------------------- 226 * This function provides cortex_a53 specific 227 * register information for crash reporting. 228 * It needs to return with x6 pointing to 229 * a list of register names in ascii and 230 * x8 - x15 having values of registers to be 231 * reported. 232 * --------------------------------------------- 233 */ 234.section .rodata.cortex_a53_regs, "aS" 235cortex_a53_regs: /* The ascii list of register names to be reported */ 236 .asciz "cpuectlr_el1", "" 237 238func cortex_a53_cpu_reg_dump 239 adr x6, cortex_a53_regs 240 mrs x8, CPUECTLR_EL1 241 ret 242endfunc cortex_a53_cpu_reg_dump 243 244declare_cpu_ops cortex_a53, CORTEX_A53_MIDR 245