1/* 2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30#include <arch.h> 31#include <asm_macros.S> 32#include <bl_common.h> 33#include <cortex_a53.h> 34#include <cpu_macros.S> 35#include <plat_macros.S> 36 37 /* --------------------------------------------- 38 * Disable L1 data cache and unified L2 cache 39 * --------------------------------------------- 40 */ 41func cortex_a53_disable_dcache 42 mrs x1, sctlr_el3 43 bic x1, x1, #SCTLR_C_BIT 44 msr sctlr_el3, x1 45 isb 46 ret 47endfunc cortex_a53_disable_dcache 48 49 /* --------------------------------------------- 50 * Disable intra-cluster coherency 51 * --------------------------------------------- 52 */ 53func cortex_a53_disable_smp 54 mrs x0, CPUECTLR_EL1 55 bic x0, x0, #CPUECTLR_SMP_BIT 56 msr CPUECTLR_EL1, x0 57 isb 58 dsb sy 59 ret 60endfunc cortex_a53_disable_smp 61 62func cortex_a53_reset_func 63 /* --------------------------------------------- 64 * As a bare minimum enable the SMP bit if it is 65 * not already set. 66 * Clobbers : x0 67 * --------------------------------------------- 68 */ 69 mrs x0, CPUECTLR_EL1 70 tst x0, #CPUECTLR_SMP_BIT 71 b.ne skip_smp_setup 72 orr x0, x0, #CPUECTLR_SMP_BIT 73 msr CPUECTLR_EL1, x0 74 isb 75skip_smp_setup: 76 ret 77endfunc cortex_a53_reset_func 78 79func cortex_a53_core_pwr_dwn 80 mov x18, x30 81 82 /* --------------------------------------------- 83 * Turn off caches. 84 * --------------------------------------------- 85 */ 86 bl cortex_a53_disable_dcache 87 88 /* --------------------------------------------- 89 * Flush L1 caches. 90 * --------------------------------------------- 91 */ 92 mov x0, #DCCISW 93 bl dcsw_op_level1 94 95 /* --------------------------------------------- 96 * Come out of intra cluster coherency 97 * --------------------------------------------- 98 */ 99 mov x30, x18 100 b cortex_a53_disable_smp 101endfunc cortex_a53_core_pwr_dwn 102 103func cortex_a53_cluster_pwr_dwn 104 mov x18, x30 105 106 /* --------------------------------------------- 107 * Turn off caches. 108 * --------------------------------------------- 109 */ 110 bl cortex_a53_disable_dcache 111 112 /* --------------------------------------------- 113 * Flush L1 caches. 114 * --------------------------------------------- 115 */ 116 mov x0, #DCCISW 117 bl dcsw_op_level1 118 119 /* --------------------------------------------- 120 * Disable the optional ACP. 121 * --------------------------------------------- 122 */ 123 bl plat_disable_acp 124 125 /* --------------------------------------------- 126 * Flush L2 caches. 127 * --------------------------------------------- 128 */ 129 mov x0, #DCCISW 130 bl dcsw_op_level2 131 132 /* --------------------------------------------- 133 * Come out of intra cluster coherency 134 * --------------------------------------------- 135 */ 136 mov x30, x18 137 b cortex_a53_disable_smp 138endfunc cortex_a53_cluster_pwr_dwn 139 140 /* --------------------------------------------- 141 * This function provides cortex_a53 specific 142 * register information for crash reporting. 143 * It needs to return with x6 pointing to 144 * a list of register names in ascii and 145 * x8 - x15 having values of registers to be 146 * reported. 147 * --------------------------------------------- 148 */ 149.section .rodata.cortex_a53_regs, "aS" 150cortex_a53_regs: /* The ascii list of register names to be reported */ 151 .asciz "cpuectlr_el1", "" 152 153func cortex_a53_cpu_reg_dump 154 adr x6, cortex_a53_regs 155 mrs x8, CPUECTLR_EL1 156 ret 157endfunc cortex_a53_cpu_reg_dump 158 159declare_cpu_ops cortex_a53, CORTEX_A53_MIDR 160