1/* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30#include <arch.h> 31#include <asm_macros.S> 32#include <bl_common.h> 33#include <cortex_a53.h> 34#include <cpu_macros.S> 35#include <debug.h> 36#include <plat_macros.S> 37 38 /* --------------------------------------------- 39 * Disable L1 data cache and unified L2 cache 40 * --------------------------------------------- 41 */ 42func cortex_a53_disable_dcache 43 mrs x1, sctlr_el3 44 bic x1, x1, #SCTLR_C_BIT 45 msr sctlr_el3, x1 46 isb 47 ret 48endfunc cortex_a53_disable_dcache 49 50 /* --------------------------------------------- 51 * Disable intra-cluster coherency 52 * --------------------------------------------- 53 */ 54func cortex_a53_disable_smp 55 mrs x0, CPUECTLR_EL1 56 bic x0, x0, #CPUECTLR_SMP_BIT 57 msr CPUECTLR_EL1, x0 58 isb 59 dsb sy 60 ret 61endfunc cortex_a53_disable_smp 62 63 /* -------------------------------------------------- 64 * Errata Workaround for Cortex A53 Errata #826319. 65 * This applies only to revision <= r0p2 of Cortex A53. 66 * Inputs: 67 * x0: variant[4:7] and revision[0:3] of current cpu. 68 * Clobbers : x0 - x5 69 * -------------------------------------------------- 70 */ 71func errata_a53_826319_wa 72 /* 73 * Compare x0 against revision r0p2 74 */ 75 cmp x0, #2 76 b.ls apply_826319 77#if LOG_LEVEL >= LOG_LEVEL_VERBOSE 78 b print_revision_warning 79#else 80 ret 81#endif 82apply_826319: 83 mrs x1, L2ACTLR_EL1 84 bic x1, x1, #L2ACTLR_ENABLE_UNIQUECLEAN 85 orr x1, x1, #L2ACTLR_DISABLE_CLEAN_PUSH 86 msr L2ACTLR_EL1, x1 87 ret 88endfunc errata_a53_826319_wa 89 90 /* --------------------------------------------------------------------- 91 * Disable the cache non-temporal hint. 92 * 93 * This ignores the Transient allocation hint in the MAIR and treats 94 * allocations the same as non-transient allocation types. As a result, 95 * the LDNP and STNP instructions in AArch64 behave the same as the 96 * equivalent LDP and STP instructions. 97 * 98 * This is relevant only for revisions <= r0p3 of Cortex-A53. 99 * From r0p4 and onwards, the bit to disable the hint is enabled by 100 * default at reset. 101 * 102 * Inputs: 103 * x0: variant[4:7] and revision[0:3] of current cpu. 104 * Clobbers : x0 - x5 105 * --------------------------------------------------------------------- 106 */ 107func a53_disable_non_temporal_hint 108 /* 109 * Compare x0 against revision r0p3 110 */ 111 cmp x0, #3 112 b.ls disable_hint 113#if LOG_LEVEL >= LOG_LEVEL_VERBOSE 114 b print_revision_warning 115#else 116 ret 117#endif 118disable_hint: 119 mrs x1, CPUACTLR_EL1 120 orr x1, x1, #CPUACTLR_DTAH 121 msr CPUACTLR_EL1, x1 122 ret 123endfunc a53_disable_non_temporal_hint 124 125 /* ------------------------------------------------- 126 * The CPU Ops reset function for Cortex-A53. 127 * Clobbers: x0-x5, x15, x19, x30 128 * ------------------------------------------------- 129 */ 130func cortex_a53_reset_func 131 mov x19, x30 132 mrs x0, midr_el1 133 134 /* 135 * Extract the variant[20:23] and revision[0:3] from x0 136 * and pack it in x15[0:7] as variant[4:7] and revision[0:3]. 137 * First extract x0[16:23] to x15[0:7] and zero fill the rest. 138 * Then extract x0[0:3] into x15[0:3] retaining other bits. 139 */ 140 ubfx x15, x0, #(MIDR_VAR_SHIFT - MIDR_REV_BITS), \ 141 #(MIDR_REV_BITS + MIDR_VAR_BITS) 142 bfxil x15, x0, #MIDR_REV_SHIFT, #MIDR_REV_BITS 143 144#if ERRATA_A53_826319 145 mov x0, x15 146 bl errata_a53_826319_wa 147#endif 148 149#if ERRATA_A53_836870 || A53_DISABLE_NON_TEMPORAL_HINT 150 mov x0, x15 151 bl a53_disable_non_temporal_hint 152#endif 153 154 /* --------------------------------------------- 155 * Enable the SMP bit. 156 * --------------------------------------------- 157 */ 158 mrs x0, CPUECTLR_EL1 159 orr x0, x0, #CPUECTLR_SMP_BIT 160 msr CPUECTLR_EL1, x0 161 isb 162 ret x19 163endfunc cortex_a53_reset_func 164 165func cortex_a53_core_pwr_dwn 166 mov x18, x30 167 168 /* --------------------------------------------- 169 * Turn off caches. 170 * --------------------------------------------- 171 */ 172 bl cortex_a53_disable_dcache 173 174 /* --------------------------------------------- 175 * Flush L1 caches. 176 * --------------------------------------------- 177 */ 178 mov x0, #DCCISW 179 bl dcsw_op_level1 180 181 /* --------------------------------------------- 182 * Come out of intra cluster coherency 183 * --------------------------------------------- 184 */ 185 mov x30, x18 186 b cortex_a53_disable_smp 187endfunc cortex_a53_core_pwr_dwn 188 189func cortex_a53_cluster_pwr_dwn 190 mov x18, x30 191 192 /* --------------------------------------------- 193 * Turn off caches. 194 * --------------------------------------------- 195 */ 196 bl cortex_a53_disable_dcache 197 198 /* --------------------------------------------- 199 * Flush L1 caches. 200 * --------------------------------------------- 201 */ 202 mov x0, #DCCISW 203 bl dcsw_op_level1 204 205 /* --------------------------------------------- 206 * Disable the optional ACP. 207 * --------------------------------------------- 208 */ 209 bl plat_disable_acp 210 211 /* --------------------------------------------- 212 * Flush L2 caches. 213 * --------------------------------------------- 214 */ 215 mov x0, #DCCISW 216 bl dcsw_op_level2 217 218 /* --------------------------------------------- 219 * Come out of intra cluster coherency 220 * --------------------------------------------- 221 */ 222 mov x30, x18 223 b cortex_a53_disable_smp 224endfunc cortex_a53_cluster_pwr_dwn 225 226 /* --------------------------------------------- 227 * This function provides cortex_a53 specific 228 * register information for crash reporting. 229 * It needs to return with x6 pointing to 230 * a list of register names in ascii and 231 * x8 - x15 having values of registers to be 232 * reported. 233 * --------------------------------------------- 234 */ 235.section .rodata.cortex_a53_regs, "aS" 236cortex_a53_regs: /* The ascii list of register names to be reported */ 237 .asciz "cpuectlr_el1", "" 238 239func cortex_a53_cpu_reg_dump 240 adr x6, cortex_a53_regs 241 mrs x8, CPUECTLR_EL1 242 ret 243endfunc cortex_a53_cpu_reg_dump 244 245declare_cpu_ops cortex_a53, CORTEX_A53_MIDR 246