1/* 2 * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <common/bl_common.h> 9#include <common/debug.h> 10#include <cortex_a53.h> 11#include <cpu_macros.S> 12#include <lib/cpus/errata_report.h> 13#include <plat_macros.S> 14 15#if A53_DISABLE_NON_TEMPORAL_HINT 16#undef ERRATA_A53_836870 17#define ERRATA_A53_836870 1 18#endif 19 20 /* --------------------------------------------- 21 * Disable L1 data cache and unified L2 cache 22 * --------------------------------------------- 23 */ 24func cortex_a53_disable_dcache 25 mrs x1, sctlr_el3 26 bic x1, x1, #SCTLR_C_BIT 27 msr sctlr_el3, x1 28 isb 29 ret 30endfunc cortex_a53_disable_dcache 31 32 /* --------------------------------------------- 33 * Disable intra-cluster coherency 34 * --------------------------------------------- 35 */ 36func cortex_a53_disable_smp 37 mrs x0, CORTEX_A53_ECTLR_EL1 38 bic x0, x0, #CORTEX_A53_ECTLR_SMP_BIT 39 msr CORTEX_A53_ECTLR_EL1, x0 40 isb 41 dsb sy 42 ret 43endfunc cortex_a53_disable_smp 44 45 /* --------------------------------------------------- 46 * Errata Workaround for Cortex A53 Errata #819472. 47 * This applies only to revision <= r0p1 of Cortex A53. 48 * Due to the nature of the errata it is applied unconditionally 49 * when built in, report it as applicable in this case 50 * --------------------------------------------------- 51 */ 52func check_errata_819472 53#if ERRATA_A53_819472 54 mov x0, #ERRATA_APPLIES 55 ret 56#else 57 mov x1, #0x01 58 b cpu_rev_var_ls 59#endif 60endfunc check_errata_819472 61 62 /* --------------------------------------------------- 63 * Errata Workaround for Cortex A53 Errata #824069. 64 * This applies only to revision <= r0p2 of Cortex A53. 65 * Due to the nature of the errata it is applied unconditionally 66 * when built in, report it as applicable in this case 67 * --------------------------------------------------- 68 */ 69func check_errata_824069 70#if ERRATA_A53_824069 71 mov x0, #ERRATA_APPLIES 72 ret 73#else 74 mov x1, #0x02 75 b cpu_rev_var_ls 76#endif 77endfunc check_errata_824069 78 79 /* -------------------------------------------------- 80 * Errata Workaround for Cortex A53 Errata #826319. 81 * This applies only to revision <= r0p2 of Cortex A53. 82 * Inputs: 83 * x0: variant[4:7] and revision[0:3] of current cpu. 84 * Shall clobber: x0-x17 85 * -------------------------------------------------- 86 */ 87func errata_a53_826319_wa 88 /* 89 * Compare x0 against revision r0p2 90 */ 91 mov x17, x30 92 bl check_errata_826319 93 cbz x0, 1f 94 mrs x1, CORTEX_A53_L2ACTLR_EL1 95 bic x1, x1, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN 96 orr x1, x1, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH 97 msr CORTEX_A53_L2ACTLR_EL1, x1 981: 99 ret x17 100endfunc errata_a53_826319_wa 101 102func check_errata_826319 103 mov x1, #0x02 104 b cpu_rev_var_ls 105endfunc check_errata_826319 106 107 /* --------------------------------------------------- 108 * Errata Workaround for Cortex A53 Errata #827319. 109 * This applies only to revision <= r0p2 of Cortex A53. 110 * Due to the nature of the errata it is applied unconditionally 111 * when built in, report it as applicable in this case 112 * --------------------------------------------------- 113 */ 114func check_errata_827319 115#if ERRATA_A53_827319 116 mov x0, #ERRATA_APPLIES 117 ret 118#else 119 mov x1, #0x02 120 b cpu_rev_var_ls 121#endif 122endfunc check_errata_827319 123 124 /* --------------------------------------------------------------------- 125 * Disable the cache non-temporal hint. 126 * 127 * This ignores the Transient allocation hint in the MAIR and treats 128 * allocations the same as non-transient allocation types. As a result, 129 * the LDNP and STNP instructions in AArch64 behave the same as the 130 * equivalent LDP and STP instructions. 131 * 132 * This is relevant only for revisions <= r0p3 of Cortex-A53. 133 * From r0p4 and onwards, the bit to disable the hint is enabled by 134 * default at reset. 135 * 136 * Inputs: 137 * x0: variant[4:7] and revision[0:3] of current cpu. 138 * Shall clobber: x0-x17 139 * --------------------------------------------------------------------- 140 */ 141func a53_disable_non_temporal_hint 142 /* 143 * Compare x0 against revision r0p3 144 */ 145 mov x17, x30 146 bl check_errata_disable_non_temporal_hint 147 cbz x0, 1f 148 mrs x1, CORTEX_A53_CPUACTLR_EL1 149 orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_DTAH 150 msr CORTEX_A53_CPUACTLR_EL1, x1 1511: 152 ret x17 153endfunc a53_disable_non_temporal_hint 154 155func check_errata_disable_non_temporal_hint 156 mov x1, #0x03 157 b cpu_rev_var_ls 158endfunc check_errata_disable_non_temporal_hint 159 160 /* -------------------------------------------------- 161 * Errata Workaround for Cortex A53 Errata #855873. 162 * 163 * This applies only to revisions >= r0p3 of Cortex A53. 164 * Earlier revisions of the core are affected as well, but don't 165 * have the chicken bit in the CPUACTLR register. It is expected that 166 * the rich OS takes care of that, especially as the workaround is 167 * shared with other erratas in those revisions of the CPU. 168 * Inputs: 169 * x0: variant[4:7] and revision[0:3] of current cpu. 170 * Shall clobber: x0-x17 171 * -------------------------------------------------- 172 */ 173func errata_a53_855873_wa 174 /* 175 * Compare x0 against revision r0p3 and higher 176 */ 177 mov x17, x30 178 bl check_errata_855873 179 cbz x0, 1f 180 181 mrs x1, CORTEX_A53_CPUACTLR_EL1 182 orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_ENDCCASCI 183 msr CORTEX_A53_CPUACTLR_EL1, x1 1841: 185 ret x17 186endfunc errata_a53_855873_wa 187 188func check_errata_855873 189 mov x1, #0x03 190 b cpu_rev_var_hs 191endfunc check_errata_855873 192 193/* 194 * Errata workaround for Cortex A53 Errata #835769. 195 * This applies to revisions <= r0p4 of Cortex A53. 196 * This workaround is statically enabled at build time. 197 */ 198func check_errata_835769 199 cmp x0, #0x04 200 b.hi errata_not_applies 201 /* 202 * Fix potentially available for revisions r0p2, r0p3 and r0p4. 203 * If r0p2, r0p3 or r0p4; check for fix in REVIDR, else exit. 204 */ 205 cmp x0, #0x01 206 mov x0, #ERRATA_APPLIES 207 b.ls exit_check_errata_835769 208 /* Load REVIDR. */ 209 mrs x1, revidr_el1 210 /* If REVIDR[7] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */ 211 tbz x1, #7, exit_check_errata_835769 212errata_not_applies: 213 mov x0, #ERRATA_NOT_APPLIES 214exit_check_errata_835769: 215 ret 216endfunc check_errata_835769 217 218/* 219 * Errata workaround for Cortex A53 Errata #843419. 220 * This applies to revisions <= r0p4 of Cortex A53. 221 * This workaround is statically enabled at build time. 222 */ 223func check_errata_843419 224 mov x1, #ERRATA_APPLIES 225 mov x2, #ERRATA_NOT_APPLIES 226 cmp x0, #0x04 227 csel x0, x1, x2, ls 228 /* 229 * Fix potentially available for revision r0p4. 230 * If r0p4 check for fix in REVIDR, else exit. 231 */ 232 b.ne exit_check_errata_843419 233 /* Load REVIDR. */ 234 mrs x3, revidr_el1 235 /* If REVIDR[8] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */ 236 tbz x3, #8, exit_check_errata_843419 237 mov x0, x2 238exit_check_errata_843419: 239 ret 240endfunc check_errata_843419 241 242 /* ------------------------------------------------- 243 * The CPU Ops reset function for Cortex-A53. 244 * Shall clobber: x0-x19 245 * ------------------------------------------------- 246 */ 247func cortex_a53_reset_func 248 mov x19, x30 249 bl cpu_get_rev_var 250 mov x18, x0 251 252 253#if ERRATA_A53_826319 254 mov x0, x18 255 bl errata_a53_826319_wa 256#endif 257 258#if ERRATA_A53_836870 259 mov x0, x18 260 bl a53_disable_non_temporal_hint 261#endif 262 263#if ERRATA_A53_855873 264 mov x0, x18 265 bl errata_a53_855873_wa 266#endif 267 268 /* --------------------------------------------- 269 * Enable the SMP bit. 270 * --------------------------------------------- 271 */ 272 mrs x0, CORTEX_A53_ECTLR_EL1 273 orr x0, x0, #CORTEX_A53_ECTLR_SMP_BIT 274 msr CORTEX_A53_ECTLR_EL1, x0 275 isb 276 ret x19 277endfunc cortex_a53_reset_func 278 279func cortex_a53_core_pwr_dwn 280 mov x18, x30 281 282#if !TI_AM65X_WORKAROUND 283 /* --------------------------------------------- 284 * Turn off caches. 285 * --------------------------------------------- 286 */ 287 bl cortex_a53_disable_dcache 288#endif 289 290 /* --------------------------------------------- 291 * Flush L1 caches. 292 * --------------------------------------------- 293 */ 294 mov x0, #DCCISW 295 bl dcsw_op_level1 296 297 /* --------------------------------------------- 298 * Come out of intra cluster coherency 299 * --------------------------------------------- 300 */ 301 mov x30, x18 302 b cortex_a53_disable_smp 303endfunc cortex_a53_core_pwr_dwn 304 305func cortex_a53_cluster_pwr_dwn 306 mov x18, x30 307 308#if !TI_AM65X_WORKAROUND 309 /* --------------------------------------------- 310 * Turn off caches. 311 * --------------------------------------------- 312 */ 313 bl cortex_a53_disable_dcache 314#endif 315 316 /* --------------------------------------------- 317 * Flush L1 caches. 318 * --------------------------------------------- 319 */ 320 mov x0, #DCCISW 321 bl dcsw_op_level1 322 323 /* --------------------------------------------- 324 * Disable the optional ACP. 325 * --------------------------------------------- 326 */ 327 bl plat_disable_acp 328 329 /* --------------------------------------------- 330 * Flush L2 caches. 331 * --------------------------------------------- 332 */ 333 mov x0, #DCCISW 334 bl dcsw_op_level2 335 336 /* --------------------------------------------- 337 * Come out of intra cluster coherency 338 * --------------------------------------------- 339 */ 340 mov x30, x18 341 b cortex_a53_disable_smp 342endfunc cortex_a53_cluster_pwr_dwn 343 344#if REPORT_ERRATA 345/* 346 * Errata printing function for Cortex A53. Must follow AAPCS. 347 */ 348func cortex_a53_errata_report 349 stp x8, x30, [sp, #-16]! 350 351 bl cpu_get_rev_var 352 mov x8, x0 353 354 /* 355 * Report all errata. The revision-variant information is passed to 356 * checking functions of each errata. 357 */ 358 report_errata ERRATA_A53_819472, cortex_a53, 819472 359 report_errata ERRATA_A53_824069, cortex_a53, 824069 360 report_errata ERRATA_A53_826319, cortex_a53, 826319 361 report_errata ERRATA_A53_827319, cortex_a53, 827319 362 report_errata ERRATA_A53_835769, cortex_a53, 835769 363 report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint 364 report_errata ERRATA_A53_843419, cortex_a53, 843419 365 report_errata ERRATA_A53_855873, cortex_a53, 855873 366 367 ldp x8, x30, [sp], #16 368 ret 369endfunc cortex_a53_errata_report 370#endif 371 372 /* --------------------------------------------- 373 * This function provides cortex_a53 specific 374 * register information for crash reporting. 375 * It needs to return with x6 pointing to 376 * a list of register names in ascii and 377 * x8 - x15 having values of registers to be 378 * reported. 379 * --------------------------------------------- 380 */ 381.section .rodata.cortex_a53_regs, "aS" 382cortex_a53_regs: /* The ascii list of register names to be reported */ 383 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", \ 384 "cpuactlr_el1", "" 385 386func cortex_a53_cpu_reg_dump 387 adr x6, cortex_a53_regs 388 mrs x8, CORTEX_A53_ECTLR_EL1 389 mrs x9, CORTEX_A53_MERRSR_EL1 390 mrs x10, CORTEX_A53_L2MERRSR_EL1 391 mrs x11, CORTEX_A53_CPUACTLR_EL1 392 ret 393endfunc cortex_a53_cpu_reg_dump 394 395declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \ 396 cortex_a53_reset_func, \ 397 cortex_a53_core_pwr_dwn, \ 398 cortex_a53_cluster_pwr_dwn 399