1/* 2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30#include <arch.h> 31#include <asm_macros.S> 32#include <cortex_a53.h> 33#include <cpu_macros.S> 34#include <plat_macros.S> 35 36 /* --------------------------------------------- 37 * Disable L1 data cache and unified L2 cache 38 * --------------------------------------------- 39 */ 40func cortex_a53_disable_dcache 41 mrs x1, sctlr_el3 42 bic x1, x1, #SCTLR_C_BIT 43 msr sctlr_el3, x1 44 isb 45 ret 46 47 /* --------------------------------------------- 48 * Disable intra-cluster coherency 49 * --------------------------------------------- 50 */ 51func cortex_a53_disable_smp 52 mrs x0, CPUECTLR_EL1 53 bic x0, x0, #CPUECTLR_SMP_BIT 54 msr CPUECTLR_EL1, x0 55 isb 56 dsb sy 57 ret 58 59func cortex_a53_reset_func 60 /* --------------------------------------------- 61 * As a bare minimum enable the SMP bit. 62 * --------------------------------------------- 63 */ 64 mrs x0, CPUECTLR_EL1 65 orr x0, x0, #CPUECTLR_SMP_BIT 66 msr CPUECTLR_EL1, x0 67 isb 68 ret 69 70func cortex_a53_core_pwr_dwn 71 mov x18, x30 72 73 /* --------------------------------------------- 74 * Turn off caches. 75 * --------------------------------------------- 76 */ 77 bl cortex_a53_disable_dcache 78 79 /* --------------------------------------------- 80 * Flush L1 caches. 81 * --------------------------------------------- 82 */ 83 mov x0, #DCCISW 84 bl dcsw_op_level1 85 86 /* --------------------------------------------- 87 * Come out of intra cluster coherency 88 * --------------------------------------------- 89 */ 90 mov x30, x18 91 b cortex_a53_disable_smp 92 93func cortex_a53_cluster_pwr_dwn 94 mov x18, x30 95 96 /* --------------------------------------------- 97 * Turn off caches. 98 * --------------------------------------------- 99 */ 100 bl cortex_a53_disable_dcache 101 102 /* --------------------------------------------- 103 * Flush L1 caches. 104 * --------------------------------------------- 105 */ 106 mov x0, #DCCISW 107 bl dcsw_op_level1 108 109 /* --------------------------------------------- 110 * Disable the optional ACP. 111 * --------------------------------------------- 112 */ 113 bl plat_disable_acp 114 115 /* --------------------------------------------- 116 * Flush L2 caches. 117 * --------------------------------------------- 118 */ 119 mov x0, #DCCISW 120 bl dcsw_op_level2 121 122 /* --------------------------------------------- 123 * Come out of intra cluster coherency 124 * --------------------------------------------- 125 */ 126 mov x30, x18 127 b cortex_a53_disable_smp 128 129 /* --------------------------------------------- 130 * This function provides cortex_a53 specific 131 * register information for crash reporting. 132 * It needs to return with x6 pointing to 133 * a list of register names in ascii and 134 * x8 - x15 having values of registers to be 135 * reported. 136 * --------------------------------------------- 137 */ 138.section .rodata.cortex_a53_regs, "aS" 139cortex_a53_regs: /* The ascii list of register names to be reported */ 140 .asciz "cpuectlr_el1", "" 141 142func cortex_a53_cpu_reg_dump 143 adr x6, cortex_a53_regs 144 mrs x8, CPUECTLR_EL1 145 ret 146 147declare_cpu_ops cortex_a53, CORTEX_A53_MIDR 148