1/* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a520.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex A520 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex A520 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24 /* ---------------------------------------------------- 25 * HW will do the cache maintenance while powering down 26 * ---------------------------------------------------- 27 */ 28func cortex_a520_core_pwr_dwn 29 /* --------------------------------------------------- 30 * Enable CPU power down bit in power control register 31 * --------------------------------------------------- 32 */ 33 sysreg_bit_set CORTEX_A520_CPUPWRCTLR_EL1, CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 34 isb 35 ret 36endfunc cortex_a520_core_pwr_dwn 37 38errata_report_shim cortex_a520 39 40cpu_reset_func_start cortex_a520 41 /* Disable speculative loads */ 42 msr SSBS, xzr 43cpu_reset_func_end cortex_a520 44 45 /* --------------------------------------------- 46 * This function provides Cortex A520 specific 47 * register information for crash reporting. 48 * It needs to return with x6 pointing to 49 * a list of register names in ascii and 50 * x8 - x15 having values of registers to be 51 * reported. 52 * --------------------------------------------- 53 */ 54.section .rodata.cortex_a520_regs, "aS" 55cortex_a520_regs: /* The ascii list of register names to be reported */ 56 .asciz "cpuectlr_el1", "" 57 58func cortex_a520_cpu_reg_dump 59 adr x6, cortex_a520_regs 60 mrs x8, CORTEX_A520_CPUECTLR_EL1 61 ret 62endfunc cortex_a520_cpu_reg_dump 63 64declare_cpu_ops cortex_a520, CORTEX_A520_MIDR, \ 65 cortex_a520_reset_func, \ 66 cortex_a520_core_pwr_dwn 67