1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a520.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14 15.global check_erratum_cortex_a520_2938996 16 17/* Hardware handled coherency */ 18#if HW_ASSISTED_COHERENCY == 0 19#error "Cortex A520 must be compiled with HW_ASSISTED_COHERENCY enabled" 20#endif 21 22/* 64-bit only core */ 23#if CTX_INCLUDE_AARCH32_REGS == 1 24#error "Cortex A520 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 25#endif 26 27cpu_reset_prologue cortex_a520 28 29workaround_reset_start cortex_a520, ERRATUM(2630792), ERRATA_A520_2630792 30 sysreg_bit_set CORTEX_A520_CPUACTLR_EL1, BIT(38) 31workaround_reset_end cortex_a520, ERRATUM(2630792) 32 33check_erratum_ls cortex_a520, ERRATUM(2630792), CPU_REV(0, 1) 34 35workaround_reset_start cortex_a520, ERRATUM(2858100), ERRATA_A520_2858100 36 sysreg_bit_set CORTEX_A520_CPUACTLR_EL1, BIT(29) 37workaround_reset_end cortex_a520, ERRATUM(2858100) 38 39check_erratum_ls cortex_a520, ERRATUM(2858100), CPU_REV(0, 1) 40 41workaround_reset_start cortex_a520, ERRATUM(2900952), ERRATA_DSU_2900952 42 errata_dsu_2900952_wa_apply 43workaround_reset_end cortex_a520, ERRATUM(2900952) 44 45check_erratum_custom_start cortex_a520, ERRATUM(2900952) 46 check_errata_dsu_2900952_applies 47 ret 48check_erratum_custom_end cortex_a520, ERRATUM(2900952) 49 50add_erratum_entry cortex_a520, ERRATUM(2938996), ERRATA_A520_2938996 51 52check_erratum_ls cortex_a520, ERRATUM(2938996), CPU_REV(0, 1) 53 54 /* ---------------------------------------------------- 55 * HW will do the cache maintenance while powering down 56 * ---------------------------------------------------- 57 */ 58func cortex_a520_core_pwr_dwn 59 /* --------------------------------------------------- 60 * Enable CPU power down bit in power control register 61 * --------------------------------------------------- 62 */ 63 sysreg_bit_set CORTEX_A520_CPUPWRCTLR_EL1, CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 64 isb 65 ret 66endfunc cortex_a520_core_pwr_dwn 67 68cpu_reset_func_start cortex_a520 69 /* Disable speculative loads */ 70 msr SSBS, xzr 71 enable_mpmm 72cpu_reset_func_end cortex_a520 73 74 /* --------------------------------------------- 75 * This function provides Cortex A520 specific 76 * register information for crash reporting. 77 * It needs to return with x6 pointing to 78 * a list of register names in ascii and 79 * x8 - x15 having values of registers to be 80 * reported. 81 * --------------------------------------------- 82 */ 83.section .rodata.cortex_a520_regs, "aS" 84cortex_a520_regs: /* The ascii list of register names to be reported */ 85 .asciz "cpuectlr_el1", "" 86 87func cortex_a520_cpu_reg_dump 88 adr x6, cortex_a520_regs 89 mrs x8, CORTEX_A520_CPUECTLR_EL1 90 ret 91endfunc cortex_a520_cpu_reg_dump 92 93declare_cpu_ops cortex_a520, CORTEX_A520_MIDR, \ 94 cortex_a520_reset_func, \ 95 cortex_a520_core_pwr_dwn 96