1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a520.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14.global check_erratum_cortex_a520_2938996 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex A520 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Cortex A520 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26cpu_reset_prologue cortex_a520 27 28workaround_reset_start cortex_a520, ERRATUM(2630792), ERRATA_A520_2630792 29 sysreg_bit_set CORTEX_A520_CPUACTLR_EL1, BIT(38) 30workaround_reset_end cortex_a520, ERRATUM(2630792) 31 32check_erratum_ls cortex_a520, ERRATUM(2630792), CPU_REV(0, 1) 33 34workaround_reset_start cortex_a520, ERRATUM(2858100), ERRATA_A520_2858100 35 sysreg_bit_set CORTEX_A520_CPUACTLR_EL1, BIT(29) 36workaround_reset_end cortex_a520, ERRATUM(2858100) 37 38check_erratum_ls cortex_a520, ERRATUM(2858100), CPU_REV(0, 1) 39 40add_erratum_entry cortex_a520, ERRATUM(2938996), ERRATA_A520_2938996 41 42check_erratum_ls cortex_a520, ERRATUM(2938996), CPU_REV(0, 1) 43 44 /* ---------------------------------------------------- 45 * HW will do the cache maintenance while powering down 46 * ---------------------------------------------------- 47 */ 48func cortex_a520_core_pwr_dwn 49 /* --------------------------------------------------- 50 * Enable CPU power down bit in power control register 51 * --------------------------------------------------- 52 */ 53 sysreg_bit_set CORTEX_A520_CPUPWRCTLR_EL1, CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 54 isb 55 ret 56endfunc cortex_a520_core_pwr_dwn 57 58cpu_reset_func_start cortex_a520 59 /* Disable speculative loads */ 60 msr SSBS, xzr 61 enable_mpmm 62cpu_reset_func_end cortex_a520 63 64 /* --------------------------------------------- 65 * This function provides Cortex A520 specific 66 * register information for crash reporting. 67 * It needs to return with x6 pointing to 68 * a list of register names in ascii and 69 * x8 - x15 having values of registers to be 70 * reported. 71 * --------------------------------------------- 72 */ 73.section .rodata.cortex_a520_regs, "aS" 74cortex_a520_regs: /* The ascii list of register names to be reported */ 75 .asciz "cpuectlr_el1", "" 76 77func cortex_a520_cpu_reg_dump 78 adr x6, cortex_a520_regs 79 mrs x8, CORTEX_A520_CPUECTLR_EL1 80 ret 81endfunc cortex_a520_cpu_reg_dump 82 83declare_cpu_ops cortex_a520, CORTEX_A520_MIDR, \ 84 cortex_a520_reset_func, \ 85 cortex_a520_core_pwr_dwn 86