1dea3d71eSGovindraj Raja/* 2b5477167SBoyan Karatotev * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3dea3d71eSGovindraj Raja * 4dea3d71eSGovindraj Raja * SPDX-License-Identifier: BSD-3-Clause 5dea3d71eSGovindraj Raja */ 6dea3d71eSGovindraj Raja 7dea3d71eSGovindraj Raja#include <arch.h> 8dea3d71eSGovindraj Raja#include <asm_macros.S> 9dea3d71eSGovindraj Raja#include <common/bl_common.h> 10dea3d71eSGovindraj Raja#include <cortex_a520.h> 11dea3d71eSGovindraj Raja#include <cpu_macros.S> 12*efc945f1SArvind Ram Prakash#include <dsu_macros.S> 13dea3d71eSGovindraj Raja#include <plat_macros.S> 14dea3d71eSGovindraj Raja 154a97ff51SArvind Ram Prakash.global check_erratum_cortex_a520_2938996 164a97ff51SArvind Ram Prakash 17dea3d71eSGovindraj Raja/* Hardware handled coherency */ 18dea3d71eSGovindraj Raja#if HW_ASSISTED_COHERENCY == 0 19dea3d71eSGovindraj Raja#error "Cortex A520 must be compiled with HW_ASSISTED_COHERENCY enabled" 20dea3d71eSGovindraj Raja#endif 21dea3d71eSGovindraj Raja 22dea3d71eSGovindraj Raja/* 64-bit only core */ 23dea3d71eSGovindraj Raja#if CTX_INCLUDE_AARCH32_REGS == 1 24dea3d71eSGovindraj Raja#error "Cortex A520 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 25dea3d71eSGovindraj Raja#endif 26dea3d71eSGovindraj Raja 2789dba82dSBoyan Karatotevcpu_reset_prologue cortex_a520 2889dba82dSBoyan Karatotev 29f03bfc30SSona Mathewworkaround_reset_start cortex_a520, ERRATUM(2630792), ERRATA_A520_2630792 30f03bfc30SSona Mathew sysreg_bit_set CORTEX_A520_CPUACTLR_EL1, BIT(38) 31f03bfc30SSona Mathewworkaround_reset_end cortex_a520, ERRATUM(2630792) 32f03bfc30SSona Mathew 33f03bfc30SSona Mathewcheck_erratum_ls cortex_a520, ERRATUM(2630792), CPU_REV(0, 1) 3434db3531SArvind Ram Prakash 3534db3531SArvind Ram Prakashworkaround_reset_start cortex_a520, ERRATUM(2858100), ERRATA_A520_2858100 3634db3531SArvind Ram Prakash sysreg_bit_set CORTEX_A520_CPUACTLR_EL1, BIT(29) 3734db3531SArvind Ram Prakashworkaround_reset_end cortex_a520, ERRATUM(2858100) 3834db3531SArvind Ram Prakash 3934db3531SArvind Ram Prakashcheck_erratum_ls cortex_a520, ERRATUM(2858100), CPU_REV(0, 1) 404a97ff51SArvind Ram Prakash 41*efc945f1SArvind Ram Prakashworkaround_reset_start cortex_a520, ERRATUM(2900952), ERRATA_DSU_2900952 42*efc945f1SArvind Ram Prakash errata_dsu_2900952_wa_apply 43*efc945f1SArvind Ram Prakashworkaround_reset_end cortex_a520, ERRATUM(2900952) 44*efc945f1SArvind Ram Prakash 45*efc945f1SArvind Ram Prakashcheck_erratum_custom_start cortex_a520, ERRATUM(2900952) 46*efc945f1SArvind Ram Prakash check_errata_dsu_2900952_applies 47*efc945f1SArvind Ram Prakash ret 48*efc945f1SArvind Ram Prakashcheck_erratum_custom_end cortex_a520, ERRATUM(2900952) 49*efc945f1SArvind Ram Prakash 5021d068beSBoyan Karatotevadd_erratum_entry cortex_a520, ERRATUM(2938996), ERRATA_A520_2938996 514a97ff51SArvind Ram Prakash 52b5477167SBoyan Karatotevcheck_erratum_ls cortex_a520, ERRATUM(2938996), CPU_REV(0, 1) 534a97ff51SArvind Ram Prakash 54dea3d71eSGovindraj Raja /* ---------------------------------------------------- 55dea3d71eSGovindraj Raja * HW will do the cache maintenance while powering down 56dea3d71eSGovindraj Raja * ---------------------------------------------------- 57dea3d71eSGovindraj Raja */ 58dea3d71eSGovindraj Rajafunc cortex_a520_core_pwr_dwn 59dea3d71eSGovindraj Raja /* --------------------------------------------------- 60dea3d71eSGovindraj Raja * Enable CPU power down bit in power control register 61dea3d71eSGovindraj Raja * --------------------------------------------------- 62dea3d71eSGovindraj Raja */ 63e4883071SGovindraj Raja sysreg_bit_set CORTEX_A520_CPUPWRCTLR_EL1, CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 64dea3d71eSGovindraj Raja isb 65dea3d71eSGovindraj Raja ret 66dea3d71eSGovindraj Rajaendfunc cortex_a520_core_pwr_dwn 67dea3d71eSGovindraj Raja 68e4883071SGovindraj Rajacpu_reset_func_start cortex_a520 69dea3d71eSGovindraj Raja /* Disable speculative loads */ 70dea3d71eSGovindraj Raja msr SSBS, xzr 712590e819SBoyan Karatotev enable_mpmm 72e4883071SGovindraj Rajacpu_reset_func_end cortex_a520 73dea3d71eSGovindraj Raja 74dea3d71eSGovindraj Raja /* --------------------------------------------- 75dea3d71eSGovindraj Raja * This function provides Cortex A520 specific 76dea3d71eSGovindraj Raja * register information for crash reporting. 77dea3d71eSGovindraj Raja * It needs to return with x6 pointing to 78dea3d71eSGovindraj Raja * a list of register names in ascii and 79dea3d71eSGovindraj Raja * x8 - x15 having values of registers to be 80dea3d71eSGovindraj Raja * reported. 81dea3d71eSGovindraj Raja * --------------------------------------------- 82dea3d71eSGovindraj Raja */ 83dea3d71eSGovindraj Raja.section .rodata.cortex_a520_regs, "aS" 84dea3d71eSGovindraj Rajacortex_a520_regs: /* The ascii list of register names to be reported */ 85dea3d71eSGovindraj Raja .asciz "cpuectlr_el1", "" 86dea3d71eSGovindraj Raja 87dea3d71eSGovindraj Rajafunc cortex_a520_cpu_reg_dump 88dea3d71eSGovindraj Raja adr x6, cortex_a520_regs 89dea3d71eSGovindraj Raja mrs x8, CORTEX_A520_CPUECTLR_EL1 90dea3d71eSGovindraj Raja ret 91dea3d71eSGovindraj Rajaendfunc cortex_a520_cpu_reg_dump 92dea3d71eSGovindraj Raja 93dea3d71eSGovindraj Rajadeclare_cpu_ops cortex_a520, CORTEX_A520_MIDR, \ 94dea3d71eSGovindraj Raja cortex_a520_reset_func, \ 95dea3d71eSGovindraj Raja cortex_a520_core_pwr_dwn 96