1/* 2 * Copyright (c) 2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a510.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-A510 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24workaround_reset_start cortex_a510, ERRATUM(1922240), ERRATA_A510_1922240 25 /* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */ 26 mrs x0, CORTEX_A510_CMPXACTLR_EL1 27 mov x1, #3 28 bfi x0, x1, #10, #2 29 msr CORTEX_A510_CMPXACTLR_EL1, x0 30workaround_reset_end cortex_a510, ERRATUM(1922240) 31 32check_erratum_ls cortex_a510, ERRATUM(1922240), CPU_REV(0, 0) 33 34workaround_reset_start cortex_a510, ERRATUM(2041909), ERRATA_A510_2041909 35 /* Apply workaround */ 36 mov x0, xzr 37 msr S3_6_C15_C4_0, x0 38 isb 39 40 mov x0, #0x8500000 41 msr S3_6_C15_C4_2, x0 42 43 mov x0, #0x1F700000 44 movk x0, #0x8, lsl #32 45 msr S3_6_C15_C4_3, x0 46 47 mov x0, #0x3F1 48 movk x0, #0x110, lsl #16 49 msr S3_6_C15_C4_1, x0 50workaround_reset_end cortex_a510, ERRATUM(2041909) 51 52check_erratum_range cortex_a510, ERRATUM(2041909), CPU_REV(0, 2), CPU_REV(0, 2) 53 54workaround_reset_start cortex_a510, ERRATUM(2042739), ERRATA_A510_2042739 55 /* Apply the workaround by disabling ReadPreferUnique. */ 56 mrs x0, CORTEX_A510_CPUECTLR_EL1 57 mov x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE 58 bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, #1 59 msr CORTEX_A510_CPUECTLR_EL1, x0 60workaround_reset_end cortex_a510, ERRATUM(2042739) 61 62check_erratum_ls cortex_a510, ERRATUM(2042739), CPU_REV(0, 2) 63 64workaround_reset_start cortex_a510, ERRATUM(2172148), ERRATA_A510_2172148 65 /* 66 * Force L2 allocation of transient lines by setting 67 * CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01. 68 */ 69 mrs x0, CORTEX_A510_CPUECTLR_EL1 70 mov x1, #1 71 bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2 72 bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2 73 msr CORTEX_A510_CPUECTLR_EL1, x0 74workaround_reset_end cortex_a510, ERRATUM(2172148) 75 76check_erratum_ls cortex_a510, ERRATUM(2172148), CPU_REV(1, 0) 77 78workaround_reset_start cortex_a510, ERRATUM(2218950), ERRATA_A510_2218950 79 /* Source register for BFI */ 80 mov x1, #1 81 82 /* Set bit 18 in CPUACTLR_EL1 */ 83 mrs x0, CORTEX_A510_CPUACTLR_EL1 84 bfi x0, x1, #18, #1 85 msr CORTEX_A510_CPUACTLR_EL1, x0 86 87 /* Set bit 25 in CMPXACTLR_EL1 */ 88 mrs x0, CORTEX_A510_CMPXACTLR_EL1 89 bfi x0, x1, #25, #1 90 msr CORTEX_A510_CMPXACTLR_EL1, x0 91workaround_reset_end cortex_a510, ERRATUM(2218950) 92 93check_erratum_ls cortex_a510, ERRATUM(2218950), CPU_REV(1, 0) 94 95 /* -------------------------------------------------- 96 * This workaround is not a typical errata fix. MPMM 97 * is disabled here, but this conflicts with the BL31 98 * MPMM support. So in addition to simply disabling 99 * the feature, a flag is set in the MPMM library 100 * indicating that it should not be enabled even if 101 * ENABLE_MPMM=1. 102 * -------------------------------------------------- 103 */ 104workaround_reset_start cortex_a510, ERRATUM(2250311), ERRATA_A510_2250311 105 /* Disable MPMM */ 106 mrs x0, CPUMPMMCR_EL3 107 bfm x0, xzr, #0, #0 /* bfc instruction does not work in GCC */ 108 msr CPUMPMMCR_EL3, x0 109 110#if ENABLE_MPMM && IMAGE_BL31 111 /* If ENABLE_MPMM is set, tell the runtime lib to skip enabling it. */ 112 bl mpmm_errata_disable 113#endif 114workaround_reset_end cortex_a510, ERRATUM(2250311) 115 116check_erratum_ls cortex_a510, ERRATUM(2250311), CPU_REV(1, 0) 117 118workaround_reset_start cortex_a510, ERRATUM(2288014), ERRATA_A510_2288014 119 /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */ 120 mrs x0, CORTEX_A510_CPUACTLR_EL1 121 mov x1, #1 122 bfi x0, x1, #18, #1 123 msr CORTEX_A510_CPUACTLR_EL1, x0 124workaround_reset_end cortex_a510, ERRATUM(2288014) 125 126check_erratum_ls cortex_a510, ERRATUM(2288014), CPU_REV(1, 0) 127 128workaround_reset_start cortex_a510, ERRATUM(2347730), ERRATA_A510_2347730 129 /* 130 * Set CPUACTLR_EL1[17] to 1'b1, which disables 131 * specific microarchitectural clock gating 132 * behaviour. 133 */ 134 mrs x1, CORTEX_A510_CPUACTLR_EL1 135 orr x1, x1, CORTEX_A510_CPUACTLR_EL1_BIT_17 136 msr CORTEX_A510_CPUACTLR_EL1, x1 137workaround_reset_end cortex_a510, ERRATUM(2347730) 138 139check_erratum_ls cortex_a510, ERRATUM(2347730), CPU_REV(1, 1) 140 141workaround_reset_start cortex_a510, ERRATUM(2371937), ERRATA_A510_2371937 142 /* 143 * Cacheable atomic operations can be forced 144 * to be executed near by setting 145 * IMP_CPUECTLR_EL1.ATOM=0b010. ATOM is found 146 * in [40:38] of CPUECTLR_EL1. 147 */ 148 mrs x0, CORTEX_A510_CPUECTLR_EL1 149 mov x1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR 150 bfi x0, x1, CORTEX_A510_CPUECTLR_EL1_ATOM, #3 151 msr CORTEX_A510_CPUECTLR_EL1, x0 152workaround_reset_end cortex_a510, ERRATUM(2371937) 153 154check_erratum_ls cortex_a510, ERRATUM(2371937), CPU_REV(1, 1) 155 156workaround_reset_start cortex_a510, ERRATUM(2666669), ERRATA_A510_2666669 157 /* 158 * Workaround will set IMP_CPUACTLR_EL1[38] 159 * to 0b1. 160 */ 161 mrs x1, CORTEX_A510_CPUACTLR_EL1 162 orr x1, x1, CORTEX_A510_CPUACTLR_EL1_BIT_38 163 msr CORTEX_A510_CPUACTLR_EL1, x1 164workaround_reset_end cortex_a510, ERRATUM(2666669) 165 166check_erratum_ls cortex_a510, ERRATUM(2666669), CPU_REV(1, 1) 167 168.global erratum_cortex_a510_2684597_wa 169workaround_runtime_start cortex_a510, ERRATUM(2684597), ERRATA_A510_2684597, CORTEX_A510_MIDR 170 /* 171 * Many assemblers do not yet understand the "tsb csync" mnemonic, 172 * so use the equivalent hint instruction. 173 */ 174 hint #18 /* tsb csync */ 175workaround_runtime_end cortex_a510, ERRATUM(2684597) 176 177check_erratum_ls cortex_a510, ERRATUM(2684597), CPU_REV(1, 2) 178 179/* 180 * ERRATA_DSU_2313941 : 181 * The errata is defined in dsu_helpers.S but applies to cortex_a510 182 * as well. Henceforth creating symbolic names to the already existing errata 183 * workaround functions to get them registered under the Errata Framework. 184 */ 185.equ check_erratum_cortex_a510_2313941, check_errata_dsu_2313941 186.equ erratum_cortex_a510_2313941_wa, errata_dsu_2313941_wa 187add_erratum_entry cortex_a510, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET 188 189 /* ---------------------------------------------------- 190 * HW will do the cache maintenance while powering down 191 * ---------------------------------------------------- 192 */ 193func cortex_a510_core_pwr_dwn 194 /* --------------------------------------------------- 195 * Enable CPU power down bit in power control register 196 * --------------------------------------------------- 197 */ 198 mrs x0, CORTEX_A510_CPUPWRCTLR_EL1 199 orr x0, x0, #CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 200 msr CORTEX_A510_CPUPWRCTLR_EL1, x0 201 isb 202 ret 203endfunc cortex_a510_core_pwr_dwn 204 205errata_report_shim cortex_a510 206 207cpu_reset_func_start cortex_a510 208 /* Disable speculative loads */ 209 msr SSBS, xzr 210cpu_reset_func_end cortex_a510 211 212 /* --------------------------------------------- 213 * This function provides Cortex-A510 specific 214 * register information for crash reporting. 215 * It needs to return with x6 pointing to 216 * a list of register names in ascii and 217 * x8 - x15 having values of registers to be 218 * reported. 219 * --------------------------------------------- 220 */ 221.section .rodata.cortex_a510_regs, "aS" 222cortex_a510_regs: /* The ascii list of register names to be reported */ 223 .asciz "cpuectlr_el1", "" 224 225func cortex_a510_cpu_reg_dump 226 adr x6, cortex_a510_regs 227 mrs x8, CORTEX_A510_CPUECTLR_EL1 228 ret 229endfunc cortex_a510_cpu_reg_dump 230 231declare_cpu_ops cortex_a510, CORTEX_A510_MIDR, \ 232 cortex_a510_reset_func, \ 233 cortex_a510_core_pwr_dwn 234