1/* 2 * Copyright (c) 2022, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a510.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-A510 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24 /* -------------------------------------------------- 25 * Errata Workaround for Cortex-A510 Errata #1922240. 26 * This applies only to revision r0p0 (fixed in r0p1) 27 * x0: variant[4:7] and revision[0:3] of current cpu. 28 * Shall clobber: x0, x1, x17 29 * -------------------------------------------------- 30 */ 31func errata_cortex_a510_1922240_wa 32 /* Check workaround compatibility. */ 33 mov x17, x30 34 bl check_errata_1922240 35 cbz x0, 1f 36 37 /* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */ 38 mrs x0, CORTEX_A510_CMPXACTLR_EL1 39 mov x1, #3 40 bfi x0, x1, #10, #2 41 msr CORTEX_A510_CMPXACTLR_EL1, x0 42 431: 44 ret x17 45endfunc errata_cortex_a510_1922240_wa 46 47func check_errata_1922240 48 /* Applies to r0p0 only */ 49 mov x1, #0x00 50 b cpu_rev_var_ls 51endfunc check_errata_1922240 52 53 /* -------------------------------------------------- 54 * Errata Workaround for Cortex-A510 Errata #2288014. 55 * This applies only to revisions r0p0, r0p1, r0p2, 56 * r0p3 and r1p0. (fixed in r1p1) 57 * x0: variant[4:7] and revision[0:3] of current cpu. 58 * Shall clobber: x0, x1, x17 59 * -------------------------------------------------- 60 */ 61func errata_cortex_a510_2288014_wa 62 /* Check workaround compatibility. */ 63 mov x17, x30 64 bl check_errata_2288014 65 cbz x0, 1f 66 67 /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */ 68 mrs x0, CORTEX_A510_CPUACTLR_EL1 69 mov x1, #1 70 bfi x0, x1, #18, #1 71 msr CORTEX_A510_CPUACTLR_EL1, x0 72 731: 74 ret x17 75endfunc errata_cortex_a510_2288014_wa 76 77func check_errata_2288014 78 /* Applies to r1p0 and below */ 79 mov x1, #0x10 80 b cpu_rev_var_ls 81endfunc check_errata_2288014 82 83 /* -------------------------------------------------- 84 * Errata Workaround for Cortex-A510 Errata #2042739. 85 * This applies only to revisions r0p0, r0p1 and r0p2. 86 * (fixed in r0p3) 87 * x0: variant[4:7] and revision[0:3] of current cpu. 88 * Shall clobber: x0, x1, x17 89 * -------------------------------------------------- 90 */ 91func errata_cortex_a510_2042739_wa 92 /* Check workaround compatibility. */ 93 mov x17, x30 94 bl check_errata_2042739 95 cbz x0, 1f 96 97 /* Apply the workaround by disabling ReadPreferUnique. */ 98 mrs x0, CORTEX_A510_CPUECTLR_EL1 99 mov x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE 100 bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, #1 101 msr CORTEX_A510_CPUECTLR_EL1, x0 102 1031: 104 ret x17 105endfunc errata_cortex_a510_2042739_wa 106 107func check_errata_2042739 108 /* Applies to revisions r0p0 - r0p2 */ 109 mov x1, #0x02 110 b cpu_rev_var_ls 111endfunc check_errata_2042739 112 113 /* -------------------------------------------------- 114 * Errata Workaround for Cortex-A510 Errata #2041909. 115 * This applies only to revision r0p2 and it is fixed in 116 * r0p3. The issue is also present in r0p0 and r0p1 but 117 * there is no workaround in those revisions. 118 * x0: variant[4:7] and revision[0:3] of current cpu. 119 * Shall clobber: x0, x1, x2, x17 120 * -------------------------------------------------- 121 */ 122func errata_cortex_a510_2041909_wa 123 /* Check workaround compatibility. */ 124 mov x17, x30 125 bl check_errata_2041909 126 cbz x0, 1f 127 128 /* Apply workaround */ 129 mov x0, xzr 130 msr S3_6_C15_C4_0, x0 131 isb 132 133 mov x0, #0x8500000 134 msr S3_6_C15_C4_2, x0 135 136 mov x0, #0x1F700000 137 movk x0, #0x8, lsl #32 138 msr S3_6_C15_C4_3, x0 139 140 mov x0, #0x3F1 141 movk x0, #0x110, lsl #16 142 msr S3_6_C15_C4_1, x0 143 isb 144 1451: 146 ret x17 147endfunc errata_cortex_a510_2041909_wa 148 149func check_errata_2041909 150 /* Applies only to revision r0p2 */ 151 mov x1, #0x02 152 mov x2, #0x02 153 b cpu_rev_var_range 154endfunc check_errata_2041909 155 156 /* ---------------------------------------------------- 157 * HW will do the cache maintenance while powering down 158 * ---------------------------------------------------- 159 */ 160func cortex_a510_core_pwr_dwn 161 /* --------------------------------------------------- 162 * Enable CPU power down bit in power control register 163 * --------------------------------------------------- 164 */ 165 mrs x0, CORTEX_A510_CPUPWRCTLR_EL1 166 orr x0, x0, #CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 167 msr CORTEX_A510_CPUPWRCTLR_EL1, x0 168 isb 169 ret 170endfunc cortex_a510_core_pwr_dwn 171 172 /* 173 * Errata printing function for Cortex-A510. Must follow AAPCS. 174 */ 175#if REPORT_ERRATA 176func cortex_a510_errata_report 177 stp x8, x30, [sp, #-16]! 178 179 bl cpu_get_rev_var 180 mov x8, x0 181 182 /* 183 * Report all errata. The revision-variant information is passed to 184 * checking functions of each errata. 185 */ 186 report_errata ERRATA_A510_1922240, cortex_a510, 1922240 187 report_errata ERRATA_A510_2288014, cortex_a510, 2288014 188 report_errata ERRATA_A510_2042739, cortex_a510, 2042739 189 report_errata ERRATA_A510_2041909, cortex_a510, 2041909 190 191 ldp x8, x30, [sp], #16 192 ret 193endfunc cortex_a510_errata_report 194#endif 195 196func cortex_a510_reset_func 197 mov x19, x30 198 199 /* Disable speculative loads */ 200 msr SSBS, xzr 201 isb 202 203 /* Get the CPU revision and stash it in x18. */ 204 bl cpu_get_rev_var 205 mov x18, x0 206 207#if ERRATA_A510_1922240 208 mov x0, x18 209 bl errata_cortex_a510_1922240_wa 210#endif 211 212#if ERRATA_A510_2288014 213 mov x0, x18 214 bl errata_cortex_a510_2288014_wa 215#endif 216 217#if ERRATA_A510_2042739 218 mov x0, x18 219 bl errata_cortex_a510_2042739_wa 220#endif 221 222#if ERRATA_A510_2041909 223 mov x0, x18 224 bl errata_cortex_a510_2041909_wa 225#endif 226 227 ret x19 228endfunc cortex_a510_reset_func 229 230 /* --------------------------------------------- 231 * This function provides Cortex-A510 specific 232 * register information for crash reporting. 233 * It needs to return with x6 pointing to 234 * a list of register names in ascii and 235 * x8 - x15 having values of registers to be 236 * reported. 237 * --------------------------------------------- 238 */ 239.section .rodata.cortex_a510_regs, "aS" 240cortex_a510_regs: /* The ascii list of register names to be reported */ 241 .asciz "cpuectlr_el1", "" 242 243func cortex_a510_cpu_reg_dump 244 adr x6, cortex_a510_regs 245 mrs x8, CORTEX_A510_CPUECTLR_EL1 246 ret 247endfunc cortex_a510_cpu_reg_dump 248 249declare_cpu_ops cortex_a510, CORTEX_A510_MIDR, \ 250 cortex_a510_reset_func, \ 251 cortex_a510_core_pwr_dwn 252