1/* 2 * Copyright (c) 2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <canyon.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Canyon must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Canyon supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24#if ERRATA_SME_POWER_DOWN == 0 25#error "Canyon needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 26#endif 27 28cpu_reset_prologue canyon 29 30cpu_reset_func_start canyon 31 /* ---------------------------------------------------- 32 * Disable speculative loads 33 * ---------------------------------------------------- 34 */ 35 msr SSBS, xzr 36cpu_reset_func_end canyon 37 38func canyon_core_pwr_dwn 39 /* --------------------------------------------------- 40 * Flip CPU power down bit in power control register. 41 * It will be set on powerdown and cleared on wakeup 42 * --------------------------------------------------- 43 */ 44 sysreg_bit_toggle CANYON_IMP_CPUPWRCTLR_EL1, \ 45 CANYON_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 46 isb 47 signal_pabandon_handled 48 ret 49endfunc canyon_core_pwr_dwn 50 51.section .rodata.canyon_regs, "aS" 52canyon_regs: /* The ASCII list of register names to be reported */ 53 .asciz "cpuectlr_el1", "" 54 55func canyon_cpu_reg_dump 56 adr x6, canyon_regs 57 mrs x8, CANYON_IMP_CPUECTLR_EL1 58 ret 59endfunc canyon_cpu_reg_dump 60 61declare_cpu_ops canyon, CANYON_MIDR, \ 62 canyon_reset_func, \ 63 canyon_core_pwr_dwn 64