1/* 2 * Copyright (c) 2023-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_ultra.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Arm C1-Ultra must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Arm C1-Ultra supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if ERRATA_SME_POWER_DOWN == 0 26#error "Arm C1-Ultra needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27#endif 28 29cpu_reset_prologue c1_ultra 30 31workaround_runtime_start c1_ultra, ERRATUM(3324333), ERRATA_C1ULTRA_3324333 32 speculation_barrier 33workaround_runtime_end c1_ultra, ERRATUM(3324333) 34 35check_erratum_ls c1_ultra, ERRATUM(3324333), CPU_REV(0, 0) 36 37workaround_reset_start c1_ultra, ERRATUM(3502731), ERRATA_C1ULTRA_3502731 38 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR4_EL1, BIT(23) 39workaround_reset_end c1_ultra, ERRATUM(3502731) 40 41check_erratum_ls c1_ultra, ERRATUM(3502731), CPU_REV(0, 0) 42 43workaround_reset_start c1_ultra, ERRATUM(3651221), ERRATA_C1ULTRA_3651221 44 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR6_EL1, BIT(41) 45workaround_reset_end c1_ultra, ERRATUM(3651221) 46 47check_erratum_ls c1_ultra, ERRATUM(3651221), CPU_REV(0, 0) 48 49.global check_erratum_c1_ultra_3658374 50add_erratum_entry c1_ultra, ERRATUM(3658374), ERRATA_C1ULTRA_3658374 51check_erratum_ls c1_ultra, ERRATUM(3658374), CPU_REV(1, 0) 52 53workaround_reset_start c1_ultra, ERRATUM(3684152), ERRATA_C1ULTRA_3684152 54 sysreg_bitfield_insert C1_ULTRA_IMP_CPUACTLR_EL1, C1_ULTRA_IMP_CPUACTLR_EL1_LOAD_BIT, \ 55 C1_ULTRA_IMP_CPUACTLR_EL1_LOAD_SHIFT, C1_ULTRA_IMP_CPUACTLR_EL1_LOAD_WIDTH 56workaround_reset_end c1_ultra, ERRATUM(3684152) 57 58check_erratum_ls c1_ultra, ERRATUM(3684152), CPU_REV(0, 0) 59 60workaround_reset_start c1_ultra, ERRATUM(3705939), ERRATA_C1ULTRA_3705939 61 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR_EL1, BIT(48) 62workaround_reset_end c1_ultra, ERRATUM(3705939) 63 64check_erratum_ls c1_ultra, ERRATUM(3705939), CPU_REV(1, 0) 65 66workaround_reset_start c1_ultra, ERRATUM(3815514), ERRATA_C1ULTRA_3815514 67 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR5_EL1, BIT(13) 68workaround_reset_end c1_ultra, ERRATUM(3815514) 69 70check_erratum_ls c1_ultra, ERRATUM(3815514), CPU_REV(1, 0) 71 72workaround_reset_start c1_ultra, ERRATUM(3865171), ERRATA_C1ULTRA_3865171 73 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR2_EL1, BIT(22) 74workaround_reset_end c1_ultra, ERRATUM(3865171) 75 76check_erratum_ls c1_ultra, ERRATUM(3865171), CPU_REV(1, 0) 77 78workaround_reset_start c1_ultra, ERRATUM(3926381), ERRATA_C1ULTRA_3926381 79 /* Convert WFx to NOP */ 80 ldr x0,=0x0 81 msr C1_ULTRA_IMP_CPUPSELR_EL3, x0 82 ldr x0,=0xD503205f 83 msr C1_ULTRA_IMP_CPUPOR_EL3, x0 84 ldr x0,=0xFFFFFFDF 85 msr C1_ULTRA_IMP_CPUPMR_EL3, x0 86 ldr x0,=0x1000002043ff 87 msr C1_ULTRA_IMP_CPUPCR_EL3, x0 88 /* Convert WFxT to NOP */ 89 ldr x0,=0x1 90 msr C1_ULTRA_IMP_CPUPSELR_EL3, x0 91 ldr x0,=0xD5031000 92 msr C1_ULTRA_IMP_CPUPOR_EL3, x0 93 ldr x0,=0xFFFFFFC0 94 msr C1_ULTRA_IMP_CPUPMR_EL3, x0 95 ldr x0,=0x1000002043ff 96 msr C1_ULTRA_IMP_CPUPCR_EL3, x0 97 isb 98workaround_reset_end c1_ultra, ERRATUM(3926381) 99 100check_erratum_range c1_ultra, ERRATUM(3926381), CPU_REV(1, 0), CPU_REV(1, 0) 101 102workaround_reset_start c1_ultra, ERRATUM(4102704), ERRATA_C1ULTRA_4102704 103 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR4_EL1, BIT(23) 104workaround_reset_end c1_ultra, ERRATUM(4102704) 105 106check_erratum_ls c1_ultra, ERRATUM(4102704), CPU_REV(1, 0) 107 108 /* ------------------------------------------------------------- 109 * CVE-2024-7881 is mitigated for C1-Ultra using erratum 3651221 110 * workaround by disabling the affected prefetcher setting 111 * CPUACTLR6_EL1[41]. 112 * ------------------------------------------------------------- 113 */ 114workaround_reset_start c1_ultra, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 115 sysreg_bit_set C1_ULTRA_IMP_CPUACTLR6_EL1, BIT(41) 116workaround_reset_end c1_ultra, CVE(2024, 7881) 117 118check_erratum_ls c1_ultra, CVE(2024, 7881), CPU_REV(0, 0) 119 120cpu_reset_func_start c1_ultra 121 /* ---------------------------------------------------- 122 * Disable speculative loads 123 * ---------------------------------------------------- 124 */ 125 msr SSBS, xzr 126 apply_erratum c1_ultra, ERRATUM(3324333), ERRATA_C1ULTRA_3324333 127 /* model bug: not cleared on reset */ 128 sysreg_bit_clear C1_ULTRA_IMP_CPUPWRCTLR_EL1, \ 129 C1_ULTRA_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 130 enable_mpmm 131cpu_reset_func_end c1_ultra 132 133func c1_ultra_core_pwr_dwn 134 /* --------------------------------------------------- 135 * Flip CPU power down bit in power control register. 136 * It will be set on powerdown and cleared on wakeup 137 * --------------------------------------------------- 138 */ 139 sysreg_bit_toggle C1_ULTRA_IMP_CPUPWRCTLR_EL1, \ 140 C1_ULTRA_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 141 isb 142 signal_pabandon_handled 143 ret 144endfunc c1_ultra_core_pwr_dwn 145 146.section .rodata.c1_ultra_regs, "aS" 147c1_ultra_regs: /* The ASCII list of register names to be reported */ 148 .asciz "cpuectlr_el1", "" 149 150func c1_ultra_cpu_reg_dump 151 adr x6, c1_ultra_regs 152 mrs x8, C1_ULTRA_IMP_CPUECTLR_EL1 153 ret 154endfunc c1_ultra_cpu_reg_dump 155 156declare_cpu_ops c1_ultra, C1_ULTRA_MIDR, \ 157 c1_ultra_reset_func, \ 158 c1_ultra_core_pwr_dwn 159