1/* 2 * Copyright (c) 2024-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_premium.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12#include <wa_cve_2025_0647_cpprctx.h> 13 14#include <plat_macros.S> 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Arm C1-Premium must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Arm C1-Premium supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26#if ERRATA_SME_POWER_DOWN == 0 27#error "Arm C1-Premium needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 28#endif 29 30cpu_reset_prologue c1_premium 31 32workaround_runtime_start c1_premium, ERRATUM(3324333), ERRATA_C1PREMIUM_3324333 33 speculation_barrier 34workaround_runtime_end c1_premium, ERRATUM(3324333) 35 36check_erratum_ls c1_premium, ERRATUM(3324333), CPU_REV(0, 0) 37 38workaround_reset_start c1_premium, ERRATUM(3502731), ERRATA_C1PREMIUM_3502731 39 sysreg_bit_set C1_PREMIUM_IMP_CPUACTLR4_EL1, BIT(23) 40workaround_reset_end c1_premium, ERRATUM(3502731) 41 42check_erratum_ls c1_premium, ERRATUM(3502731), CPU_REV(0, 0) 43 44workaround_reset_start c1_premium, ERRATUM(3651221), ERRATA_C1PREMIUM_3651221 45 sysreg_bit_set C1_PREMIUM_CPUACTLR6_EL1, BIT(41) 46workaround_reset_end c1_premium, ERRATUM(3651221) 47 48check_erratum_ls c1_premium, ERRATUM(3651221), CPU_REV(0, 0) 49 50workaround_reset_start c1_premium, ERRATUM(3684152), ERRATA_C1PREMIUM_3684152 51 sysreg_bitfield_insert C1_PREMIUM_IMP_CPUACTLR_EL1, C1_PREMIUM_IMP_CPUACTLR_EL1_LOAD_BIT, \ 52 C1_PREMIUM_IMP_CPUACTLR_EL1_LOAD_SHIFT, C1_PREMIUM_IMP_CPUACTLR_EL1_LOAD_WIDTH 53workaround_reset_end c1_premium, ERRATUM(3684152) 54 55check_erratum_ls c1_premium, ERRATUM(3684152), CPU_REV(0, 0) 56 57workaround_reset_start c1_premium, ERRATUM(3705939), ERRATA_C1PREMIUM_3705939 58 sysreg_bit_set C1_PREMIUM_IMP_CPUACTLR_EL1, BIT(48) 59workaround_reset_end c1_premium, ERRATUM(3705939) 60 61check_erratum_ls c1_premium, ERRATUM(3705939), CPU_REV(1, 0) 62 63workaround_reset_start c1_premium, ERRATUM(3815514), ERRATA_C1PREMIUM_3815514 64 sysreg_bit_set C1_PREMIUM_IMP_CPUACTLR5_EL1, BIT(13) 65workaround_reset_end c1_premium, ERRATUM(3815514) 66 67check_erratum_ls c1_premium, ERRATUM(3815514), CPU_REV(1, 0) 68 69workaround_reset_start c1_premium, ERRATUM(3865171), ERRATA_C1PREMIUM_3865171 70 sysreg_bit_set C1_PREMIUM_IMP_CPUACTLR2_EL1, BIT(22) 71workaround_reset_end c1_premium, ERRATUM(3865171) 72 73check_erratum_ls c1_premium, ERRATUM(3865171), CPU_REV(1, 0) 74 75workaround_reset_start c1_premium, ERRATUM(3926381), ERRATA_C1PREMIUM_3926381 76 /* Convert WFx to NOP */ 77 ldr x0,=0x0 78 msr C1_PREMIUM_IMP_CPUPSELR_EL3, x0 79 ldr x0,=0xD503205f 80 msr C1_PREMIUM_IMP_CPUPOR_EL3, x0 81 ldr x0,=0xFFFFFFDF 82 msr C1_PREMIUM_IMP_CPUPMR_EL3, x0 83 ldr x0,=0x1000002043ff 84 msr C1_PREMIUM_IMP_CPUPCR_EL3, x0 85 86 /* Convert WFxT to NOP */ 87 ldr x0,=0x1 88 msr C1_PREMIUM_IMP_CPUPSELR_EL3, x0 89 ldr x0,=0xD5031000 90 msr C1_PREMIUM_IMP_CPUPOR_EL3, x0 91 ldr x0,=0xFFFFFFC0 92 msr C1_PREMIUM_IMP_CPUPMR_EL3, x0 93 ldr x0,=0x1000002043ff 94 msr C1_PREMIUM_IMP_CPUPCR_EL3, x0 95 isb 96workaround_reset_end c1_premium, ERRATUM(3926381) 97 98check_erratum_range c1_premium, ERRATUM(3926381), CPU_REV(1, 0), CPU_REV(1, 0) 99 100workaround_reset_start c1_premium, ERRATUM(4102704), ERRATA_C1PREMIUM_4102704 101 sysreg_bit_set C1_PREMIUM_IMP_CPUACTLR4_EL1, BIT(23) 102workaround_reset_end c1_premium, ERRATUM(4102704) 103 104check_erratum_ls c1_premium, ERRATUM(4102704), CPU_REV(1, 0) 105 106 /* --------------------------------------------------------------- 107 * CVE-2024-7881 is mitigated for C1-Premium using erratum 3651221 108 * workaround by disabling the affected prefetcher setting 109 * CPUACTLR6_EL1[41]. 110 * --------------------------------------------------------------- 111 */ 112workaround_reset_start c1_premium, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 113 sysreg_bit_set C1_PREMIUM_CPUACTLR6_EL1, BIT(41) 114workaround_reset_end c1_premium, CVE(2024, 7881) 115 116check_erratum_ls c1_premium, CVE(2024, 7881), CPU_REV(0, 0) 117 118 /* 119 * Instruction patch sequence to trap 'cpp rctx' instructions to EL3. 120 * Enables mitigation for CVE-2025-0647. 121 */ 122workaround_reset_start c1_premium, CVE(2025, 647), WORKAROUND_CVE_2025_0647 123 mov x0, #WA_PATCH_SLOT(3) 124 bl wa_cve_2025_0647_instruction_patch 125workaround_reset_end c1_premium, CVE(2025, 647) 126 127check_erratum_chosen c1_premium, CVE(2025, 647), WORKAROUND_CVE_2025_0647 128 129#if WORKAROUND_CVE_2025_0647 130func c1_premium_impl_defined_el3_handler 131 mov x0, #WA_LS_RCG_EN 132 133 /* See if this call came from trap handler. */ 134 cmp x1, #EC_IMP_DEF_EL3 135 bne wa_cve_2025_0647_do_cpp_wa 136 orr x0, x0, #WA_IS_TRAP_HANDLER 137 b wa_cve_2025_0647_do_cpp_wa 138endfunc c1_premium_impl_defined_el3_handler 139#endif 140 141cpu_reset_func_start c1_premium 142 /* Disable speculative loads */ 143 msr SSBS, xzr 144 apply_erratum c1_premium, ERRATUM(3324333), ERRATA_C1PREMIUM_3324333 145 enable_mpmm 146cpu_reset_func_end c1_premium 147 148func c1_premium_core_pwr_dwn 149 /* --------------------------------------------------- 150 * Flip CPU power down bit in power control register. 151 * It will be set on powerdown and cleared on wakeup. 152 * --------------------------------------------------- 153 */ 154 sysreg_bit_toggle C1_PREMIUM_IMP_CPUPWRCTLR_EL1, \ 155 C1_PREMIUM_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 156 isb 157 signal_pabandon_handled 158 ret 159endfunc c1_premium_core_pwr_dwn 160 161.section .rodata.c1_premium_regs, "aS" 162c1_premium_regs: /* The ASCII list of register names to be reported */ 163 .asciz "cpuectlr_el1", "" 164 165func c1_premium_cpu_reg_dump 166 adr x6, c1_premium_regs 167 mrs x8, C1_PREMIUM_IMP_CPUECTLR_EL1 168 ret 169endfunc c1_premium_cpu_reg_dump 170 171#if WORKAROUND_CVE_2025_0647 172declare_cpu_ops_eh c1_premium, C1_PREMIUM_MIDR, \ 173 c1_premium_reset_func, \ 174 c1_premium_impl_defined_el3_handler, \ 175 c1_premium_core_pwr_dwn 176#else 177declare_cpu_ops c1_premium, C1_PREMIUM_MIDR, \ 178 c1_premium_reset_func, \ 179 c1_premium_core_pwr_dwn 180#endif 181 182