1/* 2 * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <aem_generic.h> 7#include <arch.h> 8#include <asm_macros.S> 9#include <cpu_macros.S> 10 11cpu_reset_prologue aem_generic 12 13func aem_generic_core_pwr_dwn 14 /* --------------------------------------------- 15 * Disable the Data Cache. 16 * --------------------------------------------- 17 */ 18 mrs x1, sctlr_el3 19 bic x1, x1, #SCTLR_C_BIT 20 msr sctlr_el3, x1 21 isb 22 23 /* --------------------------------------------- 24 * AEM model supports L3 caches in which case L2 25 * will be private per core caches and flush 26 * from L1 to L2 is not sufficient. 27 * --------------------------------------------- 28 */ 29 mrs x1, clidr_el1 30 31 /* --------------------------------------------- 32 * Check if L3 cache is implemented. 33 * --------------------------------------------- 34 */ 35 tst x1, ((1 << CLIDR_FIELD_WIDTH) - 1) << CTYPE_SHIFT(3) 36 37 /* --------------------------------------------- 38 * There is no L3 cache, flush L1 to L2 only. 39 * --------------------------------------------- 40 */ 41 mov x0, #DCCISW 42 b.eq dcsw_op_level1 43 44 mov x18, x30 45 46 /* --------------------------------------------- 47 * Flush L1 cache to L2. 48 * --------------------------------------------- 49 */ 50 bl dcsw_op_level1 51 mov x30, x18 52 53 /* --------------------------------------------- 54 * Flush L2 cache to L3. 55 * --------------------------------------------- 56 */ 57 mov x0, #DCCISW 58 b dcsw_op_level2 59endfunc aem_generic_core_pwr_dwn 60 61func aem_generic_cluster_pwr_dwn 62 /* --------------------------------------------- 63 * Disable the Data Cache. 64 * --------------------------------------------- 65 */ 66 mrs x1, sctlr_el3 67 bic x1, x1, #SCTLR_C_BIT 68 msr sctlr_el3, x1 69 isb 70 71 /* --------------------------------------------- 72 * Flush all caches to PoC. 73 * --------------------------------------------- 74 */ 75 mov x0, #DCCISW 76 b dcsw_op_all 77endfunc aem_generic_cluster_pwr_dwn 78 79cpu_reset_func_start aem_generic 80cpu_reset_func_end aem_generic 81 82 /* --------------------------------------------- 83 * This function provides cpu specific 84 * register information for crash reporting. 85 * It needs to return with x6 pointing to 86 * a list of register names in ascii and 87 * x8 - x15 having values of registers to be 88 * reported. 89 * --------------------------------------------- 90 */ 91.section .rodata.aem_generic_regs, "aS" 92aem_generic_regs: /* The ascii list of register names to be reported */ 93 .asciz "" /* no registers to report */ 94 95func aem_generic_cpu_reg_dump 96 adr x6, aem_generic_regs 97 ret 98endfunc aem_generic_cpu_reg_dump 99 100 101/* cpu_ops for Base AEM FVP */ 102declare_cpu_ops aem_generic, BASE_AEM_MIDR, aem_generic_reset_func, \ 103 aem_generic_core_pwr_dwn, \ 104 aem_generic_cluster_pwr_dwn 105 106/* cpu_ops for Foundation FVP */ 107declare_cpu_ops aem_generic, FOUNDATION_AEM_MIDR, aem_generic_reset_func, \ 108 aem_generic_core_pwr_dwn, \ 109 aem_generic_cluster_pwr_dwn 110