19b476841SSoby Mathew/* 2*ef430ff4SAlexei Fedorov * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 39b476841SSoby Mathew * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 59b476841SSoby Mathew */ 6add40351SSoby Mathew#include <aem_generic.h> 79b476841SSoby Mathew#include <arch.h> 89b476841SSoby Mathew#include <asm_macros.S> 99b476841SSoby Mathew#include <cpu_macros.S> 109b476841SSoby Mathew 11add40351SSoby Mathewfunc aem_generic_core_pwr_dwn 12add40351SSoby Mathew /* --------------------------------------------- 13add40351SSoby Mathew * Disable the Data Cache. 14add40351SSoby Mathew * --------------------------------------------- 15add40351SSoby Mathew */ 16add40351SSoby Mathew mrs x1, sctlr_el3 17add40351SSoby Mathew bic x1, x1, #SCTLR_C_BIT 18add40351SSoby Mathew msr sctlr_el3, x1 19add40351SSoby Mathew isb 209b476841SSoby Mathew 21add40351SSoby Mathew /* --------------------------------------------- 22*ef430ff4SAlexei Fedorov * AEM model supports L3 caches in which case L2 23*ef430ff4SAlexei Fedorov * will be private per core caches and flush 24*ef430ff4SAlexei Fedorov * from L1 to L2 is not sufficient. 25add40351SSoby Mathew * --------------------------------------------- 26add40351SSoby Mathew */ 27*ef430ff4SAlexei Fedorov mrs x1, clidr_el1 289b476841SSoby Mathew 29*ef430ff4SAlexei Fedorov /* --------------------------------------------- 30*ef430ff4SAlexei Fedorov * Check if L3 cache is implemented. 31*ef430ff4SAlexei Fedorov * --------------------------------------------- 32*ef430ff4SAlexei Fedorov */ 33*ef430ff4SAlexei Fedorov tst x1, ((1 << CLIDR_FIELD_WIDTH) - 1) << CTYPE_SHIFT(3) 34*ef430ff4SAlexei Fedorov 35*ef430ff4SAlexei Fedorov /* --------------------------------------------- 36*ef430ff4SAlexei Fedorov * There is no L3 cache, flush L1 to L2 only. 37*ef430ff4SAlexei Fedorov * --------------------------------------------- 38*ef430ff4SAlexei Fedorov */ 39*ef430ff4SAlexei Fedorov mov x0, #DCCISW 40*ef430ff4SAlexei Fedorov b.eq dcsw_op_level1 41*ef430ff4SAlexei Fedorov 42*ef430ff4SAlexei Fedorov mov x18, x30 43*ef430ff4SAlexei Fedorov 44*ef430ff4SAlexei Fedorov /* --------------------------------------------- 45*ef430ff4SAlexei Fedorov * Flush L1 cache to L2. 46*ef430ff4SAlexei Fedorov * --------------------------------------------- 47*ef430ff4SAlexei Fedorov */ 48*ef430ff4SAlexei Fedorov bl dcsw_op_level1 49*ef430ff4SAlexei Fedorov mov x30, x18 50*ef430ff4SAlexei Fedorov 51*ef430ff4SAlexei Fedorov /* --------------------------------------------- 52*ef430ff4SAlexei Fedorov * Flush L2 cache to L3. 53*ef430ff4SAlexei Fedorov * --------------------------------------------- 54*ef430ff4SAlexei Fedorov */ 55*ef430ff4SAlexei Fedorov mov x0, #DCCISW 56*ef430ff4SAlexei Fedorov b dcsw_op_level2 57*ef430ff4SAlexei Fedorovendfunc aem_generic_core_pwr_dwn 589b476841SSoby Mathew 59add40351SSoby Mathewfunc aem_generic_cluster_pwr_dwn 60add40351SSoby Mathew /* --------------------------------------------- 61add40351SSoby Mathew * Disable the Data Cache. 62add40351SSoby Mathew * --------------------------------------------- 63add40351SSoby Mathew */ 64add40351SSoby Mathew mrs x1, sctlr_el3 65add40351SSoby Mathew bic x1, x1, #SCTLR_C_BIT 66add40351SSoby Mathew msr sctlr_el3, x1 67add40351SSoby Mathew isb 68add40351SSoby Mathew 69add40351SSoby Mathew /* --------------------------------------------- 70*ef430ff4SAlexei Fedorov * Flush all caches to PoC. 71add40351SSoby Mathew * --------------------------------------------- 72add40351SSoby Mathew */ 73add40351SSoby Mathew mov x0, #DCCISW 74add40351SSoby Mathew b dcsw_op_all 758b779620SKévin Petitendfunc aem_generic_cluster_pwr_dwn 76add40351SSoby Mathew 7712af5ed4SSoby Mathew#if REPORT_ERRATA 7812af5ed4SSoby Mathew/* 7912af5ed4SSoby Mathew * Errata printing function for AEM. Must follow AAPCS. 8012af5ed4SSoby Mathew */ 8112af5ed4SSoby Mathewfunc aem_generic_errata_report 8212af5ed4SSoby Mathew ret 8312af5ed4SSoby Mathewendfunc aem_generic_errata_report 8412af5ed4SSoby Mathew#endif 8512af5ed4SSoby Mathew 86d3f70af6SSoby Mathew /* --------------------------------------------- 87d3f70af6SSoby Mathew * This function provides cpu specific 88d3f70af6SSoby Mathew * register information for crash reporting. 89d3f70af6SSoby Mathew * It needs to return with x6 pointing to 90d3f70af6SSoby Mathew * a list of register names in ascii and 91d3f70af6SSoby Mathew * x8 - x15 having values of registers to be 92d3f70af6SSoby Mathew * reported. 93d3f70af6SSoby Mathew * --------------------------------------------- 94d3f70af6SSoby Mathew */ 956fa11a5eSSoby Mathew.section .rodata.aem_generic_regs, "aS" 966fa11a5eSSoby Mathewaem_generic_regs: /* The ascii list of register names to be reported */ 976fa11a5eSSoby Mathew .asciz "" /* no registers to report */ 986fa11a5eSSoby Mathew 99d3f70af6SSoby Mathewfunc aem_generic_cpu_reg_dump 1006fa11a5eSSoby Mathew adr x6, aem_generic_regs 101d3f70af6SSoby Mathew ret 1028b779620SKévin Petitendfunc aem_generic_cpu_reg_dump 103d3f70af6SSoby Mathew 104add40351SSoby Mathew 105add40351SSoby Mathew/* cpu_ops for Base AEM FVP */ 1065dd9dbb5SJeenu Viswambharandeclare_cpu_ops aem_generic, BASE_AEM_MIDR, CPU_NO_RESET_FUNC, \ 1075dd9dbb5SJeenu Viswambharan aem_generic_core_pwr_dwn, \ 1085dd9dbb5SJeenu Viswambharan aem_generic_cluster_pwr_dwn 1099b476841SSoby Mathew 110add40351SSoby Mathew/* cpu_ops for Foundation FVP */ 1115dd9dbb5SJeenu Viswambharandeclare_cpu_ops aem_generic, FOUNDATION_AEM_MIDR, CPU_NO_RESET_FUNC, \ 1125dd9dbb5SJeenu Viswambharan aem_generic_core_pwr_dwn, \ 1135dd9dbb5SJeenu Viswambharan aem_generic_cluster_pwr_dwn 114