19b476841SSoby Mathew/* 20d020822SBoyan Karatotev * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. 39b476841SSoby Mathew * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 59b476841SSoby Mathew */ 6add40351SSoby Mathew#include <aem_generic.h> 79b476841SSoby Mathew#include <arch.h> 89b476841SSoby Mathew#include <asm_macros.S> 99b476841SSoby Mathew#include <cpu_macros.S> 109b476841SSoby Mathew 11*89dba82dSBoyan Karatotevcpu_reset_prologue aem_generic 12*89dba82dSBoyan Karatotev 13add40351SSoby Mathewfunc aem_generic_core_pwr_dwn 14add40351SSoby Mathew /* --------------------------------------------- 15add40351SSoby Mathew * Disable the Data Cache. 16add40351SSoby Mathew * --------------------------------------------- 17add40351SSoby Mathew */ 18add40351SSoby Mathew mrs x1, sctlr_el3 19add40351SSoby Mathew bic x1, x1, #SCTLR_C_BIT 20add40351SSoby Mathew msr sctlr_el3, x1 21add40351SSoby Mathew isb 229b476841SSoby Mathew 23add40351SSoby Mathew /* --------------------------------------------- 24ef430ff4SAlexei Fedorov * AEM model supports L3 caches in which case L2 25ef430ff4SAlexei Fedorov * will be private per core caches and flush 26ef430ff4SAlexei Fedorov * from L1 to L2 is not sufficient. 27add40351SSoby Mathew * --------------------------------------------- 28add40351SSoby Mathew */ 29ef430ff4SAlexei Fedorov mrs x1, clidr_el1 309b476841SSoby Mathew 31ef430ff4SAlexei Fedorov /* --------------------------------------------- 32ef430ff4SAlexei Fedorov * Check if L3 cache is implemented. 33ef430ff4SAlexei Fedorov * --------------------------------------------- 34ef430ff4SAlexei Fedorov */ 35ef430ff4SAlexei Fedorov tst x1, ((1 << CLIDR_FIELD_WIDTH) - 1) << CTYPE_SHIFT(3) 36ef430ff4SAlexei Fedorov 37ef430ff4SAlexei Fedorov /* --------------------------------------------- 38ef430ff4SAlexei Fedorov * There is no L3 cache, flush L1 to L2 only. 39ef430ff4SAlexei Fedorov * --------------------------------------------- 40ef430ff4SAlexei Fedorov */ 41ef430ff4SAlexei Fedorov mov x0, #DCCISW 42ef430ff4SAlexei Fedorov b.eq dcsw_op_level1 43ef430ff4SAlexei Fedorov 44ef430ff4SAlexei Fedorov mov x18, x30 45ef430ff4SAlexei Fedorov 46ef430ff4SAlexei Fedorov /* --------------------------------------------- 47ef430ff4SAlexei Fedorov * Flush L1 cache to L2. 48ef430ff4SAlexei Fedorov * --------------------------------------------- 49ef430ff4SAlexei Fedorov */ 50ef430ff4SAlexei Fedorov bl dcsw_op_level1 51ef430ff4SAlexei Fedorov mov x30, x18 52ef430ff4SAlexei Fedorov 53ef430ff4SAlexei Fedorov /* --------------------------------------------- 54ef430ff4SAlexei Fedorov * Flush L2 cache to L3. 55ef430ff4SAlexei Fedorov * --------------------------------------------- 56ef430ff4SAlexei Fedorov */ 57ef430ff4SAlexei Fedorov mov x0, #DCCISW 58ef430ff4SAlexei Fedorov b dcsw_op_level2 59ef430ff4SAlexei Fedorovendfunc aem_generic_core_pwr_dwn 609b476841SSoby Mathew 61add40351SSoby Mathewfunc aem_generic_cluster_pwr_dwn 62add40351SSoby Mathew /* --------------------------------------------- 63add40351SSoby Mathew * Disable the Data Cache. 64add40351SSoby Mathew * --------------------------------------------- 65add40351SSoby Mathew */ 66add40351SSoby Mathew mrs x1, sctlr_el3 67add40351SSoby Mathew bic x1, x1, #SCTLR_C_BIT 68add40351SSoby Mathew msr sctlr_el3, x1 69add40351SSoby Mathew isb 70add40351SSoby Mathew 71add40351SSoby Mathew /* --------------------------------------------- 72ef430ff4SAlexei Fedorov * Flush all caches to PoC. 73add40351SSoby Mathew * --------------------------------------------- 74add40351SSoby Mathew */ 75add40351SSoby Mathew mov x0, #DCCISW 76add40351SSoby Mathew b dcsw_op_all 778b779620SKévin Petitendfunc aem_generic_cluster_pwr_dwn 78add40351SSoby Mathew 790d020822SBoyan Karatotevcpu_reset_func_start aem_generic 800d020822SBoyan Karatotevcpu_reset_func_end aem_generic 810d020822SBoyan Karatotev 82d3f70af6SSoby Mathew /* --------------------------------------------- 83d3f70af6SSoby Mathew * This function provides cpu specific 84d3f70af6SSoby Mathew * register information for crash reporting. 85d3f70af6SSoby Mathew * It needs to return with x6 pointing to 86d3f70af6SSoby Mathew * a list of register names in ascii and 87d3f70af6SSoby Mathew * x8 - x15 having values of registers to be 88d3f70af6SSoby Mathew * reported. 89d3f70af6SSoby Mathew * --------------------------------------------- 90d3f70af6SSoby Mathew */ 916fa11a5eSSoby Mathew.section .rodata.aem_generic_regs, "aS" 926fa11a5eSSoby Mathewaem_generic_regs: /* The ascii list of register names to be reported */ 936fa11a5eSSoby Mathew .asciz "" /* no registers to report */ 946fa11a5eSSoby Mathew 95d3f70af6SSoby Mathewfunc aem_generic_cpu_reg_dump 966fa11a5eSSoby Mathew adr x6, aem_generic_regs 97d3f70af6SSoby Mathew ret 988b779620SKévin Petitendfunc aem_generic_cpu_reg_dump 99d3f70af6SSoby Mathew 100add40351SSoby Mathew 101add40351SSoby Mathew/* cpu_ops for Base AEM FVP */ 1020d020822SBoyan Karatotevdeclare_cpu_ops aem_generic, BASE_AEM_MIDR, aem_generic_reset_func, \ 1035dd9dbb5SJeenu Viswambharan aem_generic_core_pwr_dwn, \ 1045dd9dbb5SJeenu Viswambharan aem_generic_cluster_pwr_dwn 1059b476841SSoby Mathew 106add40351SSoby Mathew/* cpu_ops for Foundation FVP */ 1070d020822SBoyan Karatotevdeclare_cpu_ops aem_generic, FOUNDATION_AEM_MIDR, aem_generic_reset_func, \ 1085dd9dbb5SJeenu Viswambharan aem_generic_core_pwr_dwn, \ 1095dd9dbb5SJeenu Viswambharan aem_generic_cluster_pwr_dwn 110