19b476841SSoby Mathew/* 26fa11a5eSSoby Mathew * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. 39b476841SSoby Mathew * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 59b476841SSoby Mathew */ 6add40351SSoby Mathew#include <aem_generic.h> 79b476841SSoby Mathew#include <arch.h> 89b476841SSoby Mathew#include <asm_macros.S> 99b476841SSoby Mathew#include <cpu_macros.S> 109b476841SSoby Mathew 11add40351SSoby Mathewfunc aem_generic_core_pwr_dwn 12add40351SSoby Mathew /* --------------------------------------------- 13add40351SSoby Mathew * Disable the Data Cache. 14add40351SSoby Mathew * --------------------------------------------- 15add40351SSoby Mathew */ 16add40351SSoby Mathew mrs x1, sctlr_el3 17add40351SSoby Mathew bic x1, x1, #SCTLR_C_BIT 18add40351SSoby Mathew msr sctlr_el3, x1 19add40351SSoby Mathew isb 209b476841SSoby Mathew 21add40351SSoby Mathew mov x0, #DCCISW 22add40351SSoby Mathew 23add40351SSoby Mathew /* --------------------------------------------- 24add40351SSoby Mathew * Flush L1 cache to PoU. 25add40351SSoby Mathew * --------------------------------------------- 26add40351SSoby Mathew */ 27add40351SSoby Mathew b dcsw_op_louis 288b779620SKévin Petitendfunc aem_generic_core_pwr_dwn 299b476841SSoby Mathew 309b476841SSoby Mathew 31add40351SSoby Mathewfunc aem_generic_cluster_pwr_dwn 32add40351SSoby Mathew /* --------------------------------------------- 33add40351SSoby Mathew * Disable the Data Cache. 34add40351SSoby Mathew * --------------------------------------------- 35add40351SSoby Mathew */ 36add40351SSoby Mathew mrs x1, sctlr_el3 37add40351SSoby Mathew bic x1, x1, #SCTLR_C_BIT 38add40351SSoby Mathew msr sctlr_el3, x1 39add40351SSoby Mathew isb 40add40351SSoby Mathew 41add40351SSoby Mathew /* --------------------------------------------- 42add40351SSoby Mathew * Flush L1 and L2 caches to PoC. 43add40351SSoby Mathew * --------------------------------------------- 44add40351SSoby Mathew */ 45add40351SSoby Mathew mov x0, #DCCISW 46add40351SSoby Mathew b dcsw_op_all 478b779620SKévin Petitendfunc aem_generic_cluster_pwr_dwn 48add40351SSoby Mathew 49d3f70af6SSoby Mathew /* --------------------------------------------- 50d3f70af6SSoby Mathew * This function provides cpu specific 51d3f70af6SSoby Mathew * register information for crash reporting. 52d3f70af6SSoby Mathew * It needs to return with x6 pointing to 53d3f70af6SSoby Mathew * a list of register names in ascii and 54d3f70af6SSoby Mathew * x8 - x15 having values of registers to be 55d3f70af6SSoby Mathew * reported. 56d3f70af6SSoby Mathew * --------------------------------------------- 57d3f70af6SSoby Mathew */ 586fa11a5eSSoby Mathew.section .rodata.aem_generic_regs, "aS" 596fa11a5eSSoby Mathewaem_generic_regs: /* The ascii list of register names to be reported */ 606fa11a5eSSoby Mathew .asciz "" /* no registers to report */ 616fa11a5eSSoby Mathew 62d3f70af6SSoby Mathewfunc aem_generic_cpu_reg_dump 636fa11a5eSSoby Mathew adr x6, aem_generic_regs 64d3f70af6SSoby Mathew ret 658b779620SKévin Petitendfunc aem_generic_cpu_reg_dump 66d3f70af6SSoby Mathew 67add40351SSoby Mathew 68add40351SSoby Mathew/* cpu_ops for Base AEM FVP */ 695dd9dbb5SJeenu Viswambharandeclare_cpu_ops aem_generic, BASE_AEM_MIDR, CPU_NO_RESET_FUNC, \ 705dd9dbb5SJeenu Viswambharan aem_generic_core_pwr_dwn, \ 715dd9dbb5SJeenu Viswambharan aem_generic_cluster_pwr_dwn 729b476841SSoby Mathew 73add40351SSoby Mathew/* cpu_ops for Foundation FVP */ 745dd9dbb5SJeenu Viswambharandeclare_cpu_ops aem_generic, FOUNDATION_AEM_MIDR, CPU_NO_RESET_FUNC, \ 755dd9dbb5SJeenu Viswambharan aem_generic_core_pwr_dwn, \ 765dd9dbb5SJeenu Viswambharan aem_generic_cluster_pwr_dwn 77