19b476841SSoby Mathew/* 2*6fa11a5eSSoby Mathew * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. 39b476841SSoby Mathew * 49b476841SSoby Mathew * Redistribution and use in source and binary forms, with or without 59b476841SSoby Mathew * modification, are permitted provided that the following conditions are met: 69b476841SSoby Mathew * 79b476841SSoby Mathew * Redistributions of source code must retain the above copyright notice, this 89b476841SSoby Mathew * list of conditions and the following disclaimer. 99b476841SSoby Mathew * 109b476841SSoby Mathew * Redistributions in binary form must reproduce the above copyright notice, 119b476841SSoby Mathew * this list of conditions and the following disclaimer in the documentation 129b476841SSoby Mathew * and/or other materials provided with the distribution. 139b476841SSoby Mathew * 149b476841SSoby Mathew * Neither the name of ARM nor the names of its contributors may be used 159b476841SSoby Mathew * to endorse or promote products derived from this software without specific 169b476841SSoby Mathew * prior written permission. 179b476841SSoby Mathew * 189b476841SSoby Mathew * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 199b476841SSoby Mathew * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 209b476841SSoby Mathew * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 219b476841SSoby Mathew * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 229b476841SSoby Mathew * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 239b476841SSoby Mathew * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 249b476841SSoby Mathew * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 259b476841SSoby Mathew * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 269b476841SSoby Mathew * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 279b476841SSoby Mathew * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 289b476841SSoby Mathew * POSSIBILITY OF SUCH DAMAGE. 299b476841SSoby Mathew */ 30add40351SSoby Mathew#include <aem_generic.h> 319b476841SSoby Mathew#include <arch.h> 329b476841SSoby Mathew#include <asm_macros.S> 339b476841SSoby Mathew#include <cpu_macros.S> 349b476841SSoby Mathew 35add40351SSoby Mathewfunc aem_generic_core_pwr_dwn 36add40351SSoby Mathew /* --------------------------------------------- 37add40351SSoby Mathew * Disable the Data Cache. 38add40351SSoby Mathew * --------------------------------------------- 39add40351SSoby Mathew */ 40add40351SSoby Mathew mrs x1, sctlr_el3 41add40351SSoby Mathew bic x1, x1, #SCTLR_C_BIT 42add40351SSoby Mathew msr sctlr_el3, x1 43add40351SSoby Mathew isb 449b476841SSoby Mathew 45add40351SSoby Mathew mov x0, #DCCISW 46add40351SSoby Mathew 47add40351SSoby Mathew /* --------------------------------------------- 48add40351SSoby Mathew * Flush L1 cache to PoU. 49add40351SSoby Mathew * --------------------------------------------- 50add40351SSoby Mathew */ 51add40351SSoby Mathew b dcsw_op_louis 528b779620SKévin Petitendfunc aem_generic_core_pwr_dwn 539b476841SSoby Mathew 549b476841SSoby Mathew 55add40351SSoby Mathewfunc aem_generic_cluster_pwr_dwn 56add40351SSoby Mathew /* --------------------------------------------- 57add40351SSoby Mathew * Disable the Data Cache. 58add40351SSoby Mathew * --------------------------------------------- 59add40351SSoby Mathew */ 60add40351SSoby Mathew mrs x1, sctlr_el3 61add40351SSoby Mathew bic x1, x1, #SCTLR_C_BIT 62add40351SSoby Mathew msr sctlr_el3, x1 63add40351SSoby Mathew isb 64add40351SSoby Mathew 65add40351SSoby Mathew /* --------------------------------------------- 66add40351SSoby Mathew * Flush L1 and L2 caches to PoC. 67add40351SSoby Mathew * --------------------------------------------- 68add40351SSoby Mathew */ 69add40351SSoby Mathew mov x0, #DCCISW 70add40351SSoby Mathew b dcsw_op_all 718b779620SKévin Petitendfunc aem_generic_cluster_pwr_dwn 72add40351SSoby Mathew 73d3f70af6SSoby Mathew /* --------------------------------------------- 74d3f70af6SSoby Mathew * This function provides cpu specific 75d3f70af6SSoby Mathew * register information for crash reporting. 76d3f70af6SSoby Mathew * It needs to return with x6 pointing to 77d3f70af6SSoby Mathew * a list of register names in ascii and 78d3f70af6SSoby Mathew * x8 - x15 having values of registers to be 79d3f70af6SSoby Mathew * reported. 80d3f70af6SSoby Mathew * --------------------------------------------- 81d3f70af6SSoby Mathew */ 82*6fa11a5eSSoby Mathew.section .rodata.aem_generic_regs, "aS" 83*6fa11a5eSSoby Mathewaem_generic_regs: /* The ascii list of register names to be reported */ 84*6fa11a5eSSoby Mathew .asciz "" /* no registers to report */ 85*6fa11a5eSSoby Mathew 86d3f70af6SSoby Mathewfunc aem_generic_cpu_reg_dump 87*6fa11a5eSSoby Mathew adr x6, aem_generic_regs 88d3f70af6SSoby Mathew ret 898b779620SKévin Petitendfunc aem_generic_cpu_reg_dump 90d3f70af6SSoby Mathew 91add40351SSoby Mathew 92add40351SSoby Mathew/* cpu_ops for Base AEM FVP */ 939b476841SSoby Mathewdeclare_cpu_ops aem_generic, BASE_AEM_MIDR, 1 949b476841SSoby Mathew 95add40351SSoby Mathew/* cpu_ops for Foundation FVP */ 969b476841SSoby Mathewdeclare_cpu_ops aem_generic, FOUNDATION_AEM_MIDR, 1 97