19b476841SSoby Mathew/* 2*0d020822SBoyan Karatotev * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. 39b476841SSoby Mathew * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 59b476841SSoby Mathew */ 6add40351SSoby Mathew#include <aem_generic.h> 79b476841SSoby Mathew#include <arch.h> 89b476841SSoby Mathew#include <asm_macros.S> 99b476841SSoby Mathew#include <cpu_macros.S> 109b476841SSoby Mathew 11add40351SSoby Mathewfunc aem_generic_core_pwr_dwn 12add40351SSoby Mathew /* --------------------------------------------- 13add40351SSoby Mathew * Disable the Data Cache. 14add40351SSoby Mathew * --------------------------------------------- 15add40351SSoby Mathew */ 16add40351SSoby Mathew mrs x1, sctlr_el3 17add40351SSoby Mathew bic x1, x1, #SCTLR_C_BIT 18add40351SSoby Mathew msr sctlr_el3, x1 19add40351SSoby Mathew isb 209b476841SSoby Mathew 21add40351SSoby Mathew /* --------------------------------------------- 22ef430ff4SAlexei Fedorov * AEM model supports L3 caches in which case L2 23ef430ff4SAlexei Fedorov * will be private per core caches and flush 24ef430ff4SAlexei Fedorov * from L1 to L2 is not sufficient. 25add40351SSoby Mathew * --------------------------------------------- 26add40351SSoby Mathew */ 27ef430ff4SAlexei Fedorov mrs x1, clidr_el1 289b476841SSoby Mathew 29ef430ff4SAlexei Fedorov /* --------------------------------------------- 30ef430ff4SAlexei Fedorov * Check if L3 cache is implemented. 31ef430ff4SAlexei Fedorov * --------------------------------------------- 32ef430ff4SAlexei Fedorov */ 33ef430ff4SAlexei Fedorov tst x1, ((1 << CLIDR_FIELD_WIDTH) - 1) << CTYPE_SHIFT(3) 34ef430ff4SAlexei Fedorov 35ef430ff4SAlexei Fedorov /* --------------------------------------------- 36ef430ff4SAlexei Fedorov * There is no L3 cache, flush L1 to L2 only. 37ef430ff4SAlexei Fedorov * --------------------------------------------- 38ef430ff4SAlexei Fedorov */ 39ef430ff4SAlexei Fedorov mov x0, #DCCISW 40ef430ff4SAlexei Fedorov b.eq dcsw_op_level1 41ef430ff4SAlexei Fedorov 42ef430ff4SAlexei Fedorov mov x18, x30 43ef430ff4SAlexei Fedorov 44ef430ff4SAlexei Fedorov /* --------------------------------------------- 45ef430ff4SAlexei Fedorov * Flush L1 cache to L2. 46ef430ff4SAlexei Fedorov * --------------------------------------------- 47ef430ff4SAlexei Fedorov */ 48ef430ff4SAlexei Fedorov bl dcsw_op_level1 49ef430ff4SAlexei Fedorov mov x30, x18 50ef430ff4SAlexei Fedorov 51ef430ff4SAlexei Fedorov /* --------------------------------------------- 52ef430ff4SAlexei Fedorov * Flush L2 cache to L3. 53ef430ff4SAlexei Fedorov * --------------------------------------------- 54ef430ff4SAlexei Fedorov */ 55ef430ff4SAlexei Fedorov mov x0, #DCCISW 56ef430ff4SAlexei Fedorov b dcsw_op_level2 57ef430ff4SAlexei Fedorovendfunc aem_generic_core_pwr_dwn 589b476841SSoby Mathew 59add40351SSoby Mathewfunc aem_generic_cluster_pwr_dwn 60add40351SSoby Mathew /* --------------------------------------------- 61add40351SSoby Mathew * Disable the Data Cache. 62add40351SSoby Mathew * --------------------------------------------- 63add40351SSoby Mathew */ 64add40351SSoby Mathew mrs x1, sctlr_el3 65add40351SSoby Mathew bic x1, x1, #SCTLR_C_BIT 66add40351SSoby Mathew msr sctlr_el3, x1 67add40351SSoby Mathew isb 68add40351SSoby Mathew 69add40351SSoby Mathew /* --------------------------------------------- 70ef430ff4SAlexei Fedorov * Flush all caches to PoC. 71add40351SSoby Mathew * --------------------------------------------- 72add40351SSoby Mathew */ 73add40351SSoby Mathew mov x0, #DCCISW 74add40351SSoby Mathew b dcsw_op_all 758b779620SKévin Petitendfunc aem_generic_cluster_pwr_dwn 76add40351SSoby Mathew 77*0d020822SBoyan Karatotevcpu_reset_func_start aem_generic 78*0d020822SBoyan Karatotevcpu_reset_func_end aem_generic 79*0d020822SBoyan Karatotev 80d3f70af6SSoby Mathew /* --------------------------------------------- 81d3f70af6SSoby Mathew * This function provides cpu specific 82d3f70af6SSoby Mathew * register information for crash reporting. 83d3f70af6SSoby Mathew * It needs to return with x6 pointing to 84d3f70af6SSoby Mathew * a list of register names in ascii and 85d3f70af6SSoby Mathew * x8 - x15 having values of registers to be 86d3f70af6SSoby Mathew * reported. 87d3f70af6SSoby Mathew * --------------------------------------------- 88d3f70af6SSoby Mathew */ 896fa11a5eSSoby Mathew.section .rodata.aem_generic_regs, "aS" 906fa11a5eSSoby Mathewaem_generic_regs: /* The ascii list of register names to be reported */ 916fa11a5eSSoby Mathew .asciz "" /* no registers to report */ 926fa11a5eSSoby Mathew 93d3f70af6SSoby Mathewfunc aem_generic_cpu_reg_dump 946fa11a5eSSoby Mathew adr x6, aem_generic_regs 95d3f70af6SSoby Mathew ret 968b779620SKévin Petitendfunc aem_generic_cpu_reg_dump 97d3f70af6SSoby Mathew 98add40351SSoby Mathew 99add40351SSoby Mathew/* cpu_ops for Base AEM FVP */ 100*0d020822SBoyan Karatotevdeclare_cpu_ops aem_generic, BASE_AEM_MIDR, aem_generic_reset_func, \ 1015dd9dbb5SJeenu Viswambharan aem_generic_core_pwr_dwn, \ 1025dd9dbb5SJeenu Viswambharan aem_generic_cluster_pwr_dwn 1039b476841SSoby Mathew 104add40351SSoby Mathew/* cpu_ops for Foundation FVP */ 105*0d020822SBoyan Karatotevdeclare_cpu_ops aem_generic, FOUNDATION_AEM_MIDR, aem_generic_reset_func, \ 1065dd9dbb5SJeenu Viswambharan aem_generic_core_pwr_dwn, \ 1075dd9dbb5SJeenu Viswambharan aem_generic_cluster_pwr_dwn 108