1/* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <assert_macros.S> 34#include <cpu_data.h> 35#include <cpu_macros.S> 36 37#if IMAGE_BL1 || IMAGE_BL32 38 /* 39 * The reset handler common to all platforms. After a matching 40 * cpu_ops structure entry is found, the correponding reset_handler 41 * in the cpu_ops is invoked. The reset handler is invoked very early 42 * in the boot sequence and it is assumed that we can clobber r0 - r10 43 * without the need to follow AAPCS. 44 * Clobbers: r0 - r10 45 */ 46 .globl reset_handler 47func reset_handler 48 mov r10, lr 49 50 /* The plat_reset_handler can clobber r0 - r9 */ 51 bl plat_reset_handler 52 53 /* Get the matching cpu_ops pointer (clobbers: r0 - r5) */ 54 bl get_cpu_ops_ptr 55 56#if ASM_ASSERTION 57 cmp r0, #0 58 ASM_ASSERT(ne) 59#endif 60 61 /* Get the cpu_ops reset handler */ 62 ldr r1, [r0, #CPU_RESET_FUNC] 63 cmp r1, #0 64 mov lr, r10 65 bxne r1 66 bx lr 67endfunc reset_handler 68 69#endif /* IMAGE_BL1 || IMAGE_BL32 */ 70 71#if IMAGE_BL32 /* The power down core and cluster is needed only in BL32 */ 72 /* 73 * The prepare core power down function for all platforms. After 74 * the cpu_ops pointer is retrieved from cpu_data, the corresponding 75 * pwr_dwn_core in the cpu_ops is invoked. Follows AAPCS. 76 */ 77 .globl prepare_core_pwr_dwn 78func prepare_core_pwr_dwn 79 push {lr} 80 bl _cpu_data 81 pop {lr} 82 83 ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR] 84#if ASM_ASSERTION 85 cmp r1, #0 86 ASM_ASSERT(ne) 87#endif 88 89 /* Get the cpu_ops core_pwr_dwn handler */ 90 ldr r0, [r1, #CPU_PWR_DWN_CORE] 91 bx r0 92endfunc prepare_core_pwr_dwn 93 94 /* 95 * The prepare cluster power down function for all platforms. After 96 * the cpu_ops pointer is retrieved from cpu_data, the corresponding 97 * pwr_dwn_cluster in the cpu_ops is invoked. Follows AAPCS. 98 */ 99 .globl prepare_cluster_pwr_dwn 100func prepare_cluster_pwr_dwn 101 push {lr} 102 bl _cpu_data 103 pop {lr} 104 105 ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR] 106#if ASM_ASSERTION 107 cmp r1, #0 108 ASM_ASSERT(ne) 109#endif 110 111 /* Get the cpu_ops cluster_pwr_dwn handler */ 112 ldr r0, [r1, #CPU_PWR_DWN_CLUSTER] 113 bx r0 114endfunc prepare_cluster_pwr_dwn 115 116 /* 117 * Initializes the cpu_ops_ptr if not already initialized 118 * in cpu_data. This must only be called after the data cache 119 * is enabled. AAPCS is followed. 120 */ 121 .globl init_cpu_ops 122func init_cpu_ops 123 push {r4 - r6, lr} 124 bl _cpu_data 125 mov r6, r0 126 ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR] 127 cmp r1, #0 128 bne 1f 129 bl get_cpu_ops_ptr 130#if ASM_ASSERTION 131 cmp r0, #0 132 ASM_ASSERT(ne) 133#endif 134 str r0, [r6, #CPU_DATA_CPU_OPS_PTR]! 1351: 136 pop {r4 - r6, pc} 137endfunc init_cpu_ops 138 139#endif /* IMAGE_BL32 */ 140 141 /* 142 * The below function returns the cpu_ops structure matching the 143 * midr of the core. It reads the MIDR and finds the matching 144 * entry in cpu_ops entries. Only the implementation and part number 145 * are used to match the entries. 146 * Return : 147 * r0 - The matching cpu_ops pointer on Success 148 * r0 - 0 on failure. 149 * Clobbers: r0 - r5 150 */ 151 .globl get_cpu_ops_ptr 152func get_cpu_ops_ptr 153 /* Get the cpu_ops start and end locations */ 154 ldr r4, =(__CPU_OPS_START__ + CPU_MIDR) 155 ldr r5, =(__CPU_OPS_END__ + CPU_MIDR) 156 157 /* Initialize the return parameter */ 158 mov r0, #0 159 160 /* Read the MIDR_EL1 */ 161 ldcopr r2, MIDR 162 ldr r3, =CPU_IMPL_PN_MASK 163 164 /* Retain only the implementation and part number using mask */ 165 and r2, r2, r3 1661: 167 /* Check if we have reached end of list */ 168 cmp r4, r5 169 bge error_exit 170 171 /* load the midr from the cpu_ops */ 172 ldr r1, [r4], #CPU_OPS_SIZE 173 and r1, r1, r3 174 175 /* Check if midr matches to midr of this core */ 176 cmp r1, r2 177 bne 1b 178 179 /* Subtract the increment and offset to get the cpu-ops pointer */ 180 sub r0, r4, #(CPU_OPS_SIZE + CPU_MIDR) 181error_exit: 182 bx lr 183endfunc get_cpu_ops_ptr 184