1/* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <assert_macros.S> 34#include <cpu_data.h> 35#include <cpu_macros.S> 36 37#if IMAGE_BL1 || IMAGE_BL32 38 /* 39 * The reset handler common to all platforms. After a matching 40 * cpu_ops structure entry is found, the correponding reset_handler 41 * in the cpu_ops is invoked. The reset handler is invoked very early 42 * in the boot sequence and it is assumed that we can clobber r0 - r10 43 * without the need to follow AAPCS. 44 * Clobbers: r0 - r10 45 */ 46 .globl reset_handler 47func reset_handler 48 mov r10, lr 49 50 /* The plat_reset_handler can clobber r0 - r9 */ 51 bl plat_reset_handler 52 53 /* Get the matching cpu_ops pointer (clobbers: r0 - r5) */ 54 bl get_cpu_ops_ptr 55 56#if ASM_ASSERTION 57 cmp r0, #0 58 ASM_ASSERT(ne) 59#endif 60 61 /* Get the cpu_ops reset handler */ 62 ldr r1, [r0, #CPU_RESET_FUNC] 63 cmp r1, #0 64 mov lr, r10 65 bxne r1 66 bx lr 67endfunc reset_handler 68 69#endif /* IMAGE_BL1 || IMAGE_BL32 */ 70 71#if IMAGE_BL32 /* The power down core and cluster is needed only in BL32 */ 72 /* 73 * The prepare core power down function for all platforms. After 74 * the cpu_ops pointer is retrieved from cpu_data, the corresponding 75 * pwr_dwn_core in the cpu_ops is invoked. Follows AAPCS. 76 */ 77 .globl prepare_core_pwr_dwn 78func prepare_core_pwr_dwn 79 /* r12 is pushed to meet the 8 byte stack alignment requirement */ 80 push {r12, lr} 81 bl _cpu_data 82 pop {r12, lr} 83 84 ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR] 85#if ASM_ASSERTION 86 cmp r1, #0 87 ASM_ASSERT(ne) 88#endif 89 90 /* Get the cpu_ops core_pwr_dwn handler */ 91 ldr r0, [r1, #CPU_PWR_DWN_CORE] 92 bx r0 93endfunc prepare_core_pwr_dwn 94 95 /* 96 * The prepare cluster power down function for all platforms. After 97 * the cpu_ops pointer is retrieved from cpu_data, the corresponding 98 * pwr_dwn_cluster in the cpu_ops is invoked. Follows AAPCS. 99 */ 100 .globl prepare_cluster_pwr_dwn 101func prepare_cluster_pwr_dwn 102 /* r12 is pushed to meet the 8 byte stack alignment requirement */ 103 push {r12, lr} 104 bl _cpu_data 105 pop {r12, lr} 106 107 ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR] 108#if ASM_ASSERTION 109 cmp r1, #0 110 ASM_ASSERT(ne) 111#endif 112 113 /* Get the cpu_ops cluster_pwr_dwn handler */ 114 ldr r0, [r1, #CPU_PWR_DWN_CLUSTER] 115 bx r0 116endfunc prepare_cluster_pwr_dwn 117 118 /* 119 * Initializes the cpu_ops_ptr if not already initialized 120 * in cpu_data. This must only be called after the data cache 121 * is enabled. AAPCS is followed. 122 */ 123 .globl init_cpu_ops 124func init_cpu_ops 125 push {r4 - r6, lr} 126 bl _cpu_data 127 mov r6, r0 128 ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR] 129 cmp r1, #0 130 bne 1f 131 bl get_cpu_ops_ptr 132#if ASM_ASSERTION 133 cmp r0, #0 134 ASM_ASSERT(ne) 135#endif 136 str r0, [r6, #CPU_DATA_CPU_OPS_PTR]! 1371: 138 pop {r4 - r6, pc} 139endfunc init_cpu_ops 140 141#endif /* IMAGE_BL32 */ 142 143 /* 144 * The below function returns the cpu_ops structure matching the 145 * midr of the core. It reads the MIDR and finds the matching 146 * entry in cpu_ops entries. Only the implementation and part number 147 * are used to match the entries. 148 * Return : 149 * r0 - The matching cpu_ops pointer on Success 150 * r0 - 0 on failure. 151 * Clobbers: r0 - r5 152 */ 153 .globl get_cpu_ops_ptr 154func get_cpu_ops_ptr 155 /* Get the cpu_ops start and end locations */ 156 ldr r4, =(__CPU_OPS_START__ + CPU_MIDR) 157 ldr r5, =(__CPU_OPS_END__ + CPU_MIDR) 158 159 /* Initialize the return parameter */ 160 mov r0, #0 161 162 /* Read the MIDR_EL1 */ 163 ldcopr r2, MIDR 164 ldr r3, =CPU_IMPL_PN_MASK 165 166 /* Retain only the implementation and part number using mask */ 167 and r2, r2, r3 1681: 169 /* Check if we have reached end of list */ 170 cmp r4, r5 171 bge error_exit 172 173 /* load the midr from the cpu_ops */ 174 ldr r1, [r4], #CPU_OPS_SIZE 175 and r1, r1, r3 176 177 /* Check if midr matches to midr of this core */ 178 cmp r1, r2 179 bne 1b 180 181 /* Subtract the increment and offset to get the cpu-ops pointer */ 182 sub r0, r4, #(CPU_OPS_SIZE + CPU_MIDR) 183error_exit: 184 bx lr 185endfunc get_cpu_ops_ptr 186