1/* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <cortex_a72.h> 10#include <cpu_macros.S> 11#include <debug.h> 12 13 /* --------------------------------------------- 14 * Disable all types of L2 prefetches. 15 * --------------------------------------------- 16 */ 17func cortex_a72_disable_l2_prefetch 18 ldcopr16 r0, r1, CORTEX_A72_ECTLR 19 orr64_imm r0, r1, CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT 20 bic64_imm r0, r1, (CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK | \ 21 CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK) 22 stcopr16 r0, r1, CORTEX_A72_ECTLR 23 isb 24 bx lr 25endfunc cortex_a72_disable_l2_prefetch 26 27 /* --------------------------------------------- 28 * Disable the load-store hardware prefetcher. 29 * --------------------------------------------- 30 */ 31func cortex_a72_disable_hw_prefetcher 32 ldcopr16 r0, r1, CORTEX_A72_CPUACTLR 33 orr64_imm r0, r1, CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH 34 stcopr16 r0, r1, CORTEX_A72_CPUACTLR 35 isb 36 dsb ish 37 bx lr 38endfunc cortex_a72_disable_hw_prefetcher 39 40 /* --------------------------------------------- 41 * Disable intra-cluster coherency 42 * Clobbers: r0-r1 43 * --------------------------------------------- 44 */ 45func cortex_a72_disable_smp 46 ldcopr16 r0, r1, CORTEX_A72_ECTLR 47 bic64_imm r0, r1, CORTEX_A72_ECTLR_SMP_BIT 48 stcopr16 r0, r1, CORTEX_A72_ECTLR 49 bx lr 50endfunc cortex_a72_disable_smp 51 52 /* --------------------------------------------- 53 * Disable debug interfaces 54 * --------------------------------------------- 55 */ 56func cortex_a72_disable_ext_debug 57 mov r0, #1 58 stcopr r0, DBGOSDLR 59 isb 60 dsb sy 61 bx lr 62endfunc cortex_a72_disable_ext_debug 63 64 /* --------------------------------------------------- 65 * Errata Workaround for Cortex A72 Errata #859971. 66 * This applies only to revision <= r0p3 of Cortex A72. 67 * Inputs: 68 * r0: variant[4:7] and revision[0:3] of current cpu. 69 * Shall clobber: r0-r3 70 * --------------------------------------------------- 71 */ 72func errata_a72_859971_wa 73 mov r2,lr 74 bl check_errata_859971 75 mov lr, r2 76 cmp r0, #ERRATA_NOT_APPLIES 77 beq 1f 78 ldcopr16 r0, r1, CORTEX_A72_CPUACTLR 79 orr64_imm r1, r1, CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH 80 stcopr16 r0, r1, CORTEX_A72_CPUACTLR 811: 82 bx lr 83endfunc errata_a72_859971_wa 84 85func check_errata_859971 86 mov r1, #0x03 87 b cpu_rev_var_ls 88endfunc check_errata_859971 89 90func check_errata_cve_2017_5715 91 mov r0, #ERRATA_MISSING 92 bx lr 93endfunc check_errata_cve_2017_5715 94 95 /* ------------------------------------------------- 96 * The CPU Ops reset function for Cortex-A72. 97 * ------------------------------------------------- 98 */ 99func cortex_a72_reset_func 100 mov r5, lr 101 bl cpu_get_rev_var 102 mov r4, r0 103 104#if ERRATA_A72_859971 105 mov r0, r4 106 bl errata_a72_859971_wa 107#endif 108 /* --------------------------------------------- 109 * Enable the SMP bit. 110 * --------------------------------------------- 111 */ 112 ldcopr16 r0, r1, CORTEX_A72_ECTLR 113 orr64_imm r0, r1, CORTEX_A72_ECTLR_SMP_BIT 114 stcopr16 r0, r1, CORTEX_A72_ECTLR 115 isb 116 bx r5 117endfunc cortex_a72_reset_func 118 119 /* ---------------------------------------------------- 120 * The CPU Ops core power down function for Cortex-A72. 121 * ---------------------------------------------------- 122 */ 123func cortex_a72_core_pwr_dwn 124 push {r12, lr} 125 126 /* Assert if cache is enabled */ 127#if ENABLE_ASSERTIONS 128 ldcopr r0, SCTLR 129 tst r0, #SCTLR_C_BIT 130 ASM_ASSERT(eq) 131#endif 132 133 /* --------------------------------------------- 134 * Disable the L2 prefetches. 135 * --------------------------------------------- 136 */ 137 bl cortex_a72_disable_l2_prefetch 138 139 /* --------------------------------------------- 140 * Disable the load-store hardware prefetcher. 141 * --------------------------------------------- 142 */ 143 bl cortex_a72_disable_hw_prefetcher 144 145 /* --------------------------------------------- 146 * Flush L1 caches. 147 * --------------------------------------------- 148 */ 149 mov r0, #DC_OP_CISW 150 bl dcsw_op_level1 151 152 /* --------------------------------------------- 153 * Come out of intra cluster coherency 154 * --------------------------------------------- 155 */ 156 bl cortex_a72_disable_smp 157 158 /* --------------------------------------------- 159 * Force the debug interfaces to be quiescent 160 * --------------------------------------------- 161 */ 162 pop {r12, lr} 163 b cortex_a72_disable_ext_debug 164endfunc cortex_a72_core_pwr_dwn 165 166 /* ------------------------------------------------------- 167 * The CPU Ops cluster power down function for Cortex-A72. 168 * ------------------------------------------------------- 169 */ 170func cortex_a72_cluster_pwr_dwn 171 push {r12, lr} 172 173 /* Assert if cache is enabled */ 174#if ENABLE_ASSERTIONS 175 ldcopr r0, SCTLR 176 tst r0, #SCTLR_C_BIT 177 ASM_ASSERT(eq) 178#endif 179 180 /* --------------------------------------------- 181 * Disable the L2 prefetches. 182 * --------------------------------------------- 183 */ 184 bl cortex_a72_disable_l2_prefetch 185 186 /* --------------------------------------------- 187 * Disable the load-store hardware prefetcher. 188 * --------------------------------------------- 189 */ 190 bl cortex_a72_disable_hw_prefetcher 191 192#if !SKIP_A72_L1_FLUSH_PWR_DWN 193 /* --------------------------------------------- 194 * Flush L1 caches. 195 * --------------------------------------------- 196 */ 197 mov r0, #DC_OP_CISW 198 bl dcsw_op_level1 199#endif 200 201 /* --------------------------------------------- 202 * Disable the optional ACP. 203 * --------------------------------------------- 204 */ 205 bl plat_disable_acp 206 207 /* ------------------------------------------------- 208 * Flush the L2 caches. 209 * ------------------------------------------------- 210 */ 211 mov r0, #DC_OP_CISW 212 bl dcsw_op_level2 213 214 /* --------------------------------------------- 215 * Come out of intra cluster coherency 216 * --------------------------------------------- 217 */ 218 bl cortex_a72_disable_smp 219 220 /* --------------------------------------------- 221 * Force the debug interfaces to be quiescent 222 * --------------------------------------------- 223 */ 224 pop {r12, lr} 225 b cortex_a72_disable_ext_debug 226endfunc cortex_a72_cluster_pwr_dwn 227 228#if REPORT_ERRATA 229/* 230 * Errata printing function for Cortex A72. Must follow AAPCS. 231 */ 232func cortex_a72_errata_report 233 push {r12, lr} 234 235 bl cpu_get_rev_var 236 mov r4, r0 237 238 /* 239 * Report all errata. The revision-variant information is passed to 240 * checking functions of each errata. 241 */ 242 report_errata ERRATA_A72_859971, cortex_a72, 859971 243 report_errata WORKAROUND_CVE_2017_5715, cortex_a72, cve_2017_5715 244 245 pop {r12, lr} 246 bx lr 247endfunc cortex_a72_errata_report 248#endif 249 250declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \ 251 cortex_a72_reset_func, \ 252 cortex_a72_core_pwr_dwn, \ 253 cortex_a72_cluster_pwr_dwn 254