1/* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <cortex_a57.h> 10#include <cpu_macros.S> 11#include <debug.h> 12 13 /* --------------------------------------------- 14 * Disable intra-cluster coherency 15 * Clobbers: r0-r1 16 * --------------------------------------------- 17 */ 18func cortex_a57_disable_smp 19 ldcopr16 r0, r1, CORTEX_A57_ECTLR 20 bic64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT 21 stcopr16 r0, r1, CORTEX_A57_ECTLR 22 bx lr 23endfunc cortex_a57_disable_smp 24 25 /* --------------------------------------------- 26 * Disable all types of L2 prefetches. 27 * Clobbers: r0-r2 28 * --------------------------------------------- 29 */ 30func cortex_a57_disable_l2_prefetch 31 ldcopr16 r0, r1, CORTEX_A57_ECTLR 32 orr64_imm r0, r1, CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT 33 bic64_imm r0, r1, (CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK | \ 34 CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK) 35 stcopr16 r0, r1, CORTEX_A57_ECTLR 36 isb 37 dsb ish 38 bx lr 39endfunc cortex_a57_disable_l2_prefetch 40 41 /* --------------------------------------------- 42 * Disable debug interfaces 43 * --------------------------------------------- 44 */ 45func cortex_a57_disable_ext_debug 46 mov r0, #1 47 stcopr r0, DBGOSDLR 48 isb 49 dsb sy 50 bx lr 51endfunc cortex_a57_disable_ext_debug 52 53 /* -------------------------------------------------- 54 * Errata Workaround for Cortex A57 Errata #806969. 55 * This applies only to revision r0p0 of Cortex A57. 56 * Inputs: 57 * r0: variant[4:7] and revision[0:3] of current cpu. 58 * Shall clobber: r0-r3 59 * -------------------------------------------------- 60 */ 61func errata_a57_806969_wa 62 /* 63 * Compare r0 against revision r0p0 64 */ 65 mov r2, lr 66 bl check_errata_806969 67 mov lr, r2 68 cmp r0, #ERRATA_NOT_APPLIES 69 beq 1f 70 ldcopr16 r0, r1, CORTEX_A57_ACTLR 71 orr64_imm r0, r1, CORTEX_A57_ACTLR_NO_ALLOC_WBWA 72 stcopr16 r0, r1, CORTEX_A57_ACTLR 731: 74 bx lr 75endfunc errata_a57_806969_wa 76 77func check_errata_806969 78 mov r1, #0x00 79 b cpu_rev_var_ls 80endfunc check_errata_806969 81 82 /* --------------------------------------------------- 83 * Errata Workaround for Cortex A57 Errata #813419. 84 * This applies only to revision r0p0 of Cortex A57. 85 * --------------------------------------------------- 86 */ 87func check_errata_813419 88 /* 89 * Even though this is only needed for revision r0p0, it 90 * is always applied due to limitations of the current 91 * errata framework. 92 */ 93 mov r0, #ERRATA_APPLIES 94 bx lr 95endfunc check_errata_813419 96 97 /* --------------------------------------------------- 98 * Errata Workaround for Cortex A57 Errata #813420. 99 * This applies only to revision r0p0 of Cortex A57. 100 * Inputs: 101 * r0: variant[4:7] and revision[0:3] of current cpu. 102 * Shall clobber: r0-r3 103 * --------------------------------------------------- 104 */ 105func errata_a57_813420_wa 106 /* 107 * Compare r0 against revision r0p0 108 */ 109 mov r2, lr 110 bl check_errata_813420 111 mov lr, r2 112 cmp r0, #ERRATA_NOT_APPLIES 113 beq 1f 114 ldcopr16 r0, r1, CORTEX_A57_ACTLR 115 orr64_imm r0, r1, CORTEX_A57_ACTLR_DCC_AS_DCCI 116 stcopr16 r0, r1, CORTEX_A57_ACTLR 1171: 118 bx lr 119endfunc errata_a57_813420_wa 120 121func check_errata_813420 122 mov r1, #0x00 123 b cpu_rev_var_ls 124endfunc check_errata_813420 125 126 /* -------------------------------------------------------------------- 127 * Disable the over-read from the LDNP instruction. 128 * 129 * This applies to all revisions <= r1p2. The performance degradation 130 * observed with LDNP/STNP has been fixed on r1p3 and onwards. 131 * 132 * Inputs: 133 * r0: variant[4:7] and revision[0:3] of current cpu. 134 * Shall clobber: r0-r3 135 * --------------------------------------------------------------------- 136 */ 137func a57_disable_ldnp_overread 138 /* 139 * Compare r0 against revision r1p2 140 */ 141 mov r2, lr 142 bl check_errata_disable_ldnp_overread 143 mov lr, r2 144 cmp r0, #ERRATA_NOT_APPLIES 145 beq 1f 146 ldcopr16 r0, r1, CORTEX_A57_ACTLR 147 orr64_imm r0, r1, CORTEX_A57_ACTLR_DIS_OVERREAD 148 stcopr16 r0, r1, CORTEX_A57_ACTLR 1491: 150 bx lr 151endfunc a57_disable_ldnp_overread 152 153func check_errata_disable_ldnp_overread 154 mov r1, #0x12 155 b cpu_rev_var_ls 156endfunc check_errata_disable_ldnp_overread 157 158 /* --------------------------------------------------- 159 * Errata Workaround for Cortex A57 Errata #826974. 160 * This applies only to revision <= r1p1 of Cortex A57. 161 * Inputs: 162 * r0: variant[4:7] and revision[0:3] of current cpu. 163 * Shall clobber: r0-r3 164 * --------------------------------------------------- 165 */ 166func errata_a57_826974_wa 167 /* 168 * Compare r0 against revision r1p1 169 */ 170 mov r2, lr 171 bl check_errata_826974 172 mov lr, r2 173 cmp r0, #ERRATA_NOT_APPLIES 174 beq 1f 175 ldcopr16 r0, r1, CORTEX_A57_ACTLR 176 orr64_imm r0, r1, CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB 177 stcopr16 r0, r1, CORTEX_A57_ACTLR 1781: 179 bx lr 180endfunc errata_a57_826974_wa 181 182func check_errata_826974 183 mov r1, #0x11 184 b cpu_rev_var_ls 185endfunc check_errata_826974 186 187 /* --------------------------------------------------- 188 * Errata Workaround for Cortex A57 Errata #826977. 189 * This applies only to revision <= r1p1 of Cortex A57. 190 * Inputs: 191 * r0: variant[4:7] and revision[0:3] of current cpu. 192 * Shall clobber: r0-r3 193 * --------------------------------------------------- 194 */ 195func errata_a57_826977_wa 196 /* 197 * Compare r0 against revision r1p1 198 */ 199 mov r2, lr 200 bl check_errata_826977 201 mov lr, r2 202 cmp r0, #ERRATA_NOT_APPLIES 203 beq 1f 204 ldcopr16 r0, r1, CORTEX_A57_ACTLR 205 orr64_imm r0, r1, CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE 206 stcopr16 r0, r1, CORTEX_A57_ACTLR 2071: 208 bx lr 209endfunc errata_a57_826977_wa 210 211func check_errata_826977 212 mov r1, #0x11 213 b cpu_rev_var_ls 214endfunc check_errata_826977 215 216 /* --------------------------------------------------- 217 * Errata Workaround for Cortex A57 Errata #828024. 218 * This applies only to revision <= r1p1 of Cortex A57. 219 * Inputs: 220 * r0: variant[4:7] and revision[0:3] of current cpu. 221 * Shall clobber: r0-r3 222 * --------------------------------------------------- 223 */ 224func errata_a57_828024_wa 225 /* 226 * Compare r0 against revision r1p1 227 */ 228 mov r2, lr 229 bl check_errata_828024 230 mov lr, r2 231 cmp r0, #ERRATA_NOT_APPLIES 232 beq 1f 233 ldcopr16 r0, r1, CORTEX_A57_ACTLR 234 /* 235 * Setting the relevant bits in CORTEX_A57_ACTLR has to be done in 2 236 * instructions here because the resulting bitmask doesn't fit in a 237 * 16-bit value so it cannot be encoded in a single instruction. 238 */ 239 orr64_imm r0, r1, CORTEX_A57_ACTLR_NO_ALLOC_WBWA 240 orr64_imm r0, r1, (CORTEX_A57_ACTLR_DIS_L1_STREAMING | CORTEX_A57_ACTLR_DIS_STREAMING) 241 stcopr16 r0, r1, CORTEX_A57_ACTLR 2421: 243 bx lr 244endfunc errata_a57_828024_wa 245 246func check_errata_828024 247 mov r1, #0x11 248 b cpu_rev_var_ls 249endfunc check_errata_828024 250 251 /* --------------------------------------------------- 252 * Errata Workaround for Cortex A57 Errata #829520. 253 * This applies only to revision <= r1p2 of Cortex A57. 254 * Inputs: 255 * r0: variant[4:7] and revision[0:3] of current cpu. 256 * Shall clobber: r0-r3 257 * --------------------------------------------------- 258 */ 259func errata_a57_829520_wa 260 /* 261 * Compare r0 against revision r1p2 262 */ 263 mov r2, lr 264 bl check_errata_829520 265 mov lr, r2 266 cmp r0, #ERRATA_NOT_APPLIES 267 beq 1f 268 ldcopr16 r0, r1, CORTEX_A57_ACTLR 269 orr64_imm r0, r1, CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR 270 stcopr16 r0, r1, CORTEX_A57_ACTLR 2711: 272 bx lr 273endfunc errata_a57_829520_wa 274 275func check_errata_829520 276 mov r1, #0x12 277 b cpu_rev_var_ls 278endfunc check_errata_829520 279 280 /* --------------------------------------------------- 281 * Errata Workaround for Cortex A57 Errata #833471. 282 * This applies only to revision <= r1p2 of Cortex A57. 283 * Inputs: 284 * r0: variant[4:7] and revision[0:3] of current cpu. 285 * Shall clobber: r0-r3 286 * --------------------------------------------------- 287 */ 288func errata_a57_833471_wa 289 /* 290 * Compare r0 against revision r1p2 291 */ 292 mov r2, lr 293 bl check_errata_833471 294 mov lr, r2 295 cmp r0, #ERRATA_NOT_APPLIES 296 beq 1f 297 ldcopr16 r0, r1, CORTEX_A57_ACTLR 298 orr64_imm r1, r1, CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH 299 stcopr16 r0, r1, CORTEX_A57_ACTLR 3001: 301 bx lr 302endfunc errata_a57_833471_wa 303 304func check_errata_833471 305 mov r1, #0x12 306 b cpu_rev_var_ls 307endfunc check_errata_833471 308 309 /* ------------------------------------------------- 310 * The CPU Ops reset function for Cortex-A57. 311 * Shall clobber: r0-r6 312 * ------------------------------------------------- 313 */ 314func cortex_a57_reset_func 315 mov r5, lr 316 bl cpu_get_rev_var 317 mov r4, r0 318 319#if ERRATA_A57_806969 320 mov r0, r4 321 bl errata_a57_806969_wa 322#endif 323 324#if ERRATA_A57_813420 325 mov r0, r4 326 bl errata_a57_813420_wa 327#endif 328 329#if A57_DISABLE_NON_TEMPORAL_HINT 330 mov r0, r4 331 bl a57_disable_ldnp_overread 332#endif 333 334#if ERRATA_A57_826974 335 mov r0, r4 336 bl errata_a57_826974_wa 337#endif 338 339#if ERRATA_A57_826977 340 mov r0, r4 341 bl errata_a57_826977_wa 342#endif 343 344#if ERRATA_A57_828024 345 mov r0, r4 346 bl errata_a57_828024_wa 347#endif 348 349#if ERRATA_A57_829520 350 mov r0, r4 351 bl errata_a57_829520_wa 352#endif 353 354#if ERRATA_A57_833471 355 mov r0, r4 356 bl errata_a57_833471_wa 357#endif 358 359 /* --------------------------------------------- 360 * Enable the SMP bit. 361 * --------------------------------------------- 362 */ 363 ldcopr16 r0, r1, CORTEX_A57_ECTLR 364 orr64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT 365 stcopr16 r0, r1, CORTEX_A57_ECTLR 366 isb 367 bx r5 368endfunc cortex_a57_reset_func 369 370 /* ---------------------------------------------------- 371 * The CPU Ops core power down function for Cortex-A57. 372 * ---------------------------------------------------- 373 */ 374func cortex_a57_core_pwr_dwn 375 push {r12, lr} 376 377 /* Assert if cache is enabled */ 378#if ASM_ASSERTION 379 ldcopr r0, SCTLR 380 tst r0, #SCTLR_C_BIT 381 ASM_ASSERT(eq) 382#endif 383 384 /* --------------------------------------------- 385 * Disable the L2 prefetches. 386 * --------------------------------------------- 387 */ 388 bl cortex_a57_disable_l2_prefetch 389 390 /* --------------------------------------------- 391 * Flush L1 caches. 392 * --------------------------------------------- 393 */ 394 mov r0, #DC_OP_CISW 395 bl dcsw_op_level1 396 397 /* --------------------------------------------- 398 * Come out of intra cluster coherency 399 * --------------------------------------------- 400 */ 401 bl cortex_a57_disable_smp 402 403 /* --------------------------------------------- 404 * Force the debug interfaces to be quiescent 405 * --------------------------------------------- 406 */ 407 pop {r12, lr} 408 b cortex_a57_disable_ext_debug 409endfunc cortex_a57_core_pwr_dwn 410 411 /* ------------------------------------------------------- 412 * The CPU Ops cluster power down function for Cortex-A57. 413 * Clobbers: r0-r3 414 * ------------------------------------------------------- 415 */ 416func cortex_a57_cluster_pwr_dwn 417 push {r12, lr} 418 419 /* Assert if cache is enabled */ 420#if ASM_ASSERTION 421 ldcopr r0, SCTLR 422 tst r0, #SCTLR_C_BIT 423 ASM_ASSERT(eq) 424#endif 425 426 /* --------------------------------------------- 427 * Disable the L2 prefetches. 428 * --------------------------------------------- 429 */ 430 bl cortex_a57_disable_l2_prefetch 431 432 /* --------------------------------------------- 433 * Flush L1 caches. 434 * --------------------------------------------- 435 */ 436 mov r0, #DC_OP_CISW 437 bl dcsw_op_level1 438 439 /* --------------------------------------------- 440 * Disable the optional ACP. 441 * --------------------------------------------- 442 */ 443 bl plat_disable_acp 444 445 /* --------------------------------------------- 446 * Flush L2 caches. 447 * --------------------------------------------- 448 */ 449 mov r0, #DC_OP_CISW 450 bl dcsw_op_level2 451 452 /* --------------------------------------------- 453 * Come out of intra cluster coherency 454 * --------------------------------------------- 455 */ 456 bl cortex_a57_disable_smp 457 458 /* --------------------------------------------- 459 * Force the debug interfaces to be quiescent 460 * --------------------------------------------- 461 */ 462 pop {r12, lr} 463 b cortex_a57_disable_ext_debug 464endfunc cortex_a57_cluster_pwr_dwn 465 466#if REPORT_ERRATA 467/* 468 * Errata printing function for Cortex A57. Must follow AAPCS. 469 */ 470func cortex_a57_errata_report 471 push {r12, lr} 472 473 bl cpu_get_rev_var 474 mov r4, r0 475 476 /* 477 * Report all errata. The revision-variant information is passed to 478 * checking functions of each errata. 479 */ 480 report_errata ERRATA_A57_806969, cortex_a57, 806969 481 report_errata ERRATA_A57_813419, cortex_a57, 813419 482 report_errata ERRATA_A57_813420, cortex_a57, 813420 483 report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \ 484 disable_ldnp_overread 485 report_errata ERRATA_A57_826974, cortex_a57, 826974 486 report_errata ERRATA_A57_826977, cortex_a57, 826977 487 report_errata ERRATA_A57_828024, cortex_a57, 828024 488 report_errata ERRATA_A57_829520, cortex_a57, 829520 489 report_errata ERRATA_A57_833471, cortex_a57, 833471 490 491 pop {r12, lr} 492 bx lr 493endfunc cortex_a57_errata_report 494#endif 495 496declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \ 497 cortex_a57_reset_func, \ 498 cortex_a57_core_pwr_dwn, \ 499 cortex_a57_cluster_pwr_dwn 500