1d56a8461SEtienne Carriere/* 2*3fb52e41SRyan Everett * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. 3d56a8461SEtienne Carriere * 4d56a8461SEtienne Carriere * SPDX-License-Identifier: BSD-3-Clause 5d56a8461SEtienne Carriere */ 6d56a8461SEtienne Carriere 7d56a8461SEtienne Carriere#include <arch.h> 8d56a8461SEtienne Carriere#include <asm_macros.S> 9d56a8461SEtienne Carriere#include <assert_macros.S> 10d56a8461SEtienne Carriere#include <cortex_a5.h> 11d56a8461SEtienne Carriere#include <cpu_macros.S> 12d56a8461SEtienne Carriere 13d56a8461SEtienne Carriere .macro assert_cache_enabled 14d56a8461SEtienne Carriere#if ENABLE_ASSERTIONS 15d56a8461SEtienne Carriere ldcopr r0, SCTLR 16d56a8461SEtienne Carriere tst r0, #SCTLR_C_BIT 17d56a8461SEtienne Carriere ASM_ASSERT(eq) 18d56a8461SEtienne Carriere#endif 19d56a8461SEtienne Carriere .endm 20d56a8461SEtienne Carriere 21d56a8461SEtienne Carrierefunc cortex_a5_disable_smp 22d56a8461SEtienne Carriere ldcopr r0, ACTLR 23d56a8461SEtienne Carriere bic r0, #CORTEX_A5_ACTLR_SMP_BIT 24d56a8461SEtienne Carriere stcopr r0, ACTLR 25d56a8461SEtienne Carriere isb 26d56a8461SEtienne Carriere dsb sy 27d56a8461SEtienne Carriere bx lr 28d56a8461SEtienne Carriereendfunc cortex_a5_disable_smp 29d56a8461SEtienne Carriere 30d56a8461SEtienne Carrierefunc cortex_a5_enable_smp 31d56a8461SEtienne Carriere ldcopr r0, ACTLR 32d56a8461SEtienne Carriere orr r0, #CORTEX_A5_ACTLR_SMP_BIT 33d56a8461SEtienne Carriere stcopr r0, ACTLR 34d56a8461SEtienne Carriere isb 35d56a8461SEtienne Carriere bx lr 36d56a8461SEtienne Carriereendfunc cortex_a5_enable_smp 37d56a8461SEtienne Carriere 38d56a8461SEtienne Carrierefunc cortex_a5_reset_func 39d56a8461SEtienne Carriere b cortex_a5_enable_smp 40d56a8461SEtienne Carriereendfunc cortex_a5_reset_func 41d56a8461SEtienne Carriere 42d56a8461SEtienne Carrierefunc cortex_a5_core_pwr_dwn 43d56a8461SEtienne Carriere push {r12, lr} 44d56a8461SEtienne Carriere 45d56a8461SEtienne Carriere assert_cache_enabled 46d56a8461SEtienne Carriere 47d56a8461SEtienne Carriere /* Flush L1 cache */ 48d56a8461SEtienne Carriere mov r0, #DC_OP_CISW 49d56a8461SEtienne Carriere bl dcsw_op_level1 50d56a8461SEtienne Carriere 51d56a8461SEtienne Carriere /* Exit cluster coherency */ 52d56a8461SEtienne Carriere pop {r12, lr} 53d56a8461SEtienne Carriere b cortex_a5_disable_smp 54d56a8461SEtienne Carriereendfunc cortex_a5_core_pwr_dwn 55d56a8461SEtienne Carriere 56d56a8461SEtienne Carrierefunc cortex_a5_cluster_pwr_dwn 57d56a8461SEtienne Carriere push {r12, lr} 58d56a8461SEtienne Carriere 59d56a8461SEtienne Carriere assert_cache_enabled 60d56a8461SEtienne Carriere 61d56a8461SEtienne Carriere /* Flush L1 caches */ 62d56a8461SEtienne Carriere mov r0, #DC_OP_CISW 63d56a8461SEtienne Carriere bl dcsw_op_level1 64d56a8461SEtienne Carriere 65d56a8461SEtienne Carriere bl plat_disable_acp 66d56a8461SEtienne Carriere 67d56a8461SEtienne Carriere /* Exit cluster coherency */ 68d56a8461SEtienne Carriere pop {r12, lr} 69d56a8461SEtienne Carriere b cortex_a5_disable_smp 70d56a8461SEtienne Carriereendfunc cortex_a5_cluster_pwr_dwn 71d56a8461SEtienne Carriere 72d56a8461SEtienne Carrieredeclare_cpu_ops cortex_a5, CORTEX_A5_MIDR, \ 73d56a8461SEtienne Carriere cortex_a5_reset_func, \ 74d56a8461SEtienne Carriere cortex_a5_core_pwr_dwn, \ 75d56a8461SEtienne Carriere cortex_a5_cluster_pwr_dwn 76