1/* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <assert_macros.S> 10#include <cortex_a17.h> 11#include <cpu_macros.S> 12 13 .macro assert_cache_enabled 14#if ENABLE_ASSERTIONS 15 ldcopr r0, SCTLR 16 tst r0, #SCTLR_C_BIT 17 ASM_ASSERT(eq) 18#endif 19 .endm 20 21func cortex_a17_disable_smp 22 ldcopr r0, ACTLR 23 bic r0, #CORTEX_A17_ACTLR_SMP_BIT 24 stcopr r0, ACTLR 25 isb 26 dsb sy 27 bx lr 28endfunc cortex_a17_disable_smp 29 30func cortex_a17_enable_smp 31 ldcopr r0, ACTLR 32 orr r0, #CORTEX_A17_ACTLR_SMP_BIT 33 stcopr r0, ACTLR 34 isb 35 bx lr 36endfunc cortex_a17_enable_smp 37 38func check_errata_cve_2017_5715 39#if WORKAROUND_CVE_2017_5715 40 mov r0, #ERRATA_APPLIES 41#else 42 mov r0, #ERRATA_MISSING 43#endif 44 bx lr 45endfunc check_errata_cve_2017_5715 46 47#if REPORT_ERRATA 48/* 49 * Errata printing function for Cortex A17. Must follow AAPCS. 50 */ 51func cortex_a17_errata_report 52 push {r12, lr} 53 54 bl cpu_get_rev_var 55 mov r4, r0 56 57 /* 58 * Report all errata. The revision-variant information is passed to 59 * checking functions of each errata. 60 */ 61 report_errata WORKAROUND_CVE_2017_5715, cortex_a17, cve_2017_5715 62 63 pop {r12, lr} 64 bx lr 65endfunc cortex_a17_errata_report 66#endif 67 68func cortex_a17_reset_func 69#if IMAGE_BL32 && WORKAROUND_CVE_2017_5715 70 ldr r0, =workaround_bpiall_runtime_exceptions 71 stcopr r0, VBAR 72 stcopr r0, MVBAR 73 /* isb will be applied in the course of the reset func */ 74#endif 75 b cortex_a17_enable_smp 76endfunc cortex_a17_reset_func 77 78func cortex_a17_core_pwr_dwn 79 push {r12, lr} 80 81 assert_cache_enabled 82 83 /* Flush L1 cache */ 84 mov r0, #DC_OP_CISW 85 bl dcsw_op_level1 86 87 /* Exit cluster coherency */ 88 pop {r12, lr} 89 b cortex_a17_disable_smp 90endfunc cortex_a17_core_pwr_dwn 91 92func cortex_a17_cluster_pwr_dwn 93 push {r12, lr} 94 95 assert_cache_enabled 96 97 /* Flush L1 caches */ 98 mov r0, #DC_OP_CISW 99 bl dcsw_op_level1 100 101 bl plat_disable_acp 102 103 /* Exit cluster coherency */ 104 pop {r12, lr} 105 b cortex_a17_disable_smp 106endfunc cortex_a17_cluster_pwr_dwn 107 108declare_cpu_ops cortex_a17, CORTEX_A17_MIDR, \ 109 cortex_a17_reset_func, \ 110 cortex_a17_core_pwr_dwn, \ 111 cortex_a17_cluster_pwr_dwn 112