1*e33b78a6SSoby Mathew/* 2*e33b78a6SSoby Mathew * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3*e33b78a6SSoby Mathew * 4*e33b78a6SSoby Mathew * Redistribution and use in source and binary forms, with or without 5*e33b78a6SSoby Mathew * modification, are permitted provided that the following conditions are met: 6*e33b78a6SSoby Mathew * 7*e33b78a6SSoby Mathew * Redistributions of source code must retain the above copyright notice, this 8*e33b78a6SSoby Mathew * list of conditions and the following disclaimer. 9*e33b78a6SSoby Mathew * 10*e33b78a6SSoby Mathew * Redistributions in binary form must reproduce the above copyright notice, 11*e33b78a6SSoby Mathew * this list of conditions and the following disclaimer in the documentation 12*e33b78a6SSoby Mathew * and/or other materials provided with the distribution. 13*e33b78a6SSoby Mathew * 14*e33b78a6SSoby Mathew * Neither the name of ARM nor the names of its contributors may be used 15*e33b78a6SSoby Mathew * to endorse or promote products derived from this software without specific 16*e33b78a6SSoby Mathew * prior written permission. 17*e33b78a6SSoby Mathew * 18*e33b78a6SSoby Mathew * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*e33b78a6SSoby Mathew * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*e33b78a6SSoby Mathew * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*e33b78a6SSoby Mathew * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*e33b78a6SSoby Mathew * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*e33b78a6SSoby Mathew * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*e33b78a6SSoby Mathew * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*e33b78a6SSoby Mathew * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*e33b78a6SSoby Mathew * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*e33b78a6SSoby Mathew * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*e33b78a6SSoby Mathew * POSSIBILITY OF SUCH DAMAGE. 29*e33b78a6SSoby Mathew */ 30*e33b78a6SSoby Mathew#include <aem_generic.h> 31*e33b78a6SSoby Mathew#include <arch.h> 32*e33b78a6SSoby Mathew#include <asm_macros.S> 33*e33b78a6SSoby Mathew#include <assert_macros.S> 34*e33b78a6SSoby Mathew#include <cpu_macros.S> 35*e33b78a6SSoby Mathew 36*e33b78a6SSoby Mathewfunc aem_generic_core_pwr_dwn 37*e33b78a6SSoby Mathew /* Assert if cache is enabled */ 38*e33b78a6SSoby Mathew#if ASM_ASSERTION 39*e33b78a6SSoby Mathew ldcopr r0, SCTLR 40*e33b78a6SSoby Mathew tst r0, #SCTLR_C_BIT 41*e33b78a6SSoby Mathew ASM_ASSERT(eq) 42*e33b78a6SSoby Mathew#endif 43*e33b78a6SSoby Mathew /* --------------------------------------------- 44*e33b78a6SSoby Mathew * Flush L1 cache to PoU. 45*e33b78a6SSoby Mathew * --------------------------------------------- 46*e33b78a6SSoby Mathew */ 47*e33b78a6SSoby Mathew mov r0, #DC_OP_CISW 48*e33b78a6SSoby Mathew b dcsw_op_louis 49*e33b78a6SSoby Mathewendfunc aem_generic_core_pwr_dwn 50*e33b78a6SSoby Mathew 51*e33b78a6SSoby Mathew 52*e33b78a6SSoby Mathewfunc aem_generic_cluster_pwr_dwn 53*e33b78a6SSoby Mathew /* Assert if cache is enabled */ 54*e33b78a6SSoby Mathew#if ASM_ASSERTION 55*e33b78a6SSoby Mathew ldcopr r0, SCTLR 56*e33b78a6SSoby Mathew tst r0, #SCTLR_C_BIT 57*e33b78a6SSoby Mathew ASM_ASSERT(eq) 58*e33b78a6SSoby Mathew#endif 59*e33b78a6SSoby Mathew /* --------------------------------------------- 60*e33b78a6SSoby Mathew * Flush L1 and L2 caches to PoC. 61*e33b78a6SSoby Mathew * --------------------------------------------- 62*e33b78a6SSoby Mathew */ 63*e33b78a6SSoby Mathew mov r0, #DC_OP_CISW 64*e33b78a6SSoby Mathew b dcsw_op_all 65*e33b78a6SSoby Mathewendfunc aem_generic_cluster_pwr_dwn 66*e33b78a6SSoby Mathew 67*e33b78a6SSoby Mathew/* cpu_ops for Base AEM FVP */ 68*e33b78a6SSoby Mathewdeclare_cpu_ops aem_generic, BASE_AEM_MIDR, 1 69