1e33b78a6SSoby Mathew/* 2*0d020822SBoyan Karatotev * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved. 3e33b78a6SSoby Mathew * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5e33b78a6SSoby Mathew */ 6e33b78a6SSoby Mathew#include <aem_generic.h> 7e33b78a6SSoby Mathew#include <arch.h> 8e33b78a6SSoby Mathew#include <asm_macros.S> 9e33b78a6SSoby Mathew#include <assert_macros.S> 10e33b78a6SSoby Mathew#include <cpu_macros.S> 11e33b78a6SSoby Mathew 12e33b78a6SSoby Mathewfunc aem_generic_core_pwr_dwn 13e33b78a6SSoby Mathew /* Assert if cache is enabled */ 14044bb2faSAntonio Nino Diaz#if ENABLE_ASSERTIONS 15e33b78a6SSoby Mathew ldcopr r0, SCTLR 16e33b78a6SSoby Mathew tst r0, #SCTLR_C_BIT 17e33b78a6SSoby Mathew ASM_ASSERT(eq) 18e33b78a6SSoby Mathew#endif 19e33b78a6SSoby Mathew /* --------------------------------------------- 20e33b78a6SSoby Mathew * Flush L1 cache to PoU. 21e33b78a6SSoby Mathew * --------------------------------------------- 22e33b78a6SSoby Mathew */ 23e33b78a6SSoby Mathew mov r0, #DC_OP_CISW 24e33b78a6SSoby Mathew b dcsw_op_louis 25e33b78a6SSoby Mathewendfunc aem_generic_core_pwr_dwn 26e33b78a6SSoby Mathew 27e33b78a6SSoby Mathew 28e33b78a6SSoby Mathewfunc aem_generic_cluster_pwr_dwn 29e33b78a6SSoby Mathew /* Assert if cache is enabled */ 30044bb2faSAntonio Nino Diaz#if ENABLE_ASSERTIONS 31e33b78a6SSoby Mathew ldcopr r0, SCTLR 32e33b78a6SSoby Mathew tst r0, #SCTLR_C_BIT 33e33b78a6SSoby Mathew ASM_ASSERT(eq) 34e33b78a6SSoby Mathew#endif 35e33b78a6SSoby Mathew /* --------------------------------------------- 36e33b78a6SSoby Mathew * Flush L1 and L2 caches to PoC. 37e33b78a6SSoby Mathew * --------------------------------------------- 38e33b78a6SSoby Mathew */ 39e33b78a6SSoby Mathew mov r0, #DC_OP_CISW 40e33b78a6SSoby Mathew b dcsw_op_all 41e33b78a6SSoby Mathewendfunc aem_generic_cluster_pwr_dwn 42e33b78a6SSoby Mathew 43*0d020822SBoyan Karatotevfunc aem_generic_reset_func 44*0d020822SBoyan Karatotev bx lr 45*0d020822SBoyan Karatotevendfunc aem_generic_reset_func 4612af5ed4SSoby Mathew 47e33b78a6SSoby Mathew/* cpu_ops for Base AEM FVP */ 48*0d020822SBoyan Karatotevdeclare_cpu_ops aem_generic, BASE_AEM_MIDR, aem_generic_reset_func, \ 495dd9dbb5SJeenu Viswambharan aem_generic_core_pwr_dwn, \ 505dd9dbb5SJeenu Viswambharan aem_generic_cluster_pwr_dwn 51