1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <drivers/coreboot/cbmem_console.h> 11 #include <common/debug.h> 12 #include <lib/coreboot.h> 13 #include <lib/mmio.h> 14 #include <lib/xlat_tables/xlat_tables_v2.h> 15 16 /* 17 * Structures describing coreboot's in-memory descriptor tables. See 18 * <coreboot>/src/commonlib/include/commonlib/coreboot_tables.h for 19 * canonical implementation. 20 */ 21 22 typedef struct { 23 char signature[4]; 24 uint32_t header_bytes; 25 uint32_t header_checksum; 26 uint32_t table_bytes; 27 uint32_t table_checksum; 28 uint32_t table_entries; 29 } cb_header_t; 30 31 typedef enum { 32 CB_TAG_SERIAL = 0xf, 33 CB_TAG_CBMEM_CONSOLE = 0x17, 34 } cb_tag_t; 35 36 typedef struct { 37 uint32_t tag; 38 uint32_t size; 39 union { 40 coreboot_serial_t serial; 41 uint64_t uint64; 42 }; 43 } cb_entry_t; 44 45 coreboot_serial_t coreboot_serial; 46 47 /* 48 * The coreboot table is parsed before the MMU is enabled (i.e. with strongly 49 * ordered memory), so we cannot make unaligned accesses. The table entries 50 * immediately follow one another without padding, so nothing after the header 51 * is guaranteed to be naturally aligned. Therefore, we need to define safety 52 * functions that can read unaligned integers. 53 */ 54 static uint32_t read_le32(uint32_t *p) 55 { 56 uintptr_t addr = (uintptr_t)p; 57 return mmio_read_8(addr) | 58 mmio_read_8(addr + 1) << 8 | 59 mmio_read_8(addr + 2) << 16 | 60 mmio_read_8(addr + 3) << 24; 61 } 62 static uint64_t read_le64(uint64_t *p) 63 { 64 return read_le32((void *)p) | (uint64_t)read_le32((void *)p + 4) << 32; 65 } 66 67 static void expand_and_mmap(uintptr_t baseaddr, size_t size) 68 { 69 uintptr_t pageaddr = round_down(baseaddr, PAGE_SIZE); 70 size_t expanded = round_up(baseaddr - pageaddr + size, PAGE_SIZE); 71 mmap_add_region(pageaddr, pageaddr, expanded, 72 MT_MEMORY | MT_RW | MT_NS | MT_EXECUTE_NEVER); 73 } 74 75 static void setup_cbmem_console(uintptr_t baseaddr) 76 { 77 static console_cbmc_t console; 78 assert(!console.console.base); /* should only have one CBMEM console */ 79 80 /* CBMEM console structure stores its size in first header field. */ 81 uint32_t size = *(uint32_t *)baseaddr; 82 expand_and_mmap(baseaddr, size); 83 console_cbmc_register(baseaddr, &console); 84 console_set_scope(&console.console, CONSOLE_FLAG_BOOT | 85 CONSOLE_FLAG_RUNTIME | 86 CONSOLE_FLAG_CRASH); 87 } 88 89 void coreboot_table_setup(void *base) 90 { 91 cb_header_t *header = base; 92 void *ptr; 93 int i; 94 95 if (strncmp(header->signature, "LBIO", 4)) { 96 ERROR("coreboot table signature corrupt!\n"); 97 return; 98 } 99 100 ptr = base + header->header_bytes; 101 for (i = 0; i < header->table_entries; i++) { 102 cb_entry_t *entry = ptr; 103 104 if (ptr - base >= header->header_bytes + header->table_bytes) { 105 ERROR("coreboot table exceeds its bounds!\n"); 106 break; 107 } 108 109 switch (read_le32(&entry->tag)) { 110 case CB_TAG_SERIAL: 111 memcpy(&coreboot_serial, &entry->serial, 112 sizeof(coreboot_serial)); 113 break; 114 case CB_TAG_CBMEM_CONSOLE: 115 setup_cbmem_console(read_le64(&entry->uint64)); 116 break; 117 default: 118 /* There are many tags TF doesn't need to care about. */ 119 break; 120 } 121 122 ptr += read_le32(&entry->size); 123 } 124 } 125