1/* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <assert_macros.S> 34 35 .globl smc 36 .globl zeromem 37 .globl memcpy4 38 .globl disable_mmu_icache_secure 39 .globl disable_mmu_secure 40 41func smc 42 /* 43 * For AArch32 only r0-r3 will be in the registers; 44 * rest r4-r6 will be pushed on to the stack. So here, we'll 45 * have to load them from the stack to registers r4-r6 explicitly. 46 * Clobbers: r4-r6 47 */ 48 ldm sp, {r4, r5, r6} 49 smc #0 50endfunc smc 51 52/* ----------------------------------------------------------------------- 53 * void zeromem(void *mem, unsigned int length); 54 * 55 * Initialise a memory region to 0. 56 * The memory address and length must be 4-byte aligned. 57 * ----------------------------------------------------------------------- 58 */ 59func zeromem 60#if ASM_ASSERTION 61 tst r0, #0x3 62 ASM_ASSERT(eq) 63 tst r1, #0x3 64 ASM_ASSERT(eq) 65#endif 66 add r2, r0, r1 67 mov r1, #0 68z_loop: 69 cmp r2, r0 70 beq z_end 71 str r1, [r0], #4 72 b z_loop 73z_end: 74 bx lr 75endfunc zeromem 76 77/* -------------------------------------------------------------------------- 78 * void memcpy4(void *dest, const void *src, unsigned int length) 79 * 80 * Copy length bytes from memory area src to memory area dest. 81 * The memory areas should not overlap. 82 * Destination and source addresses must be 4-byte aligned. 83 * -------------------------------------------------------------------------- 84 */ 85func memcpy4 86#if ASM_ASSERTION 87 orr r3, r0, r1 88 tst r3, #0x3 89 ASM_ASSERT(eq) 90#endif 91/* copy 4 bytes at a time */ 92m_loop4: 93 cmp r2, #4 94 blt m_loop1 95 ldr r3, [r1], #4 96 str r3, [r0], #4 97 sub r2, r2, #4 98 b m_loop4 99/* copy byte per byte */ 100m_loop1: 101 cmp r2,#0 102 beq m_end 103 ldrb r3, [r1], #1 104 strb r3, [r0], #1 105 subs r2, r2, #1 106 bne m_loop1 107m_end: 108 bx lr 109endfunc memcpy4 110 111/* --------------------------------------------------------------------------- 112 * Disable the MMU in Secure State 113 * --------------------------------------------------------------------------- 114 */ 115 116func disable_mmu_secure 117 mov r1, #(SCTLR_M_BIT | SCTLR_C_BIT) 118do_disable_mmu: 119 ldcopr r0, SCTLR 120 bic r0, r0, r1 121 stcopr r0, SCTLR 122 isb // ensure MMU is off 123 dsb sy 124 bx lr 125endfunc disable_mmu_secure 126 127 128func disable_mmu_icache_secure 129 ldr r1, =(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT) 130 b do_disable_mmu 131endfunc disable_mmu_icache_secure 132