1*f24307deSSoby Mathew/* 2*f24307deSSoby Mathew * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3*f24307deSSoby Mathew * 4*f24307deSSoby Mathew * Redistribution and use in source and binary forms, with or without 5*f24307deSSoby Mathew * modification, are permitted provided that the following conditions are met: 6*f24307deSSoby Mathew * 7*f24307deSSoby Mathew * Redistributions of source code must retain the above copyright notice, this 8*f24307deSSoby Mathew * list of conditions and the following disclaimer. 9*f24307deSSoby Mathew * 10*f24307deSSoby Mathew * Redistributions in binary form must reproduce the above copyright notice, 11*f24307deSSoby Mathew * this list of conditions and the following disclaimer in the documentation 12*f24307deSSoby Mathew * and/or other materials provided with the distribution. 13*f24307deSSoby Mathew * 14*f24307deSSoby Mathew * Neither the name of ARM nor the names of its contributors may be used 15*f24307deSSoby Mathew * to endorse or promote products derived from this software without specific 16*f24307deSSoby Mathew * prior written permission. 17*f24307deSSoby Mathew * 18*f24307deSSoby Mathew * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*f24307deSSoby Mathew * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*f24307deSSoby Mathew * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*f24307deSSoby Mathew * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*f24307deSSoby Mathew * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*f24307deSSoby Mathew * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*f24307deSSoby Mathew * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*f24307deSSoby Mathew * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*f24307deSSoby Mathew * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*f24307deSSoby Mathew * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*f24307deSSoby Mathew * POSSIBILITY OF SUCH DAMAGE. 29*f24307deSSoby Mathew */ 30*f24307deSSoby Mathew 31*f24307deSSoby Mathew#include <arch.h> 32*f24307deSSoby Mathew#include <asm_macros.S> 33*f24307deSSoby Mathew#include <assert_macros.S> 34*f24307deSSoby Mathew 35*f24307deSSoby Mathew .globl zeromem 36*f24307deSSoby Mathew 37*f24307deSSoby Mathew/* ----------------------------------------------------------------------- 38*f24307deSSoby Mathew * void zeromem(void *mem, unsigned int length); 39*f24307deSSoby Mathew * 40*f24307deSSoby Mathew * Initialise a memory region to 0. 41*f24307deSSoby Mathew * The memory address and length must be 4-byte aligned. 42*f24307deSSoby Mathew * ----------------------------------------------------------------------- 43*f24307deSSoby Mathew */ 44*f24307deSSoby Mathewfunc zeromem 45*f24307deSSoby Mathew#if ASM_ASSERTION 46*f24307deSSoby Mathew tst r0, #0x3 47*f24307deSSoby Mathew ASM_ASSERT(eq) 48*f24307deSSoby Mathew tst r1, #0x3 49*f24307deSSoby Mathew ASM_ASSERT(eq) 50*f24307deSSoby Mathew#endif 51*f24307deSSoby Mathew add r2, r0, r1 52*f24307deSSoby Mathew mov r1, #0 53*f24307deSSoby Mathewz_loop: 54*f24307deSSoby Mathew cmp r2, r0 55*f24307deSSoby Mathew beq z_end 56*f24307deSSoby Mathew str r1, [r0], #4 57*f24307deSSoby Mathew b z_loop 58*f24307deSSoby Mathewz_end: 59*f24307deSSoby Mathew bx lr 60*f24307deSSoby Mathewendfunc zeromem 61