1 /* 2 * Copyright (c) 2022-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef RMM_CORE_MANIFEST_H 8 #define RMM_CORE_MANIFEST_H 9 10 #include <assert.h> 11 #include <stddef.h> 12 #include <stdint.h> 13 14 #include <lib/cassert.h> 15 16 #define RMMD_MANIFEST_VERSION_MAJOR U(0) 17 #define RMMD_MANIFEST_VERSION_MINOR U(5) 18 19 #define RMM_CONSOLE_MAX_NAME_LEN U(8) 20 21 /* 22 * Version encoding: 23 * - Bit[31] RES0 24 * - Bits [30:16] Major version 25 * - Bits [15:0] Minor version 26 */ 27 #define SET_VERSION(_major, _minor) \ 28 ((((_major) & 0x7FFF) << 16) | ((_minor) & 0xFFFF)) 29 30 /* Boot Manifest version */ 31 #define RMMD_MANIFEST_VERSION SET_VERSION( \ 32 RMMD_MANIFEST_VERSION_MAJOR, \ 33 RMMD_MANIFEST_VERSION_MINOR) 34 35 #define RMMD_GET_MANIFEST_VERSION_MAJOR(_version) \ 36 ((_version >> 16) & 0x7FFF) 37 38 #define RMMD_GET_MANIFEST_VERSION_MINOR(_version) \ 39 (_version & 0xFFFF) 40 41 #define PCIE_RC_INFO_VERSION_MAJOR U(0) 42 #define PCIE_RC_INFO_VERSION_MINOR U(1) 43 44 /* PCIe Root Complex info structure version */ 45 #define PCIE_RC_INFO_VERSION SET_VERSION( \ 46 PCIE_RC_INFO_VERSION_MAJOR, \ 47 PCIE_RC_INFO_VERSION_MINOR) 48 49 /* Memory bank/device region structure */ 50 struct memory_bank { 51 uint64_t base; /* Base address */ 52 uint64_t size; /* Size of memory bank/device region */ 53 }; 54 55 CASSERT(offsetof(struct memory_bank, base) == 0UL, 56 rmm_manifest_base_unaligned); 57 CASSERT(offsetof(struct memory_bank, size) == 8UL, 58 rmm_manifest_size_unaligned); 59 60 /* Memory/device region layout info structure */ 61 struct memory_info { 62 uint64_t num_banks; /* Number of memory banks/device regions */ 63 struct memory_bank *banks; /* Pointer to memory_bank[] */ 64 uint64_t checksum; /* Checksum of memory_info data */ 65 }; 66 67 CASSERT(offsetof(struct memory_info, num_banks) == 0UL, 68 rmm_manifest_num_banks_unaligned); 69 CASSERT(offsetof(struct memory_info, banks) == 8UL, 70 rmm_manifest_dram_data_unaligned); 71 CASSERT(offsetof(struct memory_info, checksum) == 16UL, 72 rmm_manifest_checksum_unaligned); 73 74 /* Console info structure */ 75 struct console_info { 76 uint64_t base; /* Console base address */ 77 uint64_t map_pages; /* Num of pages to be mapped in RMM for the console MMIO */ 78 char name[RMM_CONSOLE_MAX_NAME_LEN]; /* Name of console */ 79 uint64_t clk_in_hz; /* UART clock (in Hz) for the console */ 80 uint64_t baud_rate; /* Baud rate */ 81 uint64_t flags; /* Additional flags RES0 */ 82 }; 83 84 CASSERT(offsetof(struct console_info, base) == 0UL, 85 rmm_manifest_console_base_unaligned); 86 CASSERT(offsetof(struct console_info, map_pages) == 8UL, 87 rmm_manifest_console_map_pages_unaligned); 88 CASSERT(offsetof(struct console_info, name) == 16UL, 89 rmm_manifest_console_name_unaligned); 90 CASSERT(offsetof(struct console_info, clk_in_hz) == 24UL, 91 rmm_manifest_console_clk_in_hz_unaligned); 92 CASSERT(offsetof(struct console_info, baud_rate) == 32UL, 93 rmm_manifest_console_baud_rate_unaligned); 94 CASSERT(offsetof(struct console_info, flags) == 40UL, 95 rmm_manifest_console_flags_unaligned); 96 97 struct console_list { 98 uint64_t num_consoles; /* Number of consoles */ 99 struct console_info *consoles; /* Pointer to console_info[] */ 100 uint64_t checksum; /* Checksum of console_list data */ 101 }; 102 103 CASSERT(offsetof(struct console_list, num_consoles) == 0UL, 104 rmm_manifest_num_consoles); 105 CASSERT(offsetof(struct console_list, consoles) == 8UL, 106 rmm_manifest_consoles); 107 CASSERT(offsetof(struct console_list, checksum) == 16UL, 108 rmm_manifest_console_list_checksum); 109 110 /* SMMUv3 Info structure */ 111 struct smmu_info { 112 uint64_t smmu_base; /* SMMUv3 base address */ 113 uint64_t smmu_r_base; /* SMMUv3 Realm Pages base address */ 114 }; 115 116 CASSERT(offsetof(struct smmu_info, smmu_base) == 0UL, 117 rmm_manifest_smmu_base); 118 CASSERT(offsetof(struct smmu_info, smmu_r_base) == 8UL, 119 rmm_manifest_smmu_r_base); 120 121 /* SMMUv3 Info List structure */ 122 struct smmu_list { 123 uint64_t num_smmus; /* Number of smmu_info entries */ 124 struct smmu_info *smmus; /* Pointer to smmu_info[] array */ 125 uint64_t checksum; /* Checksum of smmu_list data */ 126 }; 127 128 CASSERT(offsetof(struct smmu_list, num_smmus) == 0UL, 129 rmm_manifest_num_smmus); 130 CASSERT(offsetof(struct smmu_list, smmus) == 8UL, 131 rmm_manifest_smmus); 132 CASSERT(offsetof(struct smmu_list, checksum) == 16UL, 133 rmm_manifest_smmu_list_checksum); 134 135 /* PCIe BDF Mapping Info structure */ 136 struct bdf_mapping_info { 137 uint16_t mapping_base; /* Base of BDF mapping (inclusive) */ 138 uint16_t mapping_top; /* Top of BDF mapping (exclusive) */ 139 uint16_t mapping_off; /* Mapping offset, as per Arm Base System Architecture: */ 140 /* StreamID = zero_extend(RequesterID[N-1:0]) + (1<<N)*Constant_B */ 141 uint16_t smmu_idx; /* SMMU index in smmu_info[] array */ 142 }; 143 144 CASSERT(offsetof(struct bdf_mapping_info, mapping_base) == 0UL, 145 rmm_manifest_mapping_base); 146 CASSERT(offsetof(struct bdf_mapping_info, mapping_top) == 2UL, 147 rmm_manifest_mapping_top); 148 CASSERT(offsetof(struct bdf_mapping_info, mapping_off) == 4UL, 149 rmm_manifest_mapping_off); 150 CASSERT(offsetof(struct bdf_mapping_info, smmu_idx) == 6UL, 151 rmm_manifest_smmu_ptr); 152 153 /* PCIe Root Port Info structure */ 154 struct root_port_info { 155 uint16_t root_port_id; /* Root Port identifier */ 156 uint16_t padding; /* RES0 */ 157 uint32_t num_bdf_mappings; /* Number of BDF mappings */ 158 struct bdf_mapping_info *bdf_mappings; /* Pointer to bdf_mapping_info[] array */ 159 }; 160 161 CASSERT(offsetof(struct root_port_info, root_port_id) == 0UL, 162 rmm_manifest_root_port_id); 163 CASSERT(offsetof(struct root_port_info, num_bdf_mappings) == 4UL, 164 rmm_manifest_num_bdf_mappingss); 165 CASSERT(offsetof(struct root_port_info, bdf_mappings) == 8UL, 166 rmm_manifest_bdf_mappings); 167 168 /* PCIe Root Complex info structure v0.1 */ 169 struct root_complex_info { 170 uint64_t ecam_base; /* ECAM base address. Size is implicitly 256MB */ 171 uint8_t segment; /* PCIe segment identifier */ 172 uint8_t padding[3]; /* RES0 */ 173 uint32_t num_root_ports; /* Number of root ports */ 174 struct root_port_info *root_ports; /* Pointer to root_port_info[] array */ 175 }; 176 177 CASSERT(offsetof(struct root_complex_info, ecam_base) == 0UL, 178 rmm_manifest_ecam_base); 179 CASSERT(offsetof(struct root_complex_info, segment) == 8UL, 180 rmm_manifest_segment); 181 CASSERT(offsetof(struct root_complex_info, num_root_ports) == 12UL, 182 rmm_manifest_num_root_ports); 183 CASSERT(offsetof(struct root_complex_info, root_ports) == 16UL, 184 rmm_manifest_root_ports); 185 186 /* PCIe Root Complex List structure */ 187 struct root_complex_list { 188 uint64_t num_root_complex; /* Number of pci_rc_info entries */ 189 uint32_t rc_info_version; /* PCIe Root Complex info structure version */ 190 uint32_t padding; /* RES0 */ 191 struct root_complex_info *root_complex; /* Pointer to pci_rc_info[] array */ 192 uint64_t checksum; /* Checksum of pci_rc_list data */ 193 }; 194 195 CASSERT(offsetof(struct root_complex_list, num_root_complex) == 0UL, 196 rmm_manifest_num_root_complex); 197 CASSERT(offsetof(struct root_complex_list, rc_info_version) == 8UL, 198 rmm_manifest_rc_info_version); 199 CASSERT(offsetof(struct root_complex_list, root_complex) == 16UL, 200 rmm_manifest_root_complex); 201 CASSERT(offsetof(struct root_complex_list, checksum) == 24UL, 202 rmm_manifest_root_complex_list_checksum); 203 204 /* Boot manifest core structure as per v0.5 */ 205 struct rmm_manifest { 206 uint32_t version; /* Manifest version */ 207 uint32_t padding; /* RES0 */ 208 uint64_t plat_data; /* Manifest platform data */ 209 /* Platform NS DRAM data (v0.2) */ 210 struct memory_info plat_dram; 211 /* Platform console list (v0.3) */ 212 struct console_list plat_console; 213 /* Platform device address ranges (v0.4) */ 214 struct memory_info plat_ncoh_region; 215 struct memory_info plat_coh_region; 216 /* Platform SMMUv3 list (v0.5) */ 217 struct smmu_list plat_smmu; 218 /* Platform PCIe Root Complex list (v0.5) */ 219 struct root_complex_list plat_root_complex; 220 }; 221 222 CASSERT(offsetof(struct rmm_manifest, version) == 0UL, 223 rmm_manifest_version_unaligned); 224 CASSERT(offsetof(struct rmm_manifest, plat_data) == 8UL, 225 rmm_manifest_plat_data_unaligned); 226 CASSERT(offsetof(struct rmm_manifest, plat_dram) == 16UL, 227 rmm_manifest_plat_dram_unaligned); 228 CASSERT(offsetof(struct rmm_manifest, plat_console) == 40UL, 229 rmm_manifest_plat_console_unaligned); 230 CASSERT(offsetof(struct rmm_manifest, plat_ncoh_region) == 64UL, 231 rmm_manifest_plat_ncoh_region_unaligned); 232 CASSERT(offsetof(struct rmm_manifest, plat_coh_region) == 88UL, 233 rmm_manifest_plat_coh_region_unaligned); 234 CASSERT(offsetof(struct rmm_manifest, plat_smmu) == 112UL, 235 rmm_manifest_plat_smmu_unaligned); 236 CASSERT(offsetof(struct rmm_manifest, plat_root_complex) == 136UL, 237 rmm_manifest_plat_root_complex); 238 239 #endif /* RMM_CORE_MANIFEST_H */ 240