1*c7a28aa7SJeremy Linton /* 2*c7a28aa7SJeremy Linton * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3*c7a28aa7SJeremy Linton * 4*c7a28aa7SJeremy Linton * SPDX-License-Identifier: BSD-3-Clause 5*c7a28aa7SJeremy Linton */ 6*c7a28aa7SJeremy Linton 7*c7a28aa7SJeremy Linton #ifndef PCI_SVC_H 8*c7a28aa7SJeremy Linton #define PCI_SVC_H 9*c7a28aa7SJeremy Linton 10*c7a28aa7SJeremy Linton #include <lib/utils_def.h> 11*c7a28aa7SJeremy Linton 12*c7a28aa7SJeremy Linton /* SMCCC PCI platform functions */ 13*c7a28aa7SJeremy Linton #define SMC_PCI_VERSION U(0x84000130) 14*c7a28aa7SJeremy Linton #define SMC_PCI_FEATURES U(0x84000131) 15*c7a28aa7SJeremy Linton #define SMC_PCI_READ U(0x84000132) 16*c7a28aa7SJeremy Linton #define SMC_PCI_WRITE U(0x84000133) 17*c7a28aa7SJeremy Linton #define SMC_PCI_SEG_INFO U(0x84000134) 18*c7a28aa7SJeremy Linton 19*c7a28aa7SJeremy Linton #define is_pci_fid(_fid) (((_fid) >= SMC_PCI_VERSION) && \ 20*c7a28aa7SJeremy Linton ((_fid) <= SMC_PCI_SEG_INFO)) 21*c7a28aa7SJeremy Linton 22*c7a28aa7SJeremy Linton uint64_t pci_smc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, 23*c7a28aa7SJeremy Linton u_register_t x3, u_register_t x4, void *cookie, 24*c7a28aa7SJeremy Linton void *handle, u_register_t flags); 25*c7a28aa7SJeremy Linton 26*c7a28aa7SJeremy Linton #define PCI_ADDR_FUN(dev) ((dev) & U(0x7)) 27*c7a28aa7SJeremy Linton #define PCI_ADDR_DEV(dev) (((dev) >> U(3)) & U(0x001F)) 28*c7a28aa7SJeremy Linton #define PCI_ADDR_BUS(dev) (((dev) >> U(8)) & U(0x00FF)) 29*c7a28aa7SJeremy Linton #define PCI_ADDR_SEG(dev) (((dev) >> U(16)) & U(0xFFFF)) 30*c7a28aa7SJeremy Linton #define PCI_OFFSET_MASK U(0xFFF) 31*c7a28aa7SJeremy Linton typedef union { 32*c7a28aa7SJeremy Linton struct { 33*c7a28aa7SJeremy Linton uint16_t minor; 34*c7a28aa7SJeremy Linton uint16_t major; 35*c7a28aa7SJeremy Linton } __packed; 36*c7a28aa7SJeremy Linton uint32_t val; 37*c7a28aa7SJeremy Linton } pcie_version; 38*c7a28aa7SJeremy Linton 39*c7a28aa7SJeremy Linton /* 40*c7a28aa7SJeremy Linton * platforms are responsible for providing implementations of these 41*c7a28aa7SJeremy Linton * three functions in a manner which conforms to the Arm PCI Configuration 42*c7a28aa7SJeremy Linton * Space Access Firmware Interface (DEN0115) and the PCIe specification's 43*c7a28aa7SJeremy Linton * sections on PCI configuration access. See the rpi4_pci_svc.c example. 44*c7a28aa7SJeremy Linton */ 45*c7a28aa7SJeremy Linton uint32_t pci_read_config(uint32_t addr, uint32_t off, uint32_t sz, uint32_t *val); 46*c7a28aa7SJeremy Linton uint32_t pci_write_config(uint32_t addr, uint32_t off, uint32_t sz, uint32_t val); 47*c7a28aa7SJeremy Linton uint32_t pci_get_bus_for_seg(uint32_t seg, uint32_t *bus_range, uint32_t *nseg); 48*c7a28aa7SJeremy Linton 49*c7a28aa7SJeremy Linton /* Return codes for Arm PCI Config Space Access Firmware SMC calls */ 50*c7a28aa7SJeremy Linton #define SMC_PCI_CALL_SUCCESS U(0) 51*c7a28aa7SJeremy Linton #define SMC_PCI_CALL_NOT_SUPPORTED -1 52*c7a28aa7SJeremy Linton #define SMC_PCI_CALL_INVAL_PARAM -2 53*c7a28aa7SJeremy Linton #define SMC_PCI_CALL_NOT_IMPL -3 54*c7a28aa7SJeremy Linton 55*c7a28aa7SJeremy Linton #define SMC_PCI_SZ_8BIT U(1) 56*c7a28aa7SJeremy Linton #define SMC_PCI_SZ_16BIT U(2) 57*c7a28aa7SJeremy Linton #define SMC_PCI_SZ_32BIT U(4) 58*c7a28aa7SJeremy Linton 59*c7a28aa7SJeremy Linton #endif /* PCI_SVC_H */ 60