xref: /rk3399_ARM-atf/include/services/drtm_svc.h (revision a1094e32f1f050eeaa841ad1c616348b91a39039) 
1 /*
2  * Copyright (c) 2022-2025 Arm Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier:    BSD-3-Clause
5  *
6  * DRTM service
7  *
8  * Authors:
9  *	Lucian Paul-Trifu <lucian.paultrifu@gmail.com>
10  *	Brian Nezvadovitz <brinez@microsoft.com> 2021-02-01
11  *
12  */
13 
14 #ifndef ARM_DRTM_SVC_H
15 #define ARM_DRTM_SVC_H
16 
17 /*
18  * SMC function IDs for DRTM Service
19  * Upper word bits set: Fast call, SMC64, Standard Secure Svc. Call (OEN = 4)
20  */
21 #define DRTM_FID(func_num)				\
22 	((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) |		\
23 	(SMC_64 << FUNCID_CC_SHIFT) |			\
24 	(OEN_STD_START << FUNCID_OEN_SHIFT) |		\
25 	((func_num) << FUNCID_NUM_SHIFT))
26 
27 #define DRTM_FNUM_SVC_VERSION		U(0x110)
28 #define DRTM_FNUM_SVC_FEATURES		U(0x111)
29 #define DRTM_FNUM_SVC_UNPROTECT_MEM	U(0x113)
30 #define DRTM_FNUM_SVC_DYNAMIC_LAUNCH	U(0x114)
31 #define DRTM_FNUM_SVC_CLOSE_LOCALITY	U(0x115)
32 #define DRTM_FNUM_SVC_GET_ERROR		U(0x116)
33 #define DRTM_FNUM_SVC_SET_ERROR		U(0x117)
34 #define DRTM_FNUM_SVC_SET_TCB_HASH	U(0x118)
35 #define DRTM_FNUM_SVC_LOCK_TCB_HASH	U(0x119)
36 
37 #define ARM_DRTM_SVC_VERSION		DRTM_FID(DRTM_FNUM_SVC_VERSION)
38 #define ARM_DRTM_SVC_FEATURES		DRTM_FID(DRTM_FNUM_SVC_FEATURES)
39 #define ARM_DRTM_SVC_UNPROTECT_MEM	DRTM_FID(DRTM_FNUM_SVC_UNPROTECT_MEM)
40 #define ARM_DRTM_SVC_DYNAMIC_LAUNCH	DRTM_FID(DRTM_FNUM_SVC_DYNAMIC_LAUNCH)
41 #define ARM_DRTM_SVC_CLOSE_LOCALITY	DRTM_FID(DRTM_FNUM_SVC_CLOSE_LOCALITY)
42 #define ARM_DRTM_SVC_GET_ERROR		DRTM_FID(DRTM_FNUM_SVC_GET_ERROR)
43 #define ARM_DRTM_SVC_SET_ERROR		DRTM_FID(DRTM_FNUM_SVC_SET_ERROR)
44 #define ARM_DRTM_SVC_SET_TCB_HASH	DRTM_FID(DRTM_FNUM_SVC_SET_TCB_HASH)
45 #define ARM_DRTM_SVC_LOCK_TCB_HASH	DRTM_FID(DRTM_FNUM_SVC_LOCK_TCB_HASH)
46 
47 #define ARM_DRTM_FEATURES_TPM		U(0x1)
48 #define ARM_DRTM_FEATURES_MEM_REQ	U(0x2)
49 #define ARM_DRTM_FEATURES_DMA_PROT	U(0x3)
50 #define ARM_DRTM_FEATURES_BOOT_PE_ID	U(0x4)
51 #define ARM_DRTM_FEATURES_TCB_HASHES	U(0x5)
52 #define ARM_DRTM_FEATURES_DLME_IMG_AUTH	U(0x6)
53 
54 #define is_drtm_fid(_fid) \
55 	(((_fid) >= ARM_DRTM_SVC_VERSION) && ((_fid) <= ARM_DRTM_SVC_LOCK_TCB_HASH))
56 
57 /* ARM DRTM Service Calls version numbers */
58 #define ARM_DRTM_VERSION_MAJOR		U(1)
59 #define ARM_DRTM_VERSION_MAJOR_SHIFT	16
60 #define ARM_DRTM_VERSION_MAJOR_MASK	U(0x7FFF)
61 #define ARM_DRTM_VERSION_MINOR		U(0)
62 #define ARM_DRTM_VERSION_MINOR_SHIFT	0
63 #define ARM_DRTM_VERSION_MINOR_MASK	U(0xFFFF)
64 
65 #define ARM_DRTM_VERSION						\
66 	((((ARM_DRTM_VERSION_MAJOR) & ARM_DRTM_VERSION_MAJOR_MASK) <<	\
67 	ARM_DRTM_VERSION_MAJOR_SHIFT)					\
68 	| (((ARM_DRTM_VERSION_MINOR) & ARM_DRTM_VERSION_MINOR_MASK) <<	\
69 	ARM_DRTM_VERSION_MINOR_SHIFT))
70 
71 #define ARM_DRTM_FUNC_SHIFT	U(63)
72 #define ARM_DRTM_FUNC_MASK	ULL(0x1)
73 #define ARM_DRTM_FUNC_ID	U(0x0)
74 #define ARM_DRTM_FEAT_ID	U(0x1)
75 #define ARM_DRTM_FEAT_ID_MASK	ULL(0xff)
76 
77 /*
78  * Definitions for DRTM features as per DRTM 1.0 section 3.3,
79  * Table 6 DRTM_FEATURES
80  */
81 #define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT		U(33)
82 #define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK		ULL(0xF)
83 #define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_DEFAULT	ULL(0x1)
84 
85 #define ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT		U(32)
86 #define ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK		ULL(0x1)
87 #define ARM_DRTM_TPM_FEATURES_TPM_HASH_NOT_SUPPORTED	ULL(0x0)
88 #define ARM_DRTM_TPM_FEATURES_TPM_HASH_SUPPORTED	ULL(0x1)
89 
90 #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT		U(0)
91 #define ARM_DRTM_TPM_FEATURES_FW_HASH_MASK		ULL(0xFFFF)
92 #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA256		ULL(0xB)
93 #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA384		ULL(0xC)
94 #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA512		ULL(0xD)
95 
96 #define ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT		U(32)
97 #define ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK		ULL(0xFFFFFFFF)
98 
99 #define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT	U(0)
100 #define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK	ULL(0xFFFFFFFF)
101 
102 #define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT	U(8)
103 #define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK	ULL(0xF)
104 
105 #define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT	U(0)
106 #define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK	ULL(0xFF)
107 #define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_COMPLETE	ULL(0x1)
108 #define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_REGION	ULL(0x2)
109 
110 #define ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT	U(0)
111 #define ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK	ULL(0xFF)
112 
113 #define ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_SHIFT	U(0)
114 #define ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_MASK	ULL(0x1)
115 
116 #define ARM_DRTM_TPM_FEATURES_SET_PCR_SCHEMA(reg, val)			\
117 	do {								\
118 		reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK \
119 		<< ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT)) | (((val) & \
120 		ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK) <<		\
121 		ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT));		\
122 	} while (false)
123 
124 #define ARM_DRTM_TPM_FEATURES_SET_TPM_HASH(reg, val)			\
125 	do {								\
126 		reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK	\
127 		<< ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT)) | (((val) &	\
128 		ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK) <<			\
129 		ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT));			\
130 	} while (false)
131 
132 #define ARM_DRTM_TPM_FEATURES_SET_FW_HASH(reg, val)			\
133 	do {								\
134 		reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_FW_HASH_MASK	\
135 		<< ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT)) | (((val) &	\
136 		ARM_DRTM_TPM_FEATURES_FW_HASH_MASK) <<			\
137 		ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT));			\
138 	} while (false)
139 
140 #define ARM_DRTM_MIN_MEM_REQ_SET_DCE_SIZE(reg, val)			\
141 	do {								\
142 		reg = (((reg) & ~(ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK	\
143 		<< ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT)) | (((val) &	\
144 		ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK) <<			\
145 		ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT));			\
146 	} while (false)
147 
148 #define ARM_DRTM_MIN_MEM_REQ_SET_MIN_DLME_DATA_SIZE(reg, val)		\
149 	do {								\
150 		reg = (((reg) &						\
151 		~(ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK <<	\
152 		ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT)) |	\
153 		(((val) & ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK) \
154 		<< ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT));	\
155 	} while (false)
156 
157 #define ARM_DRTM_DMA_PROT_FEATURES_SET_MAX_REGIONS(reg, val)		\
158 	do {								\
159 		reg = (((reg) &						\
160 		~(ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK <<	\
161 		ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT)) |	\
162 		(((val) & ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK)	\
163 		<< ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT));	\
164 	} while (false)
165 
166 #define ARM_DRTM_DMA_PROT_FEATURES_SET_DMA_SUPPORT(reg, val) \
167 	do {								\
168 		reg = (((reg) &						\
169 		~(ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK <<	\
170 		ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT)) |	\
171 		(((val) & ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK)	\
172 		<< ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT));	\
173 	} while (false)
174 
175 #define ARM_DRTM_TCB_HASH_FEATURES_SET_MAX_NUM_HASHES(reg, val)		\
176 	do {								\
177 		reg = (((reg) &						\
178 		~(ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK <<	\
179 		ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT)) |	\
180 		(((val) &						\
181 		ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK) <<	\
182 		ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT));	\
183 	} while (false)
184 
185 #define ARM_DRTM_DLME_IMG_AUTH_SUPPORT(reg, val)		\
186 	do {								\
187 		reg = (((reg) &						\
188 		~(ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_MASK <<	\
189 		ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_SHIFT)) |	\
190 		(((val) &						\
191 		ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_MASK) <<	\
192 		ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_SHIFT));	\
193 	} while (false)
194 
195 /* Definitions for DRTM address map */
196 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT	U(55)
197 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK	ULL(0x3)
198 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_NC	ULL(0)
199 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WC	ULL(1)
200 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WT	ULL(2)
201 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WB	ULL(3)
202 
203 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT	U(52)
204 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK	ULL(0x7)
205 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NORMAL	ULL(0)
206 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NCAR	ULL(1)
207 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_DEVICE	ULL(2)
208 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NV	ULL(3)
209 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_RSVD	ULL(4)
210 
211 #define ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT	U(0)
212 #define ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK	ULL(0xFFFFFFFFFFFFF)
213 
214 #define ARM_DRTM_REGION_SIZE_TYPE_SET_CACHEABILITY(reg, val)		\
215 	do {								\
216 		reg = (((reg) &						\
217 		~(ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK << 	\
218 		ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT)) |	\
219 		(((val) &						\
220 		ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK) <<		\
221 		ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT));		\
222 	} while (false)
223 
224 #define ARM_DRTM_REGION_SIZE_TYPE_SET_REGION_TYPE(reg, val)		\
225 	do {								\
226 		reg = (((reg) &						\
227 		~(ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK <<		\
228 		ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT)) |		\
229 		(((val) & ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK)	\
230 		<< ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT));	\
231 	} while (false)
232 
233 #define ARM_DRTM_REGION_SIZE_TYPE_SET_4K_PAGE_NUM(reg, val)		\
234 	do {								\
235 		reg = (((reg) &						\
236 		~(ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK <<		\
237 		ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT)) |		\
238 		(((val) & ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK)	\
239 		<< ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT));	\
240 	} while (false)
241 
242 /* Initialization routine for the DRTM service */
243 int drtm_setup(void);
244 
245 /* Handler to be called to handle DRTM SMC calls */
246 uint64_t drtm_smc_handler(uint32_t smc_fid,
247 			  uint64_t x1,
248 			  uint64_t x2,
249 			  uint64_t x3,
250 			  uint64_t x4,
251 			  void *cookie,
252 			  void *handle,
253 			  uint64_t flags);
254 
255 #endif /* ARM_DRTM_SVC_H */
256