1 /* 2 * Copyright (c) 2022-2025 Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * DRTM service 7 * 8 * Authors: 9 * Lucian Paul-Trifu <lucian.paultrifu@gmail.com> 10 * Brian Nezvadovitz <brinez@microsoft.com> 2021-02-01 11 * 12 */ 13 14 #ifndef ARM_DRTM_SVC_H 15 #define ARM_DRTM_SVC_H 16 17 #include <lib/utils_def.h> 18 19 /* 20 * SMC function IDs for DRTM Service 21 * Upper word bits set: Fast call, SMC64, Standard Secure Svc. Call (OEN = 4) 22 */ 23 #define DRTM_FID(func_num) \ 24 ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) | \ 25 (SMC_64 << FUNCID_CC_SHIFT) | \ 26 (OEN_STD_START << FUNCID_OEN_SHIFT) | \ 27 ((func_num) << FUNCID_NUM_SHIFT)) 28 29 #define DRTM_FNUM_SVC_VERSION U(0x110) 30 #define DRTM_FNUM_SVC_FEATURES U(0x111) 31 #define DRTM_FNUM_SVC_UNPROTECT_MEM U(0x113) 32 #define DRTM_FNUM_SVC_DYNAMIC_LAUNCH U(0x114) 33 #define DRTM_FNUM_SVC_CLOSE_LOCALITY U(0x115) 34 #define DRTM_FNUM_SVC_GET_ERROR U(0x116) 35 #define DRTM_FNUM_SVC_SET_ERROR U(0x117) 36 #define DRTM_FNUM_SVC_SET_TCB_HASH U(0x118) 37 #define DRTM_FNUM_SVC_LOCK_TCB_HASH U(0x119) 38 39 #define ARM_DRTM_SVC_VERSION DRTM_FID(DRTM_FNUM_SVC_VERSION) 40 #define ARM_DRTM_SVC_FEATURES DRTM_FID(DRTM_FNUM_SVC_FEATURES) 41 #define ARM_DRTM_SVC_UNPROTECT_MEM DRTM_FID(DRTM_FNUM_SVC_UNPROTECT_MEM) 42 #define ARM_DRTM_SVC_DYNAMIC_LAUNCH DRTM_FID(DRTM_FNUM_SVC_DYNAMIC_LAUNCH) 43 #define ARM_DRTM_SVC_CLOSE_LOCALITY DRTM_FID(DRTM_FNUM_SVC_CLOSE_LOCALITY) 44 #define ARM_DRTM_SVC_GET_ERROR DRTM_FID(DRTM_FNUM_SVC_GET_ERROR) 45 #define ARM_DRTM_SVC_SET_ERROR DRTM_FID(DRTM_FNUM_SVC_SET_ERROR) 46 #define ARM_DRTM_SVC_SET_TCB_HASH DRTM_FID(DRTM_FNUM_SVC_SET_TCB_HASH) 47 #define ARM_DRTM_SVC_LOCK_TCB_HASH DRTM_FID(DRTM_FNUM_SVC_LOCK_TCB_HASH) 48 49 #define ARM_DRTM_FEATURES_TPM U(0x1) 50 #define ARM_DRTM_FEATURES_MEM_REQ U(0x2) 51 #define ARM_DRTM_FEATURES_DMA_PROT U(0x3) 52 #define ARM_DRTM_FEATURES_BOOT_PE_ID U(0x4) 53 #define ARM_DRTM_FEATURES_TCB_HASHES U(0x5) 54 #define ARM_DRTM_FEATURES_DLME_IMG_AUTH U(0x6) 55 56 #define is_drtm_fid(_fid) \ 57 (((_fid) >= ARM_DRTM_SVC_VERSION) && ((_fid) <= ARM_DRTM_SVC_LOCK_TCB_HASH)) 58 59 /* ARM DRTM Service Calls version numbers */ 60 #define ARM_DRTM_VERSION_MAJOR U(1) 61 #define ARM_DRTM_VERSION_MAJOR_SHIFT 16 62 #define ARM_DRTM_VERSION_MAJOR_MASK U(0x7FFF) 63 #define ARM_DRTM_VERSION_MINOR U(0) 64 #define ARM_DRTM_VERSION_MINOR_SHIFT 0 65 #define ARM_DRTM_VERSION_MINOR_MASK U(0xFFFF) 66 67 #define ARM_DRTM_VERSION \ 68 ((((ARM_DRTM_VERSION_MAJOR) & ARM_DRTM_VERSION_MAJOR_MASK) << \ 69 ARM_DRTM_VERSION_MAJOR_SHIFT) \ 70 | (((ARM_DRTM_VERSION_MINOR) & ARM_DRTM_VERSION_MINOR_MASK) << \ 71 ARM_DRTM_VERSION_MINOR_SHIFT)) 72 73 #define ARM_DRTM_FUNC_SHIFT U(63) 74 #define ARM_DRTM_FUNC_MASK ULL(0x1) 75 #define ARM_DRTM_FUNC_ID U(0x0) 76 #define ARM_DRTM_FEAT_ID U(0x1) 77 #define ARM_DRTM_FEAT_ID_MASK ULL(0xff) 78 79 /* 80 * Definitions for DRTM features as per DRTM 1.0 section 3.3, 81 * Table 6 DRTM_FEATURES 82 */ 83 #define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT U(33) 84 #define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK ULL(0xF) 85 #define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_DEFAULT ULL(0x1) 86 87 #define ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT U(32) 88 #define ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK ULL(0x1) 89 #define ARM_DRTM_TPM_FEATURES_TPM_HASH_NOT_SUPPORTED ULL(0x0) 90 #define ARM_DRTM_TPM_FEATURES_TPM_HASH_SUPPORTED ULL(0x1) 91 92 #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT U(0) 93 #define ARM_DRTM_TPM_FEATURES_FW_HASH_MASK ULL(0xFFFF) 94 #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA256 ULL(0xB) 95 #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA384 ULL(0xC) 96 #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA512 ULL(0xD) 97 98 #define ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT U(32) 99 #define ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK ULL(0xFFFFFFFF) 100 101 #define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT U(0) 102 #define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK ULL(0xFFFFFFFF) 103 104 #define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT U(8) 105 #define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK ULL(0xF) 106 107 #define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT U(0) 108 #define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK ULL(0xFF) 109 #define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_COMPLETE ULL(0x1) 110 #define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_REGION ULL(0x2) 111 112 #define ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT U(0) 113 #define ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK ULL(0xFF) 114 115 #define ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_SHIFT U(0) 116 #define ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_MASK ULL(0x1) 117 118 #define ARM_DRTM_TPM_FEATURES_SET_PCR_SCHEMA(reg, val) \ 119 do { \ 120 reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK \ 121 << ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT)) | (((val) & \ 122 ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK) << \ 123 ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT)); \ 124 } while (false) 125 126 #define ARM_DRTM_TPM_FEATURES_SET_TPM_HASH(reg, val) \ 127 do { \ 128 reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK \ 129 << ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT)) | (((val) & \ 130 ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK) << \ 131 ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT)); \ 132 } while (false) 133 134 #define ARM_DRTM_TPM_FEATURES_SET_FW_HASH(reg, val) \ 135 do { \ 136 reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_FW_HASH_MASK \ 137 << ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT)) | (((val) & \ 138 ARM_DRTM_TPM_FEATURES_FW_HASH_MASK) << \ 139 ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT)); \ 140 } while (false) 141 142 #define ARM_DRTM_MIN_MEM_REQ_SET_DCE_SIZE(reg, val) \ 143 do { \ 144 reg = (((reg) & ~(ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK \ 145 << ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT)) | (((val) & \ 146 ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK) << \ 147 ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT)); \ 148 } while (false) 149 150 #define ARM_DRTM_MIN_MEM_REQ_SET_MIN_DLME_DATA_SIZE(reg, val) \ 151 do { \ 152 reg = (((reg) & \ 153 ~(ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK << \ 154 ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT)) | \ 155 (((val) & ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK) \ 156 << ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT)); \ 157 } while (false) 158 159 #define ARM_DRTM_DMA_PROT_FEATURES_SET_MAX_REGIONS(reg, val) \ 160 do { \ 161 reg = (((reg) & \ 162 ~(ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK << \ 163 ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT)) | \ 164 (((val) & ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK) \ 165 << ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT)); \ 166 } while (false) 167 168 #define ARM_DRTM_DMA_PROT_FEATURES_SET_DMA_SUPPORT(reg, val) \ 169 do { \ 170 reg = (((reg) & \ 171 ~(ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK << \ 172 ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT)) | \ 173 (((val) & ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK) \ 174 << ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT)); \ 175 } while (false) 176 177 #define ARM_DRTM_TCB_HASH_FEATURES_SET_MAX_NUM_HASHES(reg, val) \ 178 do { \ 179 reg = (((reg) & \ 180 ~(ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK << \ 181 ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT)) | \ 182 (((val) & \ 183 ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK) << \ 184 ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT)); \ 185 } while (false) 186 187 #define ARM_DRTM_DLME_IMG_AUTH_SUPPORT(reg, val) \ 188 do { \ 189 reg = (((reg) & \ 190 ~(ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_MASK << \ 191 ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_SHIFT)) | \ 192 (((val) & \ 193 ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_MASK) << \ 194 ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_SHIFT)); \ 195 } while (false) 196 197 /* Definitions for DRTM address map */ 198 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT U(55) 199 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK ULL(0x3) 200 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_NC ULL(0) 201 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WC ULL(1) 202 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WT ULL(2) 203 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WB ULL(3) 204 205 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT U(52) 206 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK ULL(0x7) 207 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NORMAL ULL(0) 208 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NCAR ULL(1) 209 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_DEVICE ULL(2) 210 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NV ULL(3) 211 #define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_RSVD ULL(4) 212 213 #define ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT U(0) 214 #define ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK ULL(0xFFFFFFFFFFFFF) 215 216 #define ARM_DRTM_REGION_SIZE_TYPE_SET_CACHEABILITY(reg, val) \ 217 do { \ 218 reg = (((reg) & \ 219 ~(ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK << \ 220 ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT)) | \ 221 (((val) & \ 222 ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK) << \ 223 ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT)); \ 224 } while (false) 225 226 #define ARM_DRTM_REGION_SIZE_TYPE_SET_REGION_TYPE(reg, val) \ 227 do { \ 228 reg = (((reg) & \ 229 ~(ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK << \ 230 ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT)) | \ 231 (((val) & ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK) \ 232 << ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT)); \ 233 } while (false) 234 235 #define ARM_DRTM_REGION_SIZE_TYPE_SET_4K_PAGE_NUM(reg, val) \ 236 do { \ 237 reg = (((reg) & \ 238 ~(ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK << \ 239 ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT)) | \ 240 (((val) & ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK) \ 241 << ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT)); \ 242 } while (false) 243 244 #define DRTM_LAUNCH_FEAT_DLME_IMG_AUTH_SHIFT U(6) 245 #define DRTM_LAUNCH_FEAT_MEM_PROTECTION_TYPE_SHIFT U(3) 246 #define DRTM_LAUNCH_FEAT_PCR_USAGE_SCHEMA_SHIFT U(1) 247 #define DRTM_LAUNCH_FEAT_HASHING_TYPE_SHIFT U(0) 248 249 #define DRTM_LAUNCH_FEAT_DLME_IMG_AUTH_MASK U(0x1) 250 #define DRTM_LAUNCH_FEAT_MEM_PROTECTION_TYPE_MASK U(0x7) 251 #define DRTM_LAUNCH_FEAT_PCR_USAGE_SCHEMA_MASK U(0x3) 252 #define DRTM_LAUNCH_FEAT_HASHING_TYPE_MASK U(0x1) 253 254 #define DLME_IMG_AUTH U(0x1) 255 #define REG_MEM_PROTECTION_TYPE U(0x1) 256 #define DLME_AUTH_SCHEMA U(0x1) 257 #define TPM_BASED_HASHING U(0x1) 258 259 /* Initialization routine for the DRTM service */ 260 int drtm_setup(void); 261 262 /* Handler to be called to handle DRTM SMC calls */ 263 uint64_t drtm_smc_handler(uint32_t smc_fid, 264 uint64_t x1, 265 uint64_t x2, 266 uint64_t x3, 267 uint64_t x4, 268 void *cookie, 269 void *handle, 270 uint64_t flags); 271 272 #endif /* ARM_DRTM_SVC_H */ 273