1 /* 2 * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARM_ARCH_SVC_H 8 #define ARM_ARCH_SVC_H 9 10 #define SMCCC_VERSION U(0x80000000) 11 #define SMCCC_ARCH_FEATURES U(0x80000001) 12 #define SMCCC_ARCH_SOC_ID U(0x80000002) 13 #define SMCCC_ARCH_WORKAROUND_1 U(0x80008000) 14 #define SMCCC_ARCH_WORKAROUND_2 U(0x80007FFF) 15 #define SMCCC_ARCH_WORKAROUND_3 U(0x80003FFF) 16 #define SMCCC_ARCH_FEATURE_AVAILABILITY U(0x80000003) 17 #define SMCCC_ARCH_WORKAROUND_4 U(0x80000004) 18 19 #define SMCCC_GET_SOC_VERSION U(0) 20 #define SMCCC_GET_SOC_REVISION U(1) 21 #define SMCCC_GET_SOC_NAME U(2) 22 23 #define SMCCC_SOC_NAME_LEN U(136) 24 25 #ifndef __ASSEMBLER__ 26 #if ARCH_FEATURE_AVAILABILITY 27 #include <lib/cassert.h> 28 29 #if ENABLE_FEAT_FGT2 30 #define SCR_FEAT_FGT2 SCR_FGTEN2_BIT 31 #else 32 #define SCR_FEAT_FGT2 (0) 33 #endif 34 35 #if ENABLE_FEAT_FPMR 36 #define SCR_FEAT_FPMR SCR_EnFPM_BIT 37 #else 38 #define SCR_FEAT_FPMR 39 #endif 40 41 #if ENABLE_FEAT_D128 42 #define SCR_FEAT_D128 SCR_D128En_BIT 43 #else 44 #define SCR_FEAT_D128 (0) 45 #endif 46 47 #if ENABLE_FEAT_S1PIE 48 #define SCR_FEAT_S1PIE SCR_PIEN_BIT 49 #else 50 #define SCR_FEAT_S1PIE (0) 51 #endif 52 53 #if ENABLE_FEAT_SCTLR2 54 #define SCR_FEAT_SCTLR2 SCR_SCTLR2En_BIT 55 #else 56 #define SCR_FEAT_SCTLR2 (0) 57 #endif 58 59 #if ENABLE_FEAT_TCR2 60 #define SCR_FEAT_TCR2 SCR_TCR2EN_BIT 61 #else 62 #define SCR_FEAT_TCR2 (0) 63 #endif 64 65 #if ENABLE_FEAT_THE 66 #define SCR_FEAT_THE SCR_RCWMASKEn_BIT 67 #else 68 #define SCR_FEAT_THE (0) 69 #endif 70 71 #if ENABLE_SME_FOR_NS 72 #define SCR_FEAT_SME SCR_ENTP2_BIT 73 #else 74 #define SCR_FEAT_SME (0) 75 #endif 76 77 #if ENABLE_FEAT_GCS 78 #define SCR_FEAT_GCS SCR_GCSEn_BIT 79 #else 80 #define SCR_FEAT_GCS (0) 81 #endif 82 83 #if ENABLE_FEAT_HCX 84 #define SCR_FEAT_HCX SCR_HXEn_BIT 85 #else 86 #define SCR_FEAT_HCX (0) 87 #endif 88 89 #if ENABLE_FEAT_LS64_ACCDATA 90 #define SCR_FEAT_LS64_ACCDATA (SCR_ADEn_BIT | SCR_EnAS0_BIT) 91 #else 92 #define SCR_FEAT_LS64_ACCDATA (0) 93 #endif 94 95 #if ENABLE_FEAT_AMUv1p1 96 #define SCR_FEAT_AMUv1p1 SCR_AMVOFFEN_BIT 97 #else 98 #define SCR_FEAT_AMUv1p1 (0) 99 #endif 100 101 #if ENABLE_FEAT_TWED 102 #define SCR_FEAT_TWED SCR_TWEDEn_BIT 103 #else 104 #define SCR_FEAT_TWED (0) 105 #endif 106 107 #if ENABLE_FEAT_ECV 108 #define SCR_FEAT_ECV SCR_ECVEN_BIT 109 #else 110 #define SCR_FEAT_ECV (0) 111 #endif 112 113 #if ENABLE_FEAT_FGT 114 #define SCR_FEAT_FGT SCR_FGTEN_BIT 115 #else 116 #define SCR_FEAT_FGT (0) 117 #endif 118 119 #if ENABLE_FEAT_MTE2 120 #define SCR_FEAT_MTE2 SCR_ATA_BIT 121 #else 122 #define SCR_FEAT_MTE2 (0) 123 #endif 124 125 #if ENABLE_FEAT_CSV2_2 126 #define SCR_FEAT_CSV2_2 SCR_EnSCXT_BIT 127 #else 128 #define SCR_FEAT_CSV2_2 (0) 129 #endif 130 131 #if !RAS_TRAP_NS_ERR_REC_ACCESS 132 #define SCR_FEAT_RAS SCR_TERR_BIT 133 #else 134 #define SCR_FEAT_RAS (0) 135 #endif 136 137 #if ENABLE_FEAT_MEC 138 #define SCR_FEAT_MEC SCR_MECEn_BIT 139 #else 140 #define SCR_FEAT_MEC (0) 141 #endif 142 143 #ifndef SCR_PLAT_FEATS 144 #define SCR_PLAT_FEATS (0) 145 #endif 146 #ifndef SCR_PLAT_FLIPPED 147 #define SCR_PLAT_FLIPPED (0) 148 #endif 149 #ifndef SCR_PLAT_IGNORED 150 #define SCR_PLAT_IGNORED (0) 151 #endif 152 153 #ifndef CPTR_PLAT_FEATS 154 #define CPTR_PLAT_FEATS (0) 155 #endif 156 #ifndef CPTR_PLAT_FLIPPED 157 #define CPTR_PLAT_FLIPPED (0) 158 #endif 159 160 #ifndef MDCR_PLAT_FEATS 161 #define MDCR_PLAT_FEATS (0) 162 #endif 163 #ifndef MDCR_PLAT_FLIPPED 164 #define MDCR_PLAT_FLIPPED (0) 165 #endif 166 #ifndef MDCR_PLAT_IGNORED 167 #define MDCR_PLAT_IGNORED (0) 168 #endif 169 /* 170 * XYZ_EL3_FEATS - list all bits that are relevant for feature enablement. It's 171 * a constant list based on what features are expected. This relies on the fact 172 * that if the feature is in any way disabled, then the relevant bit will not be 173 * written by context management. 174 * 175 * XYZ_EL3_FLIPPED - bits with an active 0, rather than the usual active 1. The 176 * spec always uses active 1 to mean that the feature will not trap. 177 * 178 * XYZ_EL3_IGNORED - list of all bits that are not relevant for feature 179 * enablement and should not be reported to lower ELs 180 */ 181 #define SCR_EL3_FEATS ( \ 182 SCR_FEAT_FGT2 | \ 183 SCR_FEAT_FPMR | \ 184 SCR_FEAT_MEC | \ 185 SCR_FEAT_D128 | \ 186 SCR_FEAT_S1PIE | \ 187 SCR_FEAT_SCTLR2 | \ 188 SCR_FEAT_TCR2 | \ 189 SCR_FEAT_THE | \ 190 SCR_FEAT_SME | \ 191 SCR_FEAT_GCS | \ 192 SCR_FEAT_HCX | \ 193 SCR_FEAT_LS64_ACCDATA | \ 194 SCR_FEAT_AMUv1p1 | \ 195 SCR_FEAT_TWED | \ 196 SCR_FEAT_ECV | \ 197 SCR_FEAT_FGT | \ 198 SCR_FEAT_MTE2 | \ 199 SCR_FEAT_CSV2_2 | \ 200 SCR_APK_BIT | /* FEAT_Pauth */ \ 201 SCR_FEAT_RAS | \ 202 SCR_PLAT_FEATS) 203 #define SCR_EL3_FLIPPED ( \ 204 SCR_FEAT_RAS | \ 205 SCR_PLAT_FLIPPED) 206 #define SCR_EL3_IGNORED ( \ 207 SCR_API_BIT | \ 208 SCR_RW_BIT | \ 209 SCR_SIF_BIT | \ 210 SCR_HCE_BIT | \ 211 SCR_FIQ_BIT | \ 212 SCR_IRQ_BIT | \ 213 SCR_NS_BIT | \ 214 SCR_NSE_BIT | \ 215 SCR_RES1_BITS | \ 216 SCR_PLAT_IGNORED) 217 CASSERT((SCR_EL3_FEATS & SCR_EL3_IGNORED) == 0, scr_feat_is_ignored); 218 CASSERT((SCR_EL3_FLIPPED & SCR_EL3_FEATS) == SCR_EL3_FLIPPED, scr_flipped_not_a_feat); 219 220 #if ENABLE_SYS_REG_TRACE_FOR_NS 221 #define CPTR_SYS_REG_TRACE (TCPAC_BIT | TTA_BIT) 222 #else 223 #define CPTR_SYS_REG_TRACE (0) 224 #endif 225 226 #if ENABLE_FEAT_AMU 227 #define CPTR_FEAT_AMU TAM_BIT 228 #else 229 #define CPTR_FEAT_AMU (0) 230 #endif 231 232 #if ENABLE_SME_FOR_NS 233 #define CPTR_FEAT_SME ESM_BIT 234 #else 235 #define CPTR_FEAT_SME (0) 236 #endif 237 238 #if ENABLE_SVE_FOR_NS 239 #define CPTR_FEAT_SVE CPTR_EZ_BIT 240 #else 241 #define CPTR_FEAT_SVE (0) 242 #endif 243 244 #define CPTR_EL3_FEATS ( \ 245 CPTR_SYS_REG_TRACE | \ 246 CPTR_FEAT_AMU | \ 247 CPTR_FEAT_SME | \ 248 TFP_BIT | \ 249 CPTR_FEAT_SVE | \ 250 CPTR_PLAT_FEATS) 251 #define CPTR_EL3_FLIPPED ( \ 252 CPTR_SYS_REG_TRACE | \ 253 CPTR_FEAT_AMU | \ 254 TFP_BIT | \ 255 CPTR_PLAT_FLIPPED) 256 CASSERT((CPTR_EL3_FLIPPED & CPTR_EL3_FEATS) == CPTR_EL3_FLIPPED, cptr_flipped_not_a_feat); 257 258 /* 259 * Some features enables are expressed with more than 1 bit in order to cater 260 * for multi world enablement. In those cases (BRB, TRB, SPE) only the last bit 261 * is used and reported. This (ab)uses the convenient fact that the last bit 262 * always means "enabled for this world" when context switched correctly. 263 * The per-world values have been adjusted such that this is always true. 264 */ 265 #if ENABLE_BRBE_FOR_NS 266 #define MDCR_FEAT_BRBE MDCR_SBRBE(1UL) 267 #else 268 #define MDCR_FEAT_BRBE (0) 269 #endif 270 271 #if ENABLE_FEAT_FGT 272 #define MDCR_FEAT_FGT MDCR_TDCC_BIT 273 #else 274 #define MDCR_FEAT_FGT (0) 275 #endif 276 277 #if ENABLE_TRBE_FOR_NS 278 #define MDCR_FEAT_TRBE MDCR_NSTB_EN_BIT 279 #else 280 #define MDCR_FEAT_TRBE (0) 281 #endif 282 283 #if ENABLE_TRF_FOR_NS 284 #define MDCR_FEAT_TRF MDCR_TTRF_BIT 285 #else 286 #define MDCR_FEAT_TRF (0) 287 #endif 288 289 #if ENABLE_SPE_FOR_NS 290 #define MDCR_FEAT_SPE MDCR_NSPB_EN_BIT 291 #else 292 #define MDCR_FEAT_SPE (0) 293 #endif 294 295 #define MDCR_EL3_FEATS ( \ 296 MDCR_FEAT_BRBE | \ 297 MDCR_FEAT_FGT | \ 298 MDCR_FEAT_TRBE | \ 299 MDCR_FEAT_TRF | \ 300 MDCR_FEAT_SPE | \ 301 MDCR_TDOSA_BIT | \ 302 MDCR_TDA_BIT | \ 303 MDCR_EnPM2_BIT | \ 304 MDCR_TPM_BIT | /* FEAT_PMUv3 */ \ 305 MDCR_PLAT_FEATS) 306 #define MDCR_EL3_FLIPPED ( \ 307 MDCR_FEAT_FGT | \ 308 MDCR_FEAT_TRF | \ 309 MDCR_TDOSA_BIT | \ 310 MDCR_TDA_BIT | \ 311 MDCR_TPM_BIT | \ 312 MDCR_PLAT_FLIPPED) 313 #define MDCR_EL3_IGNORED ( \ 314 MDCR_EBWE_BIT | \ 315 MDCR_EnPMS3_BIT | \ 316 MDCR_EnPMSN_BIT | \ 317 MDCR_SBRBE(2UL) | \ 318 MDCR_MTPME_BIT | \ 319 MDCR_NSTBE_BIT | \ 320 MDCR_NSTB_SS_BIT | \ 321 MDCR_MCCD_BIT | \ 322 MDCR_SCCD_BIT | \ 323 MDCR_SDD_BIT | \ 324 MDCR_SPD32(3UL) | \ 325 MDCR_NSPB_SS_BIT | \ 326 MDCR_NSPBE_BIT | \ 327 MDCR_PLAT_IGNORED) 328 CASSERT((MDCR_EL3_FEATS & MDCR_EL3_IGNORED) == 0, mdcr_feat_is_ignored); 329 CASSERT((MDCR_EL3_FLIPPED & MDCR_EL3_FEATS) == MDCR_EL3_FLIPPED, mdcr_flipped_not_a_feat); 330 331 #define MPAM3_EL3_FEATS (MPAM3_EL3_TRAPLOWER_BIT) 332 #define MPAM3_EL3_FLIPPED (MPAM3_EL3_TRAPLOWER_BIT) 333 #define MPAM3_EL3_IGNORED (MPAM3_EL3_MPAMEN_BIT) 334 CASSERT((MPAM3_EL3_FEATS & MPAM3_EL3_IGNORED) == 0, mpam3_feat_is_ignored); 335 CASSERT((MPAM3_EL3_FLIPPED & MPAM3_EL3_FEATS) == MPAM3_EL3_FLIPPED, mpam3_flipped_not_a_feat); 336 337 /* The hex representations of these registers' S3 encoding */ 338 #define SCR_EL3_OPCODE U(0x1E1100) 339 #define CPTR_EL3_OPCODE U(0x1E1140) 340 #define MDCR_EL3_OPCODE U(0x1E1320) 341 #define MPAM3_EL3_OPCODE U(0x1EA500) 342 343 #endif /* ARCH_FEATURE_AVAILABILITY */ 344 #endif /* __ASSEMBLER__ */ 345 #endif /* ARM_ARCH_SVC_H */ 346