1 #ifndef __ODY_CSRS_SAM_H__ 2 #define __ODY_CSRS_SAM_H__ 3 /* This file is auto-generated. Do not edit */ 4 5 /***********************license start*********************************** 6 * Copyright (C) 2021-2026 Marvell. 7 * SPDX-License-Identifier: BSD-3-Clause 8 * https://spdx.org/licenses 9 ***********************license end**************************************/ 10 11 12 /** 13 * @file 14 * 15 * Configuration and status register (CSR) address and type definitions for 16 * SAM. 17 * 18 * This file is auto generated. Do not edit. 19 * 20 */ 21 22 /** 23 * Enumeration sam_bar_e 24 * 25 * SAM Base Address Register Enumeration 26 * Enumerates the base address registers. 27 */ 28 #define ODY_SAM_BAR_E_SAM_PF_BAR0 (0x87e059000000ll) 29 #define ODY_SAM_BAR_E_SAM_PF_BAR0_SIZE 0x10000ull 30 31 /** 32 * Enumeration sam_dmc_size_e 33 * 34 * SAM DMC Size Enumeration 35 * Size of each memory channel 36 */ 37 #define ODY_SAM_DMC_SIZE_E_S_12GB (2) 38 #define ODY_SAM_DMC_SIZE_E_S_192GB (6) 39 #define ODY_SAM_DMC_SIZE_E_S_24GB (3) 40 #define ODY_SAM_DMC_SIZE_E_S_384GB (7) 41 #define ODY_SAM_DMC_SIZE_E_S_48GB (4) 42 #define ODY_SAM_DMC_SIZE_E_S_6GB (1) 43 #define ODY_SAM_DMC_SIZE_E_S_96GB (5) 44 #define ODY_SAM_DMC_SIZE_E_S_PWR2 (0) 45 46 /** 47 * Enumeration sam_dmc_stripe_e 48 * 49 * SAM DMC Stripe Enumeration 50 * Number of aligned consecutive bytes to keep within a memory channel 51 */ 52 #define ODY_SAM_DMC_STRIPE_E_RSVD (3) 53 #define ODY_SAM_DMC_STRIPE_E_S_128B (1) 54 #define ODY_SAM_DMC_STRIPE_E_S_256B (2) 55 #define ODY_SAM_DMC_STRIPE_E_S_64B (0) 56 57 /** 58 * Register (RSL) sam_asc_region#_attr 59 * 60 * SAM Address Space Control Region Attributes Registers 61 */ 62 union ody_sam_asc_regionx_attr { 63 uint64_t u; 64 struct ody_sam_asc_regionx_attr_s { 65 uint64_t reserved_0_19 : 20; 66 uint64_t ns_en : 1; 67 uint64_t s_en : 1; 68 uint64_t reserved_22_63 : 42; 69 } s; 70 /* struct ody_sam_asc_regionx_attr_s cn; */ 71 }; 72 typedef union ody_sam_asc_regionx_attr ody_sam_asc_regionx_attr_t; 73 74 static inline uint64_t ODY_SAM_ASC_REGIONX_ATTR(uint64_t a) __attribute__ ((pure, always_inline)); 75 static inline uint64_t ODY_SAM_ASC_REGIONX_ATTR(uint64_t a) 76 { 77 if (a <= 3) 78 return 0x87e059000018ll + 0x20ll * ((a) & 0x3); 79 __ody_csr_fatal("SAM_ASC_REGIONX_ATTR", 1, a, 0, 0, 0, 0, 0); 80 } 81 82 #define typedef_ODY_SAM_ASC_REGIONX_ATTR(a) ody_sam_asc_regionx_attr_t 83 #define bustype_ODY_SAM_ASC_REGIONX_ATTR(a) CSR_TYPE_RSL 84 #define basename_ODY_SAM_ASC_REGIONX_ATTR(a) "SAM_ASC_REGIONX_ATTR" 85 #define device_bar_ODY_SAM_ASC_REGIONX_ATTR(a) 0x0 /* PF_BAR0 */ 86 #define busnum_ODY_SAM_ASC_REGIONX_ATTR(a) (a) 87 #define arguments_ODY_SAM_ASC_REGIONX_ATTR(a) (a), -1, -1, -1 88 89 /** 90 * Register (RSL) sam_asc_region#_end 91 * 92 * SAM Address Space Control Region End Address Registers 93 */ 94 union ody_sam_asc_regionx_end { 95 uint64_t u; 96 struct ody_sam_asc_regionx_end_s { 97 uint64_t reserved_0_20 : 21; 98 uint64_t addr : 23; 99 uint64_t reserved_44_63 : 20; 100 } s; 101 /* struct ody_sam_asc_regionx_end_s cn; */ 102 }; 103 typedef union ody_sam_asc_regionx_end ody_sam_asc_regionx_end_t; 104 105 static inline uint64_t ODY_SAM_ASC_REGIONX_END(uint64_t a) __attribute__ ((pure, always_inline)); 106 static inline uint64_t ODY_SAM_ASC_REGIONX_END(uint64_t a) 107 { 108 if (a <= 3) 109 return 0x87e059000008ll + 0x20ll * ((a) & 0x3); 110 __ody_csr_fatal("SAM_ASC_REGIONX_END", 1, a, 0, 0, 0, 0, 0); 111 } 112 113 #define typedef_ODY_SAM_ASC_REGIONX_END(a) ody_sam_asc_regionx_end_t 114 #define bustype_ODY_SAM_ASC_REGIONX_END(a) CSR_TYPE_RSL 115 #define basename_ODY_SAM_ASC_REGIONX_END(a) "SAM_ASC_REGIONX_END" 116 #define device_bar_ODY_SAM_ASC_REGIONX_END(a) 0x0 /* PF_BAR0 */ 117 #define busnum_ODY_SAM_ASC_REGIONX_END(a) (a) 118 #define arguments_ODY_SAM_ASC_REGIONX_END(a) (a), -1, -1, -1 119 120 /** 121 * Register (RSL) sam_asc_region#_start 122 * 123 * SAM Address Space Control Region Start Address Registers 124 */ 125 union ody_sam_asc_regionx_start { 126 uint64_t u; 127 struct ody_sam_asc_regionx_start_s { 128 uint64_t reserved_0_20 : 21; 129 uint64_t addr : 23; 130 uint64_t reserved_44_63 : 20; 131 } s; 132 /* struct ody_sam_asc_regionx_start_s cn; */ 133 }; 134 typedef union ody_sam_asc_regionx_start ody_sam_asc_regionx_start_t; 135 136 static inline uint64_t ODY_SAM_ASC_REGIONX_START(uint64_t a) __attribute__ ((pure, always_inline)); 137 static inline uint64_t ODY_SAM_ASC_REGIONX_START(uint64_t a) 138 { 139 if (a <= 3) 140 return 0x87e059000000ll + 0x20ll * ((a) & 0x3); 141 __ody_csr_fatal("SAM_ASC_REGIONX_START", 1, a, 0, 0, 0, 0, 0); 142 } 143 144 #define typedef_ODY_SAM_ASC_REGIONX_START(a) ody_sam_asc_regionx_start_t 145 #define bustype_ODY_SAM_ASC_REGIONX_START(a) CSR_TYPE_RSL 146 #define basename_ODY_SAM_ASC_REGIONX_START(a) "SAM_ASC_REGIONX_START" 147 #define device_bar_ODY_SAM_ASC_REGIONX_START(a) 0x0 /* PF_BAR0 */ 148 #define busnum_ODY_SAM_ASC_REGIONX_START(a) (a) 149 #define arguments_ODY_SAM_ASC_REGIONX_START(a) (a), -1, -1, -1 150 151 /** 152 * Register (RSL) sam_cfg 153 * 154 * SAM Configuration Register 155 * This register holds configuration information. 156 */ 157 union ody_sam_cfg { 158 uint64_t u; 159 struct ody_sam_cfg_s { 160 uint64_t dss_ch : 4; 161 uint64_t dmc_2ch : 1; 162 uint64_t dmc_size : 3; 163 uint64_t dmc_stripe : 2; 164 uint64_t dss_columns_dis : 5; 165 uint64_t reserved_15_63 : 49; 166 } s; 167 /* struct ody_sam_cfg_s cn; */ 168 }; 169 typedef union ody_sam_cfg ody_sam_cfg_t; 170 171 #define ODY_SAM_CFG ODY_SAM_CFG_FUNC() 172 static inline uint64_t ODY_SAM_CFG_FUNC(void) __attribute__ ((pure, always_inline)); 173 static inline uint64_t ODY_SAM_CFG_FUNC(void) 174 { 175 return 0x87e059000400ll; 176 } 177 178 #define typedef_ODY_SAM_CFG ody_sam_cfg_t 179 #define bustype_ODY_SAM_CFG CSR_TYPE_RSL 180 #define basename_ODY_SAM_CFG "SAM_CFG" 181 #define device_bar_ODY_SAM_CFG 0x0 /* PF_BAR0 */ 182 #define busnum_ODY_SAM_CFG 0 183 #define arguments_ODY_SAM_CFG -1, -1, -1, -1 184 185 /** 186 * Register (RSL) sam_hash# 187 * 188 * SAM hash matrix coefficients Registers 189 * This hash matrix is used to spread addresses among tiles/sets. Each register 190 * represents an output bit. Each coefficient bit represents inputs that are XOR'd to 191 * create the output bit. bit. HASH(16..0)[CO]\<22:6\> must form an invertible 192 * matrix. Input bit 6 must only affect output bit 6. Input bit 7 must only affect 193 * output bits 6 and 7. It is recommended that every 17x17 submatrix is invertible for 194 * best stride resistance. If scratch mode is used in a 10 DSS system, SAM_HASH(16..15) 195 * must come from the identity matrix. If scratch mode is used is a 4 DSS system, 196 * SAM_HASH(16) must come from the identity matrix. The reset value is compatible with 197 * a 10 DSS system. 198 */ 199 union ody_sam_hashx { 200 uint64_t u; 201 struct ody_sam_hashx_s { 202 uint64_t reserved_0_5 : 6; 203 uint64_t co : 38; 204 uint64_t reserved_44_63 : 20; 205 } s; 206 /* struct ody_sam_hashx_s cn; */ 207 }; 208 typedef union ody_sam_hashx ody_sam_hashx_t; 209 210 static inline uint64_t ODY_SAM_HASHX(uint64_t a) __attribute__ ((pure, always_inline)); 211 static inline uint64_t ODY_SAM_HASHX(uint64_t a) 212 { 213 if (a <= 16) 214 return 0x87e059004000ll + 8ll * ((a) & 0x1f); 215 __ody_csr_fatal("SAM_HASHX", 1, a, 0, 0, 0, 0, 0); 216 } 217 218 #define typedef_ODY_SAM_HASHX(a) ody_sam_hashx_t 219 #define bustype_ODY_SAM_HASHX(a) CSR_TYPE_RSL 220 #define basename_ODY_SAM_HASHX(a) "SAM_HASHX" 221 #define device_bar_ODY_SAM_HASHX(a) 0x0 /* PF_BAR0 */ 222 #define busnum_ODY_SAM_HASHX(a) (a) 223 #define arguments_ODY_SAM_HASHX(a) (a), -1, -1, -1 224 225 /** 226 * Register (RSL) sam_ihash# 227 * 228 * SAM inverse hash matrix coefficients Registers 229 * This matrix must be the inverse of SAM_HASH 230 */ 231 union ody_sam_ihashx { 232 uint64_t u; 233 struct ody_sam_ihashx_s { 234 uint64_t reserved_0_5 : 6; 235 uint64_t co : 38; 236 uint64_t reserved_44_63 : 20; 237 } s; 238 /* struct ody_sam_ihashx_s cn; */ 239 }; 240 typedef union ody_sam_ihashx ody_sam_ihashx_t; 241 242 static inline uint64_t ODY_SAM_IHASHX(uint64_t a) __attribute__ ((pure, always_inline)); 243 static inline uint64_t ODY_SAM_IHASHX(uint64_t a) 244 { 245 if (a <= 16) 246 return 0x87e059004100ll + 8ll * ((a) & 0x1f); 247 __ody_csr_fatal("SAM_IHASHX", 1, a, 0, 0, 0, 0, 0); 248 } 249 250 #define typedef_ODY_SAM_IHASHX(a) ody_sam_ihashx_t 251 #define bustype_ODY_SAM_IHASHX(a) CSR_TYPE_RSL 252 #define basename_ODY_SAM_IHASHX(a) "SAM_IHASHX" 253 #define device_bar_ODY_SAM_IHASHX(a) 0x0 /* PF_BAR0 */ 254 #define busnum_ODY_SAM_IHASHX(a) (a) 255 #define arguments_ODY_SAM_IHASHX(a) (a), -1, -1, -1 256 257 /** 258 * Register (RSL) sam_mn_map# 259 * 260 * SAM MN Map Registers 261 * These registers specify the location of MN. Note that it is illegal to provision an 262 * MN on a tile with a TAD that is disabled for any reason. 263 */ 264 union ody_sam_mn_mapx { 265 uint64_t u; 266 struct ody_sam_mn_mapx_s { 267 uint64_t y : 4; 268 uint64_t x : 4; 269 uint64_t val : 1; 270 uint64_t reserved_9_63 : 55; 271 } s; 272 /* struct ody_sam_mn_mapx_s cn; */ 273 }; 274 typedef union ody_sam_mn_mapx ody_sam_mn_mapx_t; 275 276 static inline uint64_t ODY_SAM_MN_MAPX(uint64_t a) __attribute__ ((pure, always_inline)); 277 static inline uint64_t ODY_SAM_MN_MAPX(uint64_t a) 278 { 279 if (a <= 7) 280 return 0x87e059004200ll + 8ll * ((a) & 0x7); 281 __ody_csr_fatal("SAM_MN_MAPX", 1, a, 0, 0, 0, 0, 0); 282 } 283 284 #define typedef_ODY_SAM_MN_MAPX(a) ody_sam_mn_mapx_t 285 #define bustype_ODY_SAM_MN_MAPX(a) CSR_TYPE_RSL 286 #define basename_ODY_SAM_MN_MAPX(a) "SAM_MN_MAPX" 287 #define device_bar_ODY_SAM_MN_MAPX(a) 0x0 /* PF_BAR0 */ 288 #define busnum_ODY_SAM_MN_MAPX(a) (a) 289 #define arguments_ODY_SAM_MN_MAPX(a) (a), -1, -1, -1 290 291 /** 292 * Register (RSL) sam_ncb#_const 293 * 294 * SAM Processor Number Routing Map Registers 295 * A table of IOB routing destinations. 296 * 297 * \<pre\> 298 * Index a bus Bus index 299 * ------- --- --------- 300 * 00-3F NCB DID 00-3F 301 * 40-5F NCB DID 60-7F 302 * 60-7F NCB DID E0-FF 303 * 80-BF ECAM DOM 00-3F 304 * C0-CF PEM DID 00-0F 305 * D0-FF Reserved 306 * \</pre\> 307 */ 308 union ody_sam_ncbx_const { 309 uint64_t u; 310 struct ody_sam_ncbx_const_s { 311 uint64_t valid : 1; 312 uint64_t iob : 3; 313 uint64_t ncb : 2; 314 uint64_t reserved_6_7 : 2; 315 uint64_t arbid : 4; 316 uint64_t reserved_12_63 : 52; 317 } s; 318 /* struct ody_sam_ncbx_const_s cn; */ 319 }; 320 typedef union ody_sam_ncbx_const ody_sam_ncbx_const_t; 321 322 static inline uint64_t ODY_SAM_NCBX_CONST(uint64_t a) __attribute__ ((pure, always_inline)); 323 static inline uint64_t ODY_SAM_NCBX_CONST(uint64_t a) 324 { 325 if (a <= 255) 326 return 0x87e059008800ll + 8ll * ((a) & 0xff); 327 __ody_csr_fatal("SAM_NCBX_CONST", 1, a, 0, 0, 0, 0, 0); 328 } 329 330 #define typedef_ODY_SAM_NCBX_CONST(a) ody_sam_ncbx_const_t 331 #define bustype_ODY_SAM_NCBX_CONST(a) CSR_TYPE_RSL 332 #define basename_ODY_SAM_NCBX_CONST(a) "SAM_NCBX_CONST" 333 #define device_bar_ODY_SAM_NCBX_CONST(a) 0x0 /* PF_BAR0 */ 334 #define busnum_ODY_SAM_NCBX_CONST(a) (a) 335 #define arguments_ODY_SAM_NCBX_CONST(a) (a), -1, -1, -1 336 337 /** 338 * Register (RSL) sam_pn_map# 339 * 340 * SAM Processor Number Routing Map Registers 341 * A table of routing destinations indexed by logical processor number. The default 342 * numbering is row-major. 343 */ 344 union ody_sam_pn_mapx { 345 uint64_t u; 346 struct ody_sam_pn_mapx_s { 347 uint64_t y : 4; 348 uint64_t x : 4; 349 uint64_t val : 1; 350 uint64_t reserved_9_63 : 55; 351 } s; 352 /* struct ody_sam_pn_mapx_s cn; */ 353 }; 354 typedef union ody_sam_pn_mapx ody_sam_pn_mapx_t; 355 356 static inline uint64_t ODY_SAM_PN_MAPX(uint64_t a) __attribute__ ((pure, always_inline)); 357 static inline uint64_t ODY_SAM_PN_MAPX(uint64_t a) 358 { 359 if (a <= 81) 360 return 0x87e059000800ll + 8ll * ((a) & 0x7f); 361 __ody_csr_fatal("SAM_PN_MAPX", 1, a, 0, 0, 0, 0, 0); 362 } 363 364 #define typedef_ODY_SAM_PN_MAPX(a) ody_sam_pn_mapx_t 365 #define bustype_ODY_SAM_PN_MAPX(a) CSR_TYPE_RSL 366 #define basename_ODY_SAM_PN_MAPX(a) "SAM_PN_MAPX" 367 #define device_bar_ODY_SAM_PN_MAPX(a) 0x0 /* PF_BAR0 */ 368 #define busnum_ODY_SAM_PN_MAPX(a) (a) 369 #define arguments_ODY_SAM_PN_MAPX(a) (a), -1, -1, -1 370 371 #endif /* __ODY_CSRS_SAM_H__ */ 372