1 #ifndef __ODY_CSRS_MDC_H__ 2 #define __ODY_CSRS_MDC_H__ 3 /* This file is auto-generated. Do not edit */ 4 5 /***********************license start*********************************** 6 * Copyright (C) 2021-2026 Marvell. 7 * SPDX-License-Identifier: BSD-3-Clause 8 * https://spdx.org/licenses 9 ***********************license end**************************************/ 10 11 12 /** 13 * @file 14 * 15 * Configuration and status register (CSR) address and type definitions for 16 * MDC. 17 * 18 * This file is auto generated. Do not edit. 19 * 20 */ 21 22 /** 23 * Enumeration mdc_bar_e 24 * 25 * MDC Base Address Register Enumeration 26 * Enumerates the base address registers. 27 */ 28 #define ODY_MDC_BAR_E_MDC_PF_BAR0 (0x87e010000000ll) 29 #define ODY_MDC_BAR_E_MDC_PF_BAR0_SIZE 0x100000ull 30 #define ODY_MDC_BAR_E_MDC_PF_BAR2 (0x87e008000000ll) 31 #define ODY_MDC_BAR_E_MDC_PF_BAR2_SIZE 0x1000000ull 32 #define ODY_MDC_BAR_E_MDC_PF_BAR4 (0x87e010100000ll) 33 #define ODY_MDC_BAR_E_MDC_PF_BAR4_SIZE 0x100000ull 34 35 /** 36 * Enumeration mdc_int_vec_e 37 * 38 * MDC Interrupt Source Enumeration 39 * Enumerates the different MDC-generated interrupts. 40 */ 41 #define ODY_MDC_INT_VEC_E_MDC_ECC_ERR (0) 42 43 /** 44 * Enumeration mdc_ras_uet_e 45 * 46 * MDC RAS Uncorrected Error Type Enumeration 47 * Enumerates the uncorrected error types in MDC_RAS_ROM(). See also RAS_UET_E of which 48 * this enumeration is a superset. 49 */ 50 #define ODY_MDC_RAS_UET_E_NOUC (4) 51 #define ODY_MDC_RAS_UET_E_UC (0) 52 #define ODY_MDC_RAS_UET_E_UEO (2) 53 #define ODY_MDC_RAS_UET_E_UER (3) 54 #define ODY_MDC_RAS_UET_E_UEU (1) 55 56 /** 57 * Structure mdc_ras_entry_s 58 * 59 * MDN RAS Entry Structure 60 * This structure describes the leaf node data returned from MDC_RAS_ROM(). 61 */ 62 union ody_mdc_ras_entry_s { 63 uint64_t u; 64 struct ody_mdc_ras_entry_s_s { 65 uint64_t reserved_0_17 : 18; 66 uint64_t ras_poison : 2; 67 uint64_t ras_transient : 1; 68 uint64_t ras_uet : 3; 69 uint64_t ras_serr : 8; 70 uint64_t ras_id : 32; 71 } s; 72 /* struct ody_mdc_ras_entry_s_s cn; */ 73 }; 74 75 /** 76 * Register (RSL) mdc_active_pc 77 * 78 * MDC Active Cycles Register 79 */ 80 union ody_mdc_active_pc { 81 uint64_t u; 82 struct ody_mdc_active_pc_s { 83 uint64_t act_cyc : 64; 84 } s; 85 /* struct ody_mdc_active_pc_s cn; */ 86 }; 87 typedef union ody_mdc_active_pc ody_mdc_active_pc_t; 88 89 #define ODY_MDC_ACTIVE_PC ODY_MDC_ACTIVE_PC_FUNC() 90 static inline uint64_t ODY_MDC_ACTIVE_PC_FUNC(void) __attribute__ ((pure, always_inline)); 91 static inline uint64_t ODY_MDC_ACTIVE_PC_FUNC(void) 92 { 93 return 0x87e0100000e8ll; 94 } 95 96 #define typedef_ODY_MDC_ACTIVE_PC ody_mdc_active_pc_t 97 #define bustype_ODY_MDC_ACTIVE_PC CSR_TYPE_RSL 98 #define basename_ODY_MDC_ACTIVE_PC "MDC_ACTIVE_PC" 99 #define device_bar_ODY_MDC_ACTIVE_PC 0x0 /* PF_BAR0 */ 100 #define busnum_ODY_MDC_ACTIVE_PC 0 101 #define arguments_ODY_MDC_ACTIVE_PC -1, -1, -1, -1 102 103 /** 104 * Register (RSL) mdc_bist_config 105 * 106 * MDC Configuration Register 107 */ 108 union ody_mdc_bist_config { 109 uint64_t u; 110 struct ody_mdc_bist_config_s { 111 uint64_t stagger_period : 16; 112 uint64_t stagger_disable : 1; 113 uint64_t bisr_soft_disable_xor : 1; 114 uint64_t mdn_start_ratio : 4; 115 uint64_t mdh_start_ratio : 3; 116 uint64_t mdc_broadcast : 1; 117 uint64_t clock_gating_enable : 1; 118 uint64_t reserved_27_63 : 37; 119 } s; 120 /* struct ody_mdc_bist_config_s cn; */ 121 }; 122 typedef union ody_mdc_bist_config ody_mdc_bist_config_t; 123 124 #define ODY_MDC_BIST_CONFIG ODY_MDC_BIST_CONFIG_FUNC() 125 static inline uint64_t ODY_MDC_BIST_CONFIG_FUNC(void) __attribute__ ((pure, always_inline)); 126 static inline uint64_t ODY_MDC_BIST_CONFIG_FUNC(void) 127 { 128 return 0x87e010000008ll; 129 } 130 131 #define typedef_ODY_MDC_BIST_CONFIG ody_mdc_bist_config_t 132 #define bustype_ODY_MDC_BIST_CONFIG CSR_TYPE_RSL 133 #define basename_ODY_MDC_BIST_CONFIG "MDC_BIST_CONFIG" 134 #define device_bar_ODY_MDC_BIST_CONFIG 0x0 /* PF_BAR0 */ 135 #define busnum_ODY_MDC_BIST_CONFIG 0 136 #define arguments_ODY_MDC_BIST_CONFIG -1, -1, -1, -1 137 138 /** 139 * Register (RSL) mdc_bist_control 140 * 141 * MDC Global BIST Control Register 142 */ 143 union ody_mdc_bist_control { 144 uint64_t u; 145 struct ody_mdc_bist_control_s { 146 uint64_t start : 1; 147 uint64_t clear : 1; 148 uint64_t reset : 1; 149 uint64_t reserved_3_63 : 61; 150 } s; 151 /* struct ody_mdc_bist_control_s cn; */ 152 }; 153 typedef union ody_mdc_bist_control ody_mdc_bist_control_t; 154 155 #define ODY_MDC_BIST_CONTROL ODY_MDC_BIST_CONTROL_FUNC() 156 static inline uint64_t ODY_MDC_BIST_CONTROL_FUNC(void) __attribute__ ((pure, always_inline)); 157 static inline uint64_t ODY_MDC_BIST_CONTROL_FUNC(void) 158 { 159 return 0x87e010000028ll; 160 } 161 162 #define typedef_ODY_MDC_BIST_CONTROL ody_mdc_bist_control_t 163 #define bustype_ODY_MDC_BIST_CONTROL CSR_TYPE_RSL 164 #define basename_ODY_MDC_BIST_CONTROL "MDC_BIST_CONTROL" 165 #define device_bar_ODY_MDC_BIST_CONTROL 0x0 /* PF_BAR0 */ 166 #define busnum_ODY_MDC_BIST_CONTROL 0 167 #define arguments_ODY_MDC_BIST_CONTROL -1, -1, -1, -1 168 169 /** 170 * Register (RSL) mdc_bist_debug_mode 171 * 172 * MDC Configuration Register 173 */ 174 union ody_mdc_bist_debug_mode { 175 uint64_t u; 176 struct ody_mdc_bist_debug_mode_s { 177 uint64_t enable : 1; 178 uint64_t reserved_1_63 : 63; 179 } s; 180 /* struct ody_mdc_bist_debug_mode_s cn; */ 181 }; 182 typedef union ody_mdc_bist_debug_mode ody_mdc_bist_debug_mode_t; 183 184 #define ODY_MDC_BIST_DEBUG_MODE ODY_MDC_BIST_DEBUG_MODE_FUNC() 185 static inline uint64_t ODY_MDC_BIST_DEBUG_MODE_FUNC(void) __attribute__ ((pure, always_inline)); 186 static inline uint64_t ODY_MDC_BIST_DEBUG_MODE_FUNC(void) 187 { 188 return 0x87e010000000ll; 189 } 190 191 #define typedef_ODY_MDC_BIST_DEBUG_MODE ody_mdc_bist_debug_mode_t 192 #define bustype_ODY_MDC_BIST_DEBUG_MODE CSR_TYPE_RSL 193 #define basename_ODY_MDC_BIST_DEBUG_MODE "MDC_BIST_DEBUG_MODE" 194 #define device_bar_ODY_MDC_BIST_DEBUG_MODE 0x0 /* PF_BAR0 */ 195 #define busnum_ODY_MDC_BIST_DEBUG_MODE 0 196 #define arguments_ODY_MDC_BIST_DEBUG_MODE -1, -1, -1, -1 197 198 /** 199 * Register (RSL) mdc_bist_fail# 200 * 201 * MDC BIST Failures Register 202 * This register array holds information about the first 32 BIST failures. 203 */ 204 union ody_mdc_bist_failx { 205 uint64_t u; 206 struct ody_mdc_bist_failx_s { 207 uint64_t info : 12; 208 uint64_t node_id : 10; 209 uint64_t hub_id : 7; 210 uint64_t chain_id : 3; 211 uint64_t reserved_32_63 : 32; 212 } s; 213 /* struct ody_mdc_bist_failx_s cn; */ 214 }; 215 typedef union ody_mdc_bist_failx ody_mdc_bist_failx_t; 216 217 static inline uint64_t ODY_MDC_BIST_FAILX(uint64_t a) __attribute__ ((pure, always_inline)); 218 static inline uint64_t ODY_MDC_BIST_FAILX(uint64_t a) 219 { 220 if (a <= 31) 221 return 0x87e010000100ll + 8ll * ((a) & 0x1f); 222 __ody_csr_fatal("MDC_BIST_FAILX", 1, a, 0, 0, 0, 0, 0); 223 } 224 225 #define typedef_ODY_MDC_BIST_FAILX(a) ody_mdc_bist_failx_t 226 #define bustype_ODY_MDC_BIST_FAILX(a) CSR_TYPE_RSL 227 #define basename_ODY_MDC_BIST_FAILX(a) "MDC_BIST_FAILX" 228 #define device_bar_ODY_MDC_BIST_FAILX(a) 0x0 /* PF_BAR0 */ 229 #define busnum_ODY_MDC_BIST_FAILX(a) (a) 230 #define arguments_ODY_MDC_BIST_FAILX(a) (a), -1, -1, -1 231 232 /** 233 * Register (RSL) mdc_bist_status 234 * 235 * MDC Global BIST Status Register 236 */ 237 union ody_mdc_bist_status { 238 uint64_t u; 239 struct ody_mdc_bist_status_s { 240 uint64_t status : 3; 241 uint64_t rst_bist_req : 1; 242 uint64_t reserved_4_15 : 12; 243 uint64_t fail_count : 16; 244 uint64_t sm_state : 6; 245 uint64_t reserved_38_63 : 26; 246 } s; 247 /* struct ody_mdc_bist_status_s cn; */ 248 }; 249 typedef union ody_mdc_bist_status ody_mdc_bist_status_t; 250 251 #define ODY_MDC_BIST_STATUS ODY_MDC_BIST_STATUS_FUNC() 252 static inline uint64_t ODY_MDC_BIST_STATUS_FUNC(void) __attribute__ ((pure, always_inline)); 253 static inline uint64_t ODY_MDC_BIST_STATUS_FUNC(void) 254 { 255 return 0x87e010000030ll; 256 } 257 258 #define typedef_ODY_MDC_BIST_STATUS ody_mdc_bist_status_t 259 #define bustype_ODY_MDC_BIST_STATUS CSR_TYPE_RSL 260 #define basename_ODY_MDC_BIST_STATUS "MDC_BIST_STATUS" 261 #define device_bar_ODY_MDC_BIST_STATUS 0x0 /* PF_BAR0 */ 262 #define busnum_ODY_MDC_BIST_STATUS 0 263 #define arguments_ODY_MDC_BIST_STATUS -1, -1, -1, -1 264 265 /** 266 * Register (RSL) mdc_const 267 * 268 * MDC Constants Register 269 */ 270 union ody_mdc_const { 271 uint64_t u; 272 struct ody_mdc_const_s { 273 uint64_t reserved_0_15 : 16; 274 uint64_t max_node_id : 10; 275 uint64_t max_hub_id : 8; 276 uint64_t max_chain_id : 5; 277 uint64_t reserved_39_63 : 25; 278 } s; 279 /* struct ody_mdc_const_s cn; */ 280 }; 281 typedef union ody_mdc_const ody_mdc_const_t; 282 283 #define ODY_MDC_CONST ODY_MDC_CONST_FUNC() 284 static inline uint64_t ODY_MDC_CONST_FUNC(void) __attribute__ ((pure, always_inline)); 285 static inline uint64_t ODY_MDC_CONST_FUNC(void) 286 { 287 return 0x87e010000068ll; 288 } 289 290 #define typedef_ODY_MDC_CONST ody_mdc_const_t 291 #define bustype_ODY_MDC_CONST CSR_TYPE_RSL 292 #define basename_ODY_MDC_CONST "MDC_CONST" 293 #define device_bar_ODY_MDC_CONST 0x0 /* PF_BAR0 */ 294 #define busnum_ODY_MDC_CONST 0 295 #define arguments_ODY_MDC_CONST -1, -1, -1, -1 296 297 /** 298 * Register (RSL) mdc_ecc_config 299 * 300 * MDC ECC Configuration Register 301 */ 302 union ody_mdc_ecc_config { 303 uint64_t u; 304 struct ody_mdc_ecc_config_s { 305 uint64_t polling_period : 32; 306 uint64_t reserved_32_63 : 32; 307 } s; 308 /* struct ody_mdc_ecc_config_s cn; */ 309 }; 310 typedef union ody_mdc_ecc_config ody_mdc_ecc_config_t; 311 312 #define ODY_MDC_ECC_CONFIG ODY_MDC_ECC_CONFIG_FUNC() 313 static inline uint64_t ODY_MDC_ECC_CONFIG_FUNC(void) __attribute__ ((pure, always_inline)); 314 static inline uint64_t ODY_MDC_ECC_CONFIG_FUNC(void) 315 { 316 return 0x87e010000038ll; 317 } 318 319 #define typedef_ODY_MDC_ECC_CONFIG ody_mdc_ecc_config_t 320 #define bustype_ODY_MDC_ECC_CONFIG CSR_TYPE_RSL 321 #define basename_ODY_MDC_ECC_CONFIG "MDC_ECC_CONFIG" 322 #define device_bar_ODY_MDC_ECC_CONFIG 0x0 /* PF_BAR0 */ 323 #define busnum_ODY_MDC_ECC_CONFIG 0 324 #define arguments_ODY_MDC_ECC_CONFIG -1, -1, -1, -1 325 326 /** 327 * Register (RSL) mdc_ecc_status 328 * 329 * MDC Interrupt Status Register 330 */ 331 union ody_mdc_ecc_status { 332 uint64_t u; 333 struct ody_mdc_ecc_status_s { 334 uint64_t sbe : 1; 335 uint64_t dbe : 1; 336 uint64_t sbe_plus : 1; 337 uint64_t dbe_plus : 1; 338 uint64_t reserved_4_15 : 12; 339 uint64_t node_id : 10; 340 uint64_t hub_id : 7; 341 uint64_t chain_id : 3; 342 uint64_t reserved_36_47 : 12; 343 uint64_t row : 14; 344 uint64_t reserved_62_63 : 2; 345 } s; 346 /* struct ody_mdc_ecc_status_s cn; */ 347 }; 348 typedef union ody_mdc_ecc_status ody_mdc_ecc_status_t; 349 350 #define ODY_MDC_ECC_STATUS ODY_MDC_ECC_STATUS_FUNC() 351 static inline uint64_t ODY_MDC_ECC_STATUS_FUNC(void) __attribute__ ((pure, always_inline)); 352 static inline uint64_t ODY_MDC_ECC_STATUS_FUNC(void) 353 { 354 return 0x87e010000040ll; 355 } 356 357 #define typedef_ODY_MDC_ECC_STATUS ody_mdc_ecc_status_t 358 #define bustype_ODY_MDC_ECC_STATUS CSR_TYPE_RSL 359 #define basename_ODY_MDC_ECC_STATUS "MDC_ECC_STATUS" 360 #define device_bar_ODY_MDC_ECC_STATUS 0x0 /* PF_BAR0 */ 361 #define busnum_ODY_MDC_ECC_STATUS 0 362 #define arguments_ODY_MDC_ECC_STATUS -1, -1, -1, -1 363 364 /** 365 * Register (RSL) mdc_int_ena_w1c 366 * 367 * MDC Interrupt Enable Write-1-Clear Register 368 * This register clears interrupt enable bits. 369 */ 370 union ody_mdc_int_ena_w1c { 371 uint64_t u; 372 struct ody_mdc_int_ena_w1c_s { 373 uint64_t ecc_error : 1; 374 uint64_t reserved_1_63 : 63; 375 } s; 376 /* struct ody_mdc_int_ena_w1c_s cn; */ 377 }; 378 typedef union ody_mdc_int_ena_w1c ody_mdc_int_ena_w1c_t; 379 380 #define ODY_MDC_INT_ENA_W1C ODY_MDC_INT_ENA_W1C_FUNC() 381 static inline uint64_t ODY_MDC_INT_ENA_W1C_FUNC(void) __attribute__ ((pure, always_inline)); 382 static inline uint64_t ODY_MDC_INT_ENA_W1C_FUNC(void) 383 { 384 return 0x87e010000058ll; 385 } 386 387 #define typedef_ODY_MDC_INT_ENA_W1C ody_mdc_int_ena_w1c_t 388 #define bustype_ODY_MDC_INT_ENA_W1C CSR_TYPE_RSL 389 #define basename_ODY_MDC_INT_ENA_W1C "MDC_INT_ENA_W1C" 390 #define device_bar_ODY_MDC_INT_ENA_W1C 0x0 /* PF_BAR0 */ 391 #define busnum_ODY_MDC_INT_ENA_W1C 0 392 #define arguments_ODY_MDC_INT_ENA_W1C -1, -1, -1, -1 393 394 /** 395 * Register (RSL) mdc_int_ena_w1s 396 * 397 * MDC Interrupt Enable Write-1-Set Register 398 * This register sets interrupt enable bits. 399 */ 400 union ody_mdc_int_ena_w1s { 401 uint64_t u; 402 struct ody_mdc_int_ena_w1s_s { 403 uint64_t ecc_error : 1; 404 uint64_t reserved_1_63 : 63; 405 } s; 406 /* struct ody_mdc_int_ena_w1s_s cn; */ 407 }; 408 typedef union ody_mdc_int_ena_w1s ody_mdc_int_ena_w1s_t; 409 410 #define ODY_MDC_INT_ENA_W1S ODY_MDC_INT_ENA_W1S_FUNC() 411 static inline uint64_t ODY_MDC_INT_ENA_W1S_FUNC(void) __attribute__ ((pure, always_inline)); 412 static inline uint64_t ODY_MDC_INT_ENA_W1S_FUNC(void) 413 { 414 return 0x87e010000060ll; 415 } 416 417 #define typedef_ODY_MDC_INT_ENA_W1S ody_mdc_int_ena_w1s_t 418 #define bustype_ODY_MDC_INT_ENA_W1S CSR_TYPE_RSL 419 #define basename_ODY_MDC_INT_ENA_W1S "MDC_INT_ENA_W1S" 420 #define device_bar_ODY_MDC_INT_ENA_W1S 0x0 /* PF_BAR0 */ 421 #define busnum_ODY_MDC_INT_ENA_W1S 0 422 #define arguments_ODY_MDC_INT_ENA_W1S -1, -1, -1, -1 423 424 /** 425 * Register (RSL) mdc_int_w1c 426 * 427 * MDC Interrupt Control Register 428 */ 429 union ody_mdc_int_w1c { 430 uint64_t u; 431 struct ody_mdc_int_w1c_s { 432 uint64_t ecc_error : 1; 433 uint64_t reserved_1_63 : 63; 434 } s; 435 /* struct ody_mdc_int_w1c_s cn; */ 436 }; 437 typedef union ody_mdc_int_w1c ody_mdc_int_w1c_t; 438 439 #define ODY_MDC_INT_W1C ODY_MDC_INT_W1C_FUNC() 440 static inline uint64_t ODY_MDC_INT_W1C_FUNC(void) __attribute__ ((pure, always_inline)); 441 static inline uint64_t ODY_MDC_INT_W1C_FUNC(void) 442 { 443 return 0x87e010000048ll; 444 } 445 446 #define typedef_ODY_MDC_INT_W1C ody_mdc_int_w1c_t 447 #define bustype_ODY_MDC_INT_W1C CSR_TYPE_RSL 448 #define basename_ODY_MDC_INT_W1C "MDC_INT_W1C" 449 #define device_bar_ODY_MDC_INT_W1C 0x0 /* PF_BAR0 */ 450 #define busnum_ODY_MDC_INT_W1C 0 451 #define arguments_ODY_MDC_INT_W1C -1, -1, -1, -1 452 453 /** 454 * Register (RSL) mdc_int_w1s 455 * 456 * MDC Interrupt Control Register 457 * This register sets interrupt bits. 458 */ 459 union ody_mdc_int_w1s { 460 uint64_t u; 461 struct ody_mdc_int_w1s_s { 462 uint64_t ecc_error : 1; 463 uint64_t reserved_1_63 : 63; 464 } s; 465 /* struct ody_mdc_int_w1s_s cn; */ 466 }; 467 typedef union ody_mdc_int_w1s ody_mdc_int_w1s_t; 468 469 #define ODY_MDC_INT_W1S ODY_MDC_INT_W1S_FUNC() 470 static inline uint64_t ODY_MDC_INT_W1S_FUNC(void) __attribute__ ((pure, always_inline)); 471 static inline uint64_t ODY_MDC_INT_W1S_FUNC(void) 472 { 473 return 0x87e010000050ll; 474 } 475 476 #define typedef_ODY_MDC_INT_W1S ody_mdc_int_w1s_t 477 #define bustype_ODY_MDC_INT_W1S CSR_TYPE_RSL 478 #define basename_ODY_MDC_INT_W1S "MDC_INT_W1S" 479 #define device_bar_ODY_MDC_INT_W1S 0x0 /* PF_BAR0 */ 480 #define busnum_ODY_MDC_INT_W1S 0 481 #define arguments_ODY_MDC_INT_W1S -1, -1, -1, -1 482 483 /** 484 * Register (RSL) mdc_pf_msix_pba# 485 * 486 * MDC MSI-X Pending Bit Array Registers 487 * This register is the MSI-X PBA table; the bit number is indexed by the MDC_INT_VEC_E 488 * enumeration. 489 */ 490 union ody_mdc_pf_msix_pbax { 491 uint64_t u; 492 struct ody_mdc_pf_msix_pbax_s { 493 uint64_t pend : 64; 494 } s; 495 /* struct ody_mdc_pf_msix_pbax_s cn; */ 496 }; 497 typedef union ody_mdc_pf_msix_pbax ody_mdc_pf_msix_pbax_t; 498 499 static inline uint64_t ODY_MDC_PF_MSIX_PBAX(uint64_t a) __attribute__ ((pure, always_inline)); 500 static inline uint64_t ODY_MDC_PF_MSIX_PBAX(uint64_t a) 501 { 502 if (a == 0) 503 return 0x87e0101f0000ll; 504 __ody_csr_fatal("MDC_PF_MSIX_PBAX", 1, a, 0, 0, 0, 0, 0); 505 } 506 507 #define typedef_ODY_MDC_PF_MSIX_PBAX(a) ody_mdc_pf_msix_pbax_t 508 #define bustype_ODY_MDC_PF_MSIX_PBAX(a) CSR_TYPE_RSL 509 #define basename_ODY_MDC_PF_MSIX_PBAX(a) "MDC_PF_MSIX_PBAX" 510 #define device_bar_ODY_MDC_PF_MSIX_PBAX(a) 0x4 /* PF_BAR4 */ 511 #define busnum_ODY_MDC_PF_MSIX_PBAX(a) (a) 512 #define arguments_ODY_MDC_PF_MSIX_PBAX(a) (a), -1, -1, -1 513 514 /** 515 * Register (RSL) mdc_pf_msix_vec#_addr 516 * 517 * MDC MSI-X Vector-Table Address Register 518 * This register is the MSI-X vector table, indexed by the MDC_INT_VEC_E enumeration. 519 */ 520 union ody_mdc_pf_msix_vecx_addr { 521 uint64_t u; 522 struct ody_mdc_pf_msix_vecx_addr_s { 523 uint64_t secvec : 1; 524 uint64_t reserved_1 : 1; 525 uint64_t addr : 51; 526 uint64_t reserved_53_63 : 11; 527 } s; 528 /* struct ody_mdc_pf_msix_vecx_addr_s cn; */ 529 }; 530 typedef union ody_mdc_pf_msix_vecx_addr ody_mdc_pf_msix_vecx_addr_t; 531 532 static inline uint64_t ODY_MDC_PF_MSIX_VECX_ADDR(uint64_t a) __attribute__ ((pure, always_inline)); 533 static inline uint64_t ODY_MDC_PF_MSIX_VECX_ADDR(uint64_t a) 534 { 535 if (a == 0) 536 return 0x87e010100000ll; 537 __ody_csr_fatal("MDC_PF_MSIX_VECX_ADDR", 1, a, 0, 0, 0, 0, 0); 538 } 539 540 #define typedef_ODY_MDC_PF_MSIX_VECX_ADDR(a) ody_mdc_pf_msix_vecx_addr_t 541 #define bustype_ODY_MDC_PF_MSIX_VECX_ADDR(a) CSR_TYPE_RSL 542 #define basename_ODY_MDC_PF_MSIX_VECX_ADDR(a) "MDC_PF_MSIX_VECX_ADDR" 543 #define device_bar_ODY_MDC_PF_MSIX_VECX_ADDR(a) 0x4 /* PF_BAR4 */ 544 #define busnum_ODY_MDC_PF_MSIX_VECX_ADDR(a) (a) 545 #define arguments_ODY_MDC_PF_MSIX_VECX_ADDR(a) (a), -1, -1, -1 546 547 /** 548 * Register (RSL) mdc_pf_msix_vec#_ctl 549 * 550 * MDC MSI-X Vector-Table Control and Data Register 551 * This register is the MSI-X vector table, indexed by the MDC_INT_VEC_E enumeration. 552 */ 553 union ody_mdc_pf_msix_vecx_ctl { 554 uint64_t u; 555 struct ody_mdc_pf_msix_vecx_ctl_s { 556 uint64_t data : 32; 557 uint64_t mask : 1; 558 uint64_t reserved_33_63 : 31; 559 } s; 560 /* struct ody_mdc_pf_msix_vecx_ctl_s cn; */ 561 }; 562 typedef union ody_mdc_pf_msix_vecx_ctl ody_mdc_pf_msix_vecx_ctl_t; 563 564 static inline uint64_t ODY_MDC_PF_MSIX_VECX_CTL(uint64_t a) __attribute__ ((pure, always_inline)); 565 static inline uint64_t ODY_MDC_PF_MSIX_VECX_CTL(uint64_t a) 566 { 567 if (a == 0) 568 return 0x87e010100008ll; 569 __ody_csr_fatal("MDC_PF_MSIX_VECX_CTL", 1, a, 0, 0, 0, 0, 0); 570 } 571 572 #define typedef_ODY_MDC_PF_MSIX_VECX_CTL(a) ody_mdc_pf_msix_vecx_ctl_t 573 #define bustype_ODY_MDC_PF_MSIX_VECX_CTL(a) CSR_TYPE_RSL 574 #define basename_ODY_MDC_PF_MSIX_VECX_CTL(a) "MDC_PF_MSIX_VECX_CTL" 575 #define device_bar_ODY_MDC_PF_MSIX_VECX_CTL(a) 0x4 /* PF_BAR4 */ 576 #define busnum_ODY_MDC_PF_MSIX_VECX_CTL(a) (a) 577 #define arguments_ODY_MDC_PF_MSIX_VECX_CTL(a) (a), -1, -1, -1 578 579 /** 580 * Register (RSL) mdc_ras_rom# 581 * 582 * MDC RAM ROM Access Register 583 */ 584 union ody_mdc_ras_romx { 585 uint64_t u; 586 struct ody_mdc_ras_romx_s { 587 uint64_t data : 64; 588 } s; 589 /* struct ody_mdc_ras_romx_s cn; */ 590 }; 591 typedef union ody_mdc_ras_romx ody_mdc_ras_romx_t; 592 593 static inline uint64_t ODY_MDC_RAS_ROMX(uint64_t a) __attribute__ ((pure, always_inline)); 594 static inline uint64_t ODY_MDC_RAS_ROMX(uint64_t a) 595 { 596 if (a <= 16383) 597 return 0x87e010010000ll + 8ll * ((a) & 0x3fff); 598 __ody_csr_fatal("MDC_RAS_ROMX", 1, a, 0, 0, 0, 0, 0); 599 } 600 601 #define typedef_ODY_MDC_RAS_ROMX(a) ody_mdc_ras_romx_t 602 #define bustype_ODY_MDC_RAS_ROMX(a) CSR_TYPE_RSL 603 #define basename_ODY_MDC_RAS_ROMX(a) "MDC_RAS_ROMX" 604 #define device_bar_ODY_MDC_RAS_ROMX(a) 0x0 /* PF_BAR0 */ 605 #define busnum_ODY_MDC_RAS_ROMX(a) (a) 606 #define arguments_ODY_MDC_RAS_ROMX(a) (a), -1, -1, -1 607 608 /** 609 * Register (RSL) mdc_timeouts 610 * 611 * MDC Protocol Timeout Register 612 */ 613 union ody_mdc_timeouts { 614 uint64_t u; 615 struct ody_mdc_timeouts_s { 616 uint64_t bist_completion : 28; 617 uint64_t reserved_28_31 : 4; 618 uint64_t bus_response : 16; 619 uint64_t reserved_48_63 : 16; 620 } s; 621 /* struct ody_mdc_timeouts_s cn; */ 622 }; 623 typedef union ody_mdc_timeouts ody_mdc_timeouts_t; 624 625 #define ODY_MDC_TIMEOUTS ODY_MDC_TIMEOUTS_FUNC() 626 static inline uint64_t ODY_MDC_TIMEOUTS_FUNC(void) __attribute__ ((pure, always_inline)); 627 static inline uint64_t ODY_MDC_TIMEOUTS_FUNC(void) 628 { 629 return 0x87e010000070ll; 630 } 631 632 #define typedef_ODY_MDC_TIMEOUTS ody_mdc_timeouts_t 633 #define bustype_ODY_MDC_TIMEOUTS CSR_TYPE_RSL 634 #define basename_ODY_MDC_TIMEOUTS "MDC_TIMEOUTS" 635 #define device_bar_ODY_MDC_TIMEOUTS 0x0 /* PF_BAR0 */ 636 #define busnum_ODY_MDC_TIMEOUTS 0 637 #define arguments_ODY_MDC_TIMEOUTS -1, -1, -1, -1 638 639 /** 640 * Register (RSL) mdc_win_cmd 641 * 642 * MDC Windowed Access Command Register 643 * Writing to this register initiates a MDC serial bus read or write request 644 * according to the [WE] field. MDC_WIN_DAT handles associated read 645 * or write data and it contains a status field MDC_WIN_DAT[PENDING] that 646 * indicates whether or not a request is in progress. Writes 647 * to MDC_WIN_CMD are ignored while MDC_WIN_DAT[PENDING] is asserted. 648 */ 649 union ody_mdc_win_cmd { 650 uint64_t u; 651 struct ody_mdc_win_cmd_s { 652 uint64_t csr_id : 8; 653 uint64_t we : 1; 654 uint64_t bc_nodes : 1; 655 uint64_t bc_chains : 1; 656 uint64_t reserved_11_15 : 5; 657 uint64_t node_id : 10; 658 uint64_t hub_id : 7; 659 uint64_t chain_id : 3; 660 uint64_t reserved_36_63 : 28; 661 } s; 662 /* struct ody_mdc_win_cmd_s cn; */ 663 }; 664 typedef union ody_mdc_win_cmd ody_mdc_win_cmd_t; 665 666 #define ODY_MDC_WIN_CMD ODY_MDC_WIN_CMD_FUNC() 667 static inline uint64_t ODY_MDC_WIN_CMD_FUNC(void) __attribute__ ((pure, always_inline)); 668 static inline uint64_t ODY_MDC_WIN_CMD_FUNC(void) 669 { 670 return 0x87e010000010ll; 671 } 672 673 #define typedef_ODY_MDC_WIN_CMD ody_mdc_win_cmd_t 674 #define bustype_ODY_MDC_WIN_CMD CSR_TYPE_RSL 675 #define basename_ODY_MDC_WIN_CMD "MDC_WIN_CMD" 676 #define device_bar_ODY_MDC_WIN_CMD 0x0 /* PF_BAR0 */ 677 #define busnum_ODY_MDC_WIN_CMD 0 678 #define arguments_ODY_MDC_WIN_CMD -1, -1, -1, -1 679 680 /** 681 * Register (RSL) mdc_win_dat 682 * 683 * MDC Windowed Access Read Data Register 684 */ 685 union ody_mdc_win_dat { 686 uint64_t u; 687 struct ody_mdc_win_dat_s { 688 uint64_t data : 32; 689 uint64_t read_valid : 1; 690 uint64_t pending : 1; 691 uint64_t timeout : 1; 692 uint64_t reserved_35_63 : 29; 693 } s; 694 /* struct ody_mdc_win_dat_s cn; */ 695 }; 696 typedef union ody_mdc_win_dat ody_mdc_win_dat_t; 697 698 #define ODY_MDC_WIN_DAT ODY_MDC_WIN_DAT_FUNC() 699 static inline uint64_t ODY_MDC_WIN_DAT_FUNC(void) __attribute__ ((pure, always_inline)); 700 static inline uint64_t ODY_MDC_WIN_DAT_FUNC(void) 701 { 702 return 0x87e010000018ll; 703 } 704 705 #define typedef_ODY_MDC_WIN_DAT ody_mdc_win_dat_t 706 #define bustype_ODY_MDC_WIN_DAT CSR_TYPE_RSL 707 #define basename_ODY_MDC_WIN_DAT "MDC_WIN_DAT" 708 #define device_bar_ODY_MDC_WIN_DAT 0x0 /* PF_BAR0 */ 709 #define busnum_ODY_MDC_WIN_DAT 0 710 #define arguments_ODY_MDC_WIN_DAT -1, -1, -1, -1 711 712 /** 713 * Register (RSL) mdc_win_tdr 714 * 715 * MDC Windowed Access TDR Register 716 * This allows MDN_BIST_CONFIG[BROADCAST_DISABLE] and 717 * MDN_BIST_CONFIG[MARCH_BROADCAST_DISABLE] in 32 nodes to be updated using a single 718 * write. 719 * Writing to this register initiates a MDC serial bus write request to 720 * MDN_ACTIVE_NODES of the nodes. 721 * Writes to MDC_WIN_CMD are ignored while MDC_WIN_DAT[PENDING] is asserted. 722 */ 723 union ody_mdc_win_tdr { 724 uint64_t u; 725 struct ody_mdc_win_tdr_s { 726 uint64_t node_map : 32; 727 uint64_t node_id_u : 5; 728 uint64_t hub_id : 7; 729 uint64_t chain_id : 3; 730 uint64_t march_broadcast_disable : 1; 731 uint64_t broadcast_disable : 1; 732 uint64_t reserved_49_63 : 15; 733 } s; 734 /* struct ody_mdc_win_tdr_s cn; */ 735 }; 736 typedef union ody_mdc_win_tdr ody_mdc_win_tdr_t; 737 738 #define ODY_MDC_WIN_TDR ODY_MDC_WIN_TDR_FUNC() 739 static inline uint64_t ODY_MDC_WIN_TDR_FUNC(void) __attribute__ ((pure, always_inline)); 740 static inline uint64_t ODY_MDC_WIN_TDR_FUNC(void) 741 { 742 return 0x87e010000020ll; 743 } 744 745 #define typedef_ODY_MDC_WIN_TDR ody_mdc_win_tdr_t 746 #define bustype_ODY_MDC_WIN_TDR CSR_TYPE_RSL 747 #define basename_ODY_MDC_WIN_TDR "MDC_WIN_TDR" 748 #define device_bar_ODY_MDC_WIN_TDR 0x0 /* PF_BAR0 */ 749 #define busnum_ODY_MDC_WIN_TDR 0 750 #define arguments_ODY_MDC_WIN_TDR -1, -1, -1, -1 751 752 #endif /* __ODY_CSRS_MDC_H__ */ 753