1 #ifndef __ODY_CSRS_IOBN_H__ 2 #define __ODY_CSRS_IOBN_H__ 3 /* This file is auto-generated. Do not edit */ 4 5 /***********************license start*********************************** 6 * Copyright (C) 2021-2026 Marvell. 7 * SPDX-License-Identifier: BSD-3-Clause 8 * https://spdx.org/licenses 9 ***********************license end**************************************/ 10 11 12 /** 13 * @file 14 * 15 * Configuration and status register (CSR) address and type definitions for 16 * IOBN. 17 * 18 * This file is auto generated. Do not edit. 19 * 20 */ 21 22 /** 23 * Enumeration iobn_bar_e 24 * 25 * IOBN Base Address Register Enumeration 26 * Enumerates the base address registers. 27 */ 28 #define ODY_IOBN_BAR_E_IOBNX_PF_BAR0(a) (0x87e120000000ll + 0x1000000ll * (a)) 29 #define ODY_IOBN_BAR_E_IOBNX_PF_BAR0_SIZE 0x100000ull 30 #define ODY_IOBN_BAR_E_IOBNX_PF_BAR4(a) (0x87e120f00000ll + 0x1000000ll * (a)) 31 #define ODY_IOBN_BAR_E_IOBNX_PF_BAR4_SIZE 0x100000ull 32 33 /** 34 * Enumeration iobn_inb_err_e 35 * 36 * IOBN In Bound Error Enumeration 37 * Enumerates the types of error detected on IOB inbound path. Errors are logged based on 38 * priority, where ::ABORT_ZERO_ERR has highest 39 * priority and ::ADDR_ERR has the lowest priority. See IOBN_INB_ERR_STATUS. 40 */ 41 #define ODY_IOBN_INB_ERR_E_ABORT_ZERO_ERR (1) 42 #define ODY_IOBN_INB_ERR_E_ADDR_ERR (2) 43 #define ODY_IOBN_INB_ERR_E_NONE (0) 44 #define ODY_IOBN_INB_ERR_E_RSVD (3) 45 46 /** 47 * Enumeration iobn_int_vec_e 48 * 49 * IOBN MSI-X Vector Enumeration 50 * Enumerates the MSI-X interrupt vectors. 51 */ 52 #define ODY_IOBN_INT_VEC_E_INTS (0) 53 54 /** 55 * Enumeration iobn_ncbi_ro_mod_e 56 * 57 * IOBN NCBI Relax Order Modification Enumeration 58 * Enumerates the controls for when CR's are allowed to pass PRs, see 59 * IOBN_ARBID()_CTL[CRPPR_ENA]. 60 */ 61 #define ODY_IOBN_NCBI_RO_MOD_E_BUS_CTL (0) 62 #define ODY_IOBN_NCBI_RO_MOD_E_OFF (2) 63 #define ODY_IOBN_NCBI_RO_MOD_E_ON (3) 64 #define ODY_IOBN_NCBI_RO_MOD_E_RSVD (1) 65 66 /** 67 * Enumeration iobn_outb_err_e 68 * 69 * IOBN Outbound Error Enumeration 70 * Enumerates the types of error detected on IOB outbound path. If the bit is set in 71 * IOBN_OUTB_ERR_STATUS corresponding to the enumeration value, that error occurred. 72 */ 73 #define ODY_IOBN_OUTB_ERR_E_ABORT_ZERO_ERR (1) 74 #define ODY_IOBN_OUTB_ERR_E_ADDR_ERR (2) 75 #define ODY_IOBN_OUTB_ERR_E_CLASS_A_FAULT (4) 76 #define ODY_IOBN_OUTB_ERR_E_NCBO_RDY_FAULT (0x10) 77 #define ODY_IOBN_OUTB_ERR_E_NONE (0) 78 #define ODY_IOBN_OUTB_ERR_E_PERMIT_FAULT (8) 79 80 /** 81 * Register (RSL) iobn#_cfg0 82 * 83 * IOBN General Configuration 0 Register 84 */ 85 union ody_iobnx_cfg0 { 86 uint64_t u; 87 struct ody_iobnx_cfg0_s { 88 uint64_t force_sclk_cond_clk_en : 1; 89 uint64_t reserved_1_3 : 3; 90 uint64_t dis_ncbo_cr_pois : 4; 91 uint64_t clken : 4; 92 uint64_t reserved_12_63 : 52; 93 } s; 94 /* struct ody_iobnx_cfg0_s cn; */ 95 }; 96 typedef union ody_iobnx_cfg0 ody_iobnx_cfg0_t; 97 98 static inline uint64_t ODY_IOBNX_CFG0(uint64_t a) __attribute__ ((pure, always_inline)); 99 static inline uint64_t ODY_IOBNX_CFG0(uint64_t a) 100 { 101 if (a <= 4) 102 return 0x87e120002000ll + 0x1000000ll * ((a) & 0x7); 103 __ody_csr_fatal("IOBNX_CFG0", 1, a, 0, 0, 0, 0, 0); 104 } 105 106 #define typedef_ODY_IOBNX_CFG0(a) ody_iobnx_cfg0_t 107 #define bustype_ODY_IOBNX_CFG0(a) CSR_TYPE_RSL 108 #define basename_ODY_IOBNX_CFG0(a) "IOBNX_CFG0" 109 #define device_bar_ODY_IOBNX_CFG0(a) 0x0 /* PF_BAR0 */ 110 #define busnum_ODY_IOBNX_CFG0(a) (a) 111 #define arguments_ODY_IOBNX_CFG0(a) (a), -1, -1, -1 112 113 /** 114 * Register (RSL) iobn#_cfg1 115 * 116 * IOBN General Configuration 1 Register 117 */ 118 union ody_iobnx_cfg1 { 119 uint64_t u; 120 struct ody_iobnx_cfg1_s { 121 uint64_t force_rclk_cond_clk_en : 1; 122 uint64_t reserved_1_2 : 2; 123 uint64_t tlb_sync_dis : 1; 124 uint64_t reserved_4_7 : 4; 125 uint64_t mem_rtry_psize : 4; 126 uint64_t reserved_12_15 : 4; 127 uint64_t smmu_rtry_psize : 4; 128 uint64_t eats_cache_dis : 1; 129 uint64_t utlb_clone_dis : 1; 130 uint64_t utlb_cam_evict_cnt : 6; 131 uint64_t reserved_28_63 : 36; 132 } s; 133 /* struct ody_iobnx_cfg1_s cn; */ 134 }; 135 typedef union ody_iobnx_cfg1 ody_iobnx_cfg1_t; 136 137 static inline uint64_t ODY_IOBNX_CFG1(uint64_t a) __attribute__ ((pure, always_inline)); 138 static inline uint64_t ODY_IOBNX_CFG1(uint64_t a) 139 { 140 if (a <= 4) 141 return 0x87e120082010ll + 0x1000000ll * ((a) & 0x7); 142 __ody_csr_fatal("IOBNX_CFG1", 1, a, 0, 0, 0, 0, 0); 143 } 144 145 #define typedef_ODY_IOBNX_CFG1(a) ody_iobnx_cfg1_t 146 #define bustype_ODY_IOBNX_CFG1(a) CSR_TYPE_RSL 147 #define basename_ODY_IOBNX_CFG1(a) "IOBNX_CFG1" 148 #define device_bar_ODY_IOBNX_CFG1(a) 0x0 /* PF_BAR0 */ 149 #define busnum_ODY_IOBNX_CFG1(a) (a) 150 #define arguments_ODY_IOBNX_CFG1(a) (a), -1, -1, -1 151 152 /** 153 * Register (RSL) iobn#_const 154 * 155 * IOBN Constant Registers 156 * This register returns discovery information. 157 */ 158 union ody_iobnx_const { 159 uint64_t u; 160 struct ody_iobnx_const_s { 161 uint64_t lsw_pres : 4; 162 uint64_t reserved_4_7 : 4; 163 uint64_t ncbs : 3; 164 uint64_t reserved_11_15 : 5; 165 uint64_t st_ncb_num : 4; 166 uint64_t reserved_20_63 : 44; 167 } s; 168 /* struct ody_iobnx_const_s cn; */ 169 }; 170 typedef union ody_iobnx_const ody_iobnx_const_t; 171 172 static inline uint64_t ODY_IOBNX_CONST(uint64_t a) __attribute__ ((pure, always_inline)); 173 static inline uint64_t ODY_IOBNX_CONST(uint64_t a) 174 { 175 if (a <= 4) 176 return 0x87e120000000ll + 0x1000000ll * ((a) & 0x7); 177 __ody_csr_fatal("IOBNX_CONST", 1, a, 0, 0, 0, 0, 0); 178 } 179 180 #define typedef_ODY_IOBNX_CONST(a) ody_iobnx_const_t 181 #define bustype_ODY_IOBNX_CONST(a) CSR_TYPE_RSL 182 #define basename_ODY_IOBNX_CONST(a) "IOBNX_CONST" 183 #define device_bar_ODY_IOBNX_CONST(a) 0x0 /* PF_BAR0 */ 184 #define busnum_ODY_IOBNX_CONST(a) (a) 185 #define arguments_ODY_IOBNX_CONST(a) (a), -1, -1, -1 186 187 /** 188 * Register (RSL) iobn#_dom#_bus#_streams 189 * 190 * IOBN Domain Bus Permit Registers 191 * This register sets the permissions for a NCBI transaction (which are DMA 192 * transactions or MSI-X writes), for requests for NCB device virtual-functions 193 * and bridges. 194 * 195 * Index {b} corresponds to the stream's domain (stream_id\<21:16\>). 196 * 197 * Index {c} corresponds to the stream's bus number (stream_id\<15:8\>). 198 * 199 * For each combination of index {b} and {c}, each index {a} (the IOB number) must be 200 * programmed to the same value. 201 * 202 * Streams which hit index {c}=0x0 are also affected by IOBN_DOM()_DEV()_STREAMS. 203 * Streams which hit index {b}=PCC_DEV_CON_E::MRML\<21:16\>, 204 * {c}=PCC_DEV_CON_E::MRML\<15:8\> are also affected by IOBN_RSL()_STREAMS. 205 * Both of those alternative registers provide better granularity, so those indices 206 * into this register should be left permissive (value of 0x0). 207 */ 208 union ody_iobnx_domx_busx_streams { 209 uint64_t u; 210 struct ody_iobnx_domx_busx_streams_s { 211 uint64_t phys_nsec : 1; 212 uint64_t strm_nsec : 1; 213 uint64_t reserved_2_63 : 62; 214 } s; 215 /* struct ody_iobnx_domx_busx_streams_s cn; */ 216 }; 217 typedef union ody_iobnx_domx_busx_streams ody_iobnx_domx_busx_streams_t; 218 219 static inline uint64_t ODY_IOBNX_DOMX_BUSX_STREAMS(uint64_t a, uint64_t b, uint64_t c) __attribute__ ((pure, always_inline)); 220 static inline uint64_t ODY_IOBNX_DOMX_BUSX_STREAMS(uint64_t a, uint64_t b, uint64_t c) 221 { 222 if ((a <= 4) && (b <= 18) && (c <= 255)) 223 return 0x87e120040000ll + 0x1000000ll * ((a) & 0x7) + 0x800ll * ((b) & 0x1f) + 8ll * ((c) & 0xff); 224 __ody_csr_fatal("IOBNX_DOMX_BUSX_STREAMS", 3, a, b, c, 0, 0, 0); 225 } 226 227 #define typedef_ODY_IOBNX_DOMX_BUSX_STREAMS(a, b, c) ody_iobnx_domx_busx_streams_t 228 #define bustype_ODY_IOBNX_DOMX_BUSX_STREAMS(a, b, c) CSR_TYPE_RSL 229 #define basename_ODY_IOBNX_DOMX_BUSX_STREAMS(a, b, c) "IOBNX_DOMX_BUSX_STREAMS" 230 #define device_bar_ODY_IOBNX_DOMX_BUSX_STREAMS(a, b, c) 0x0 /* PF_BAR0 */ 231 #define busnum_ODY_IOBNX_DOMX_BUSX_STREAMS(a, b, c) (a) 232 #define arguments_ODY_IOBNX_DOMX_BUSX_STREAMS(a, b, c) (a), (b), (c), -1 233 234 /** 235 * Register (RSL) iobn#_dom#_dev#_streams 236 * 237 * IOBN Device Bus Permit Registers 238 * This register sets the permissions for a NCBI transaction (which are DMA 239 * transactions or MSI-X writes), for requests for NCB device physical-functions, 240 * i.e. those where: 241 * 242 * _ stream_id\<15:8\> = 0x0. 243 * 244 * Index {a} corresponds to the stream's domain number (stream_id\<21:16\>). 245 * 246 * Index {b} corresponds to the non-ARI ECAM device number (stream_id\<7:3\>). 247 * 248 * For each combination of index {b} and {c}, each index {a} (the IOB number) must be 249 * programmed to the same value. 250 */ 251 union ody_iobnx_domx_devx_streams { 252 uint64_t u; 253 struct ody_iobnx_domx_devx_streams_s { 254 uint64_t phys_nsec : 1; 255 uint64_t strm_nsec : 1; 256 uint64_t reserved_2_63 : 62; 257 } s; 258 /* struct ody_iobnx_domx_devx_streams_s cn; */ 259 }; 260 typedef union ody_iobnx_domx_devx_streams ody_iobnx_domx_devx_streams_t; 261 262 static inline uint64_t ODY_IOBNX_DOMX_DEVX_STREAMS(uint64_t a, uint64_t b, uint64_t c) __attribute__ ((pure, always_inline)); 263 static inline uint64_t ODY_IOBNX_DOMX_DEVX_STREAMS(uint64_t a, uint64_t b, uint64_t c) 264 { 265 if ((a <= 4) && (b <= 18) && (c <= 31)) 266 return 0x87e120010000ll + 0x1000000ll * ((a) & 0x7) + 0x100ll * ((b) & 0x1f) + 8ll * ((c) & 0x1f); 267 __ody_csr_fatal("IOBNX_DOMX_DEVX_STREAMS", 3, a, b, c, 0, 0, 0); 268 } 269 270 #define typedef_ODY_IOBNX_DOMX_DEVX_STREAMS(a, b, c) ody_iobnx_domx_devx_streams_t 271 #define bustype_ODY_IOBNX_DOMX_DEVX_STREAMS(a, b, c) CSR_TYPE_RSL 272 #define basename_ODY_IOBNX_DOMX_DEVX_STREAMS(a, b, c) "IOBNX_DOMX_DEVX_STREAMS" 273 #define device_bar_ODY_IOBNX_DOMX_DEVX_STREAMS(a, b, c) 0x0 /* PF_BAR0 */ 274 #define busnum_ODY_IOBNX_DOMX_DEVX_STREAMS(a, b, c) (a) 275 #define arguments_ODY_IOBNX_DOMX_DEVX_STREAMS(a, b, c) (a), (b), (c), -1 276 277 /** 278 * Register (RSL) iobn#_ecam_dom#_dev#_permit 279 * 280 * IOBN ECAM Domain Device Permit Registers 281 * Program identically to ECAM_DOM()_DEV()_PERMIT. 282 * 283 * This register sets the permissions for a ECAM access (derived from request address) to NCBO 284 * for a request from an IO device. 285 * Index {a} corresponds to the domain, addr[32:28]. 286 * Index {b} corresponds to the dev, addr[19:15]. 287 * If ECAM access resuts in a failure a response will be returned and where required data 288 * with a value of all 1's and FAULT == 0 (MESH, CHI_RESPERR_OK). 289 * 290 * If IOBN_CONST.UNIMP_REG is set this register is not implemented. 291 * Reads will respond with zero and writes will be ignored. 292 */ 293 union ody_iobnx_ecam_domx_devx_permit { 294 uint64_t u; 295 struct ody_iobnx_ecam_domx_devx_permit_s { 296 uint64_t sec_dis : 1; 297 uint64_t nsec_dis : 1; 298 uint64_t xcp0_dis : 1; 299 uint64_t xcp1_dis : 1; 300 uint64_t xcp2_dis : 1; 301 uint64_t reserved_5_6 : 2; 302 uint64_t kill : 1; 303 uint64_t lock : 1; 304 uint64_t reserved_9_63 : 55; 305 } s; 306 /* struct ody_iobnx_ecam_domx_devx_permit_s cn; */ 307 }; 308 typedef union ody_iobnx_ecam_domx_devx_permit ody_iobnx_ecam_domx_devx_permit_t; 309 310 static inline uint64_t ODY_IOBNX_ECAM_DOMX_DEVX_PERMIT(uint64_t a, uint64_t b, uint64_t c) __attribute__ ((pure, always_inline)); 311 static inline uint64_t ODY_IOBNX_ECAM_DOMX_DEVX_PERMIT(uint64_t a, uint64_t b, uint64_t c) 312 { 313 if ((a <= 4) && (b <= 18) && (c <= 31)) 314 return 0x87e1200e0000ll + 0x1000000ll * ((a) & 0x7) + 0x800ll * ((b) & 0x1f) + 8ll * ((c) & 0x1f); 315 __ody_csr_fatal("IOBNX_ECAM_DOMX_DEVX_PERMIT", 3, a, b, c, 0, 0, 0); 316 } 317 318 #define typedef_ODY_IOBNX_ECAM_DOMX_DEVX_PERMIT(a, b, c) ody_iobnx_ecam_domx_devx_permit_t 319 #define bustype_ODY_IOBNX_ECAM_DOMX_DEVX_PERMIT(a, b, c) CSR_TYPE_RSL 320 #define basename_ODY_IOBNX_ECAM_DOMX_DEVX_PERMIT(a, b, c) "IOBNX_ECAM_DOMX_DEVX_PERMIT" 321 #define device_bar_ODY_IOBNX_ECAM_DOMX_DEVX_PERMIT(a, b, c) 0x0 /* PF_BAR0 */ 322 #define busnum_ODY_IOBNX_ECAM_DOMX_DEVX_PERMIT(a, b, c) (a) 323 #define arguments_ODY_IOBNX_ECAM_DOMX_DEVX_PERMIT(a, b, c) (a), (b), (c), -1 324 325 /** 326 * Register (RSL) iobn#_err_ena 327 * 328 * IOBN Error Enable Register 329 * Controls what errors are logged into IOBN_INB_ERR_STATUS and IOBN_OUTB_ERR_STATUS registers. 330 */ 331 union ody_iobnx_err_ena { 332 uint64_t u; 333 struct ody_iobnx_err_ena_s { 334 uint64_t inb_err_enb : 2; 335 uint64_t reserved_2_7 : 6; 336 uint64_t outb_err_enb : 5; 337 uint64_t reserved_13_63 : 51; 338 } s; 339 /* struct ody_iobnx_err_ena_s cn; */ 340 }; 341 typedef union ody_iobnx_err_ena ody_iobnx_err_ena_t; 342 343 static inline uint64_t ODY_IOBNX_ERR_ENA(uint64_t a) __attribute__ ((pure, always_inline)); 344 static inline uint64_t ODY_IOBNX_ERR_ENA(uint64_t a) 345 { 346 if (a <= 4) 347 return 0x87e120083080ll + 0x1000000ll * ((a) & 0x7); 348 __ody_csr_fatal("IOBNX_ERR_ENA", 1, a, 0, 0, 0, 0, 0); 349 } 350 351 #define typedef_ODY_IOBNX_ERR_ENA(a) ody_iobnx_err_ena_t 352 #define bustype_ODY_IOBNX_ERR_ENA(a) CSR_TYPE_RSL 353 #define basename_ODY_IOBNX_ERR_ENA(a) "IOBNX_ERR_ENA" 354 #define device_bar_ODY_IOBNX_ERR_ENA(a) 0x0 /* PF_BAR0 */ 355 #define busnum_ODY_IOBNX_ERR_ENA(a) (a) 356 #define arguments_ODY_IOBNX_ERR_ENA(a) (a), -1, -1, -1 357 358 /** 359 * Register (RSL) iobn#_inb_err_status 360 * 361 * IOBN In Bound Error Status Register 362 * Inbound error status register logs first error detected on inbound control path. 363 */ 364 union ody_iobnx_inb_err_status { 365 uint64_t u; 366 struct ody_iobnx_inb_err_status_s { 367 uint64_t err_type : 2; 368 uint64_t reserved_2_11 : 10; 369 uint64_t address : 40; 370 uint64_t reserved_52_55 : 4; 371 uint64_t arbid : 4; 372 uint64_t reserved_60_63 : 4; 373 } s; 374 /* struct ody_iobnx_inb_err_status_s cn; */ 375 }; 376 typedef union ody_iobnx_inb_err_status ody_iobnx_inb_err_status_t; 377 378 static inline uint64_t ODY_IOBNX_INB_ERR_STATUS(uint64_t a) __attribute__ ((pure, always_inline)); 379 static inline uint64_t ODY_IOBNX_INB_ERR_STATUS(uint64_t a) 380 { 381 if (a <= 4) 382 return 0x87e120083088ll + 0x1000000ll * ((a) & 0x7); 383 __ody_csr_fatal("IOBNX_INB_ERR_STATUS", 1, a, 0, 0, 0, 0, 0); 384 } 385 386 #define typedef_ODY_IOBNX_INB_ERR_STATUS(a) ody_iobnx_inb_err_status_t 387 #define bustype_ODY_IOBNX_INB_ERR_STATUS(a) CSR_TYPE_RSL 388 #define basename_ODY_IOBNX_INB_ERR_STATUS(a) "IOBNX_INB_ERR_STATUS" 389 #define device_bar_ODY_IOBNX_INB_ERR_STATUS(a) 0x0 /* PF_BAR0 */ 390 #define busnum_ODY_IOBNX_INB_ERR_STATUS(a) (a) 391 #define arguments_ODY_IOBNX_INB_ERR_STATUS(a) (a), -1, -1, -1 392 393 /** 394 * Register (RSL) iobn#_inb_mesh_throttle 395 * 396 * IOBN Inbound Mesh Throttle Register 397 * Controls the rate of TX_REQ sent to the MESH. 398 * Rate is dynamically controlled by ARM CHI CBUSY messages. Absolute min rate is 1 399 * every 16 cycles. Max rate is 16 every 16 cycles. 400 * Decrease TX_REQ rate if more than THRESH of the last WINDOW reponses contain CBUSY==3. 401 * Increase TX_REQ rate if more than THRESH of the last WINDOW reponses contain CBUSY \<2. 402 */ 403 union ody_iobnx_inb_mesh_throttle { 404 uint64_t u; 405 struct ody_iobnx_inb_mesh_throttle_s { 406 uint64_t ena : 1; 407 uint64_t reserved_1_3 : 3; 408 uint64_t incr : 2; 409 uint64_t decr : 2; 410 uint64_t thresh : 2; 411 uint64_t window : 2; 412 uint64_t min_rate : 4; 413 uint64_t max_rate : 4; 414 uint64_t timeout : 4; 415 uint64_t reserved_24_63 : 40; 416 } s; 417 /* struct ody_iobnx_inb_mesh_throttle_s cn; */ 418 }; 419 typedef union ody_iobnx_inb_mesh_throttle ody_iobnx_inb_mesh_throttle_t; 420 421 static inline uint64_t ODY_IOBNX_INB_MESH_THROTTLE(uint64_t a) __attribute__ ((pure, always_inline)); 422 static inline uint64_t ODY_IOBNX_INB_MESH_THROTTLE(uint64_t a) 423 { 424 if (a <= 4) 425 return 0x87e120082200ll + 0x1000000ll * ((a) & 0x7); 426 __ody_csr_fatal("IOBNX_INB_MESH_THROTTLE", 1, a, 0, 0, 0, 0, 0); 427 } 428 429 #define typedef_ODY_IOBNX_INB_MESH_THROTTLE(a) ody_iobnx_inb_mesh_throttle_t 430 #define bustype_ODY_IOBNX_INB_MESH_THROTTLE(a) CSR_TYPE_RSL 431 #define basename_ODY_IOBNX_INB_MESH_THROTTLE(a) "IOBNX_INB_MESH_THROTTLE" 432 #define device_bar_ODY_IOBNX_INB_MESH_THROTTLE(a) 0x0 /* PF_BAR0 */ 433 #define busnum_ODY_IOBNX_INB_MESH_THROTTLE(a) (a) 434 #define arguments_ODY_IOBNX_INB_MESH_THROTTLE(a) (a), -1, -1, -1 435 436 /** 437 * Register (RSL) iobn#_int_ena_w1c 438 * 439 * IOBN Interrupt Enable Clear Register 440 * This register clears interrupt enable bits. 441 */ 442 union ody_iobnx_int_ena_w1c { 443 uint64_t u; 444 struct ody_iobnx_int_ena_w1c_s { 445 uint64_t ncbo_to : 4; 446 uint64_t ncbo_ncb_psn : 4; 447 uint64_t ncbi_unexp_cr : 4; 448 uint64_t ncbo_pois_cr : 4; 449 uint64_t ncbo_flt_cr : 4; 450 uint64_t msh_dat_dbe : 1; 451 uint64_t msh_dat_sbe : 1; 452 uint64_t reserved_22_23 : 2; 453 uint64_t msh_dat_chk : 1; 454 uint64_t msh_req_chk : 1; 455 uint64_t msh_snp_chk : 1; 456 uint64_t msh_rsp_chk : 1; 457 uint64_t msh_dat1_chk : 1; 458 uint64_t msh_rsp1_chk : 1; 459 uint64_t msh_smmu_psn : 1; 460 uint64_t msh_dato_dbe : 1; 461 uint64_t msh_dato_sbe : 1; 462 uint64_t reserved_33_63 : 31; 463 } s; 464 /* struct ody_iobnx_int_ena_w1c_s cn; */ 465 }; 466 typedef union ody_iobnx_int_ena_w1c ody_iobnx_int_ena_w1c_t; 467 468 static inline uint64_t ODY_IOBNX_INT_ENA_W1C(uint64_t a) __attribute__ ((pure, always_inline)); 469 static inline uint64_t ODY_IOBNX_INT_ENA_W1C(uint64_t a) 470 { 471 if (a <= 4) 472 return 0x87e120088000ll + 0x1000000ll * ((a) & 0x7); 473 __ody_csr_fatal("IOBNX_INT_ENA_W1C", 1, a, 0, 0, 0, 0, 0); 474 } 475 476 #define typedef_ODY_IOBNX_INT_ENA_W1C(a) ody_iobnx_int_ena_w1c_t 477 #define bustype_ODY_IOBNX_INT_ENA_W1C(a) CSR_TYPE_RSL 478 #define basename_ODY_IOBNX_INT_ENA_W1C(a) "IOBNX_INT_ENA_W1C" 479 #define device_bar_ODY_IOBNX_INT_ENA_W1C(a) 0x0 /* PF_BAR0 */ 480 #define busnum_ODY_IOBNX_INT_ENA_W1C(a) (a) 481 #define arguments_ODY_IOBNX_INT_ENA_W1C(a) (a), -1, -1, -1 482 483 /** 484 * Register (RSL) iobn#_int_ena_w1s 485 * 486 * IOBN Interrupt Enable Set Register 487 * This register sets interrupt enable bits. 488 */ 489 union ody_iobnx_int_ena_w1s { 490 uint64_t u; 491 struct ody_iobnx_int_ena_w1s_s { 492 uint64_t ncbo_to : 4; 493 uint64_t ncbo_ncb_psn : 4; 494 uint64_t ncbi_unexp_cr : 4; 495 uint64_t ncbo_pois_cr : 4; 496 uint64_t ncbo_flt_cr : 4; 497 uint64_t msh_dat_dbe : 1; 498 uint64_t msh_dat_sbe : 1; 499 uint64_t reserved_22_23 : 2; 500 uint64_t msh_dat_chk : 1; 501 uint64_t msh_req_chk : 1; 502 uint64_t msh_snp_chk : 1; 503 uint64_t msh_rsp_chk : 1; 504 uint64_t msh_dat1_chk : 1; 505 uint64_t msh_rsp1_chk : 1; 506 uint64_t msh_smmu_psn : 1; 507 uint64_t msh_dato_dbe : 1; 508 uint64_t msh_dato_sbe : 1; 509 uint64_t reserved_33_63 : 31; 510 } s; 511 /* struct ody_iobnx_int_ena_w1s_s cn; */ 512 }; 513 typedef union ody_iobnx_int_ena_w1s ody_iobnx_int_ena_w1s_t; 514 515 static inline uint64_t ODY_IOBNX_INT_ENA_W1S(uint64_t a) __attribute__ ((pure, always_inline)); 516 static inline uint64_t ODY_IOBNX_INT_ENA_W1S(uint64_t a) 517 { 518 if (a <= 4) 519 return 0x87e120089000ll + 0x1000000ll * ((a) & 0x7); 520 __ody_csr_fatal("IOBNX_INT_ENA_W1S", 1, a, 0, 0, 0, 0, 0); 521 } 522 523 #define typedef_ODY_IOBNX_INT_ENA_W1S(a) ody_iobnx_int_ena_w1s_t 524 #define bustype_ODY_IOBNX_INT_ENA_W1S(a) CSR_TYPE_RSL 525 #define basename_ODY_IOBNX_INT_ENA_W1S(a) "IOBNX_INT_ENA_W1S" 526 #define device_bar_ODY_IOBNX_INT_ENA_W1S(a) 0x0 /* PF_BAR0 */ 527 #define busnum_ODY_IOBNX_INT_ENA_W1S(a) (a) 528 #define arguments_ODY_IOBNX_INT_ENA_W1S(a) (a), -1, -1, -1 529 530 /** 531 * Register (RSL) iobn#_int_sum 532 * 533 * IOBN Interrupt Summary Register 534 * This register contains the different interrupt-summary bits of the IOBN. 535 * Bits in this register are RAS related events, that are expected to be routed to the SCP. 536 */ 537 union ody_iobnx_int_sum { 538 uint64_t u; 539 struct ody_iobnx_int_sum_s { 540 uint64_t ncbo_to : 4; 541 uint64_t ncbo_ncb_psn : 4; 542 uint64_t ncbi_unexp_cr : 4; 543 uint64_t ncbo_pois_cr : 4; 544 uint64_t ncbo_flt_cr : 4; 545 uint64_t msh_dat_dbe : 1; 546 uint64_t msh_dat_sbe : 1; 547 uint64_t reserved_22_23 : 2; 548 uint64_t msh_dat_chk : 1; 549 uint64_t msh_req_chk : 1; 550 uint64_t msh_snp_chk : 1; 551 uint64_t msh_rsp_chk : 1; 552 uint64_t msh_dat1_chk : 1; 553 uint64_t msh_rsp1_chk : 1; 554 uint64_t msh_smmu_psn : 1; 555 uint64_t msh_dato_dbe : 1; 556 uint64_t msh_dato_sbe : 1; 557 uint64_t reserved_33_63 : 31; 558 } s; 559 /* struct ody_iobnx_int_sum_s cn; */ 560 }; 561 typedef union ody_iobnx_int_sum ody_iobnx_int_sum_t; 562 563 static inline uint64_t ODY_IOBNX_INT_SUM(uint64_t a) __attribute__ ((pure, always_inline)); 564 static inline uint64_t ODY_IOBNX_INT_SUM(uint64_t a) 565 { 566 if (a <= 4) 567 return 0x87e120086000ll + 0x1000000ll * ((a) & 0x7); 568 __ody_csr_fatal("IOBNX_INT_SUM", 1, a, 0, 0, 0, 0, 0); 569 } 570 571 #define typedef_ODY_IOBNX_INT_SUM(a) ody_iobnx_int_sum_t 572 #define bustype_ODY_IOBNX_INT_SUM(a) CSR_TYPE_RSL 573 #define basename_ODY_IOBNX_INT_SUM(a) "IOBNX_INT_SUM" 574 #define device_bar_ODY_IOBNX_INT_SUM(a) 0x0 /* PF_BAR0 */ 575 #define busnum_ODY_IOBNX_INT_SUM(a) (a) 576 #define arguments_ODY_IOBNX_INT_SUM(a) (a), -1, -1, -1 577 578 /** 579 * Register (RSL) iobn#_int_sum_w1s 580 * 581 * IOBN Interrupt Set Register 582 * This register sets interrupt bits. 583 */ 584 union ody_iobnx_int_sum_w1s { 585 uint64_t u; 586 struct ody_iobnx_int_sum_w1s_s { 587 uint64_t ncbo_to : 4; 588 uint64_t ncbo_ncb_psn : 4; 589 uint64_t ncbi_unexp_cr : 4; 590 uint64_t ncbo_pois_cr : 4; 591 uint64_t ncbo_flt_cr : 4; 592 uint64_t msh_dat_dbe : 1; 593 uint64_t msh_dat_sbe : 1; 594 uint64_t reserved_22_23 : 2; 595 uint64_t msh_dat_chk : 1; 596 uint64_t msh_req_chk : 1; 597 uint64_t msh_snp_chk : 1; 598 uint64_t msh_rsp_chk : 1; 599 uint64_t msh_dat1_chk : 1; 600 uint64_t msh_rsp1_chk : 1; 601 uint64_t msh_smmu_psn : 1; 602 uint64_t msh_dato_dbe : 1; 603 uint64_t msh_dato_sbe : 1; 604 uint64_t reserved_33_63 : 31; 605 } s; 606 /* struct ody_iobnx_int_sum_w1s_s cn; */ 607 }; 608 typedef union ody_iobnx_int_sum_w1s ody_iobnx_int_sum_w1s_t; 609 610 static inline uint64_t ODY_IOBNX_INT_SUM_W1S(uint64_t a) __attribute__ ((pure, always_inline)); 611 static inline uint64_t ODY_IOBNX_INT_SUM_W1S(uint64_t a) 612 { 613 if (a <= 4) 614 return 0x87e120087000ll + 0x1000000ll * ((a) & 0x7); 615 __ody_csr_fatal("IOBNX_INT_SUM_W1S", 1, a, 0, 0, 0, 0, 0); 616 } 617 618 #define typedef_ODY_IOBNX_INT_SUM_W1S(a) ody_iobnx_int_sum_w1s_t 619 #define bustype_ODY_IOBNX_INT_SUM_W1S(a) CSR_TYPE_RSL 620 #define basename_ODY_IOBNX_INT_SUM_W1S(a) "IOBNX_INT_SUM_W1S" 621 #define device_bar_ODY_IOBNX_INT_SUM_W1S(a) 0x0 /* PF_BAR0 */ 622 #define busnum_ODY_IOBNX_INT_SUM_W1S(a) (a) 623 #define arguments_ODY_IOBNX_INT_SUM_W1S(a) (a), -1, -1, -1 624 625 /** 626 * Register (RSL) iobn#_lsw_cfg 627 * 628 * IOBN LSW General Configuration Register 629 */ 630 union ody_iobnx_lsw_cfg { 631 uint64_t u; 632 struct ody_iobnx_lsw_cfg_s { 633 uint64_t lsw0_force_cond_clk_en : 1; 634 uint64_t lsw0_rsvd : 7; 635 uint64_t lsw1_force_cond_clk_en : 1; 636 uint64_t lsw1_rsvd : 7; 637 uint64_t reserved_16_63 : 48; 638 } s; 639 /* struct ody_iobnx_lsw_cfg_s cn; */ 640 }; 641 typedef union ody_iobnx_lsw_cfg ody_iobnx_lsw_cfg_t; 642 643 static inline uint64_t ODY_IOBNX_LSW_CFG(uint64_t a) __attribute__ ((pure, always_inline)); 644 static inline uint64_t ODY_IOBNX_LSW_CFG(uint64_t a) 645 { 646 if (a <= 4) 647 return 0x87e120002100ll + 0x1000000ll * ((a) & 0x7); 648 __ody_csr_fatal("IOBNX_LSW_CFG", 1, a, 0, 0, 0, 0, 0); 649 } 650 651 #define typedef_ODY_IOBNX_LSW_CFG(a) ody_iobnx_lsw_cfg_t 652 #define bustype_ODY_IOBNX_LSW_CFG(a) CSR_TYPE_RSL 653 #define basename_ODY_IOBNX_LSW_CFG(a) "IOBNX_LSW_CFG" 654 #define device_bar_ODY_IOBNX_LSW_CFG(a) 0x0 /* PF_BAR0 */ 655 #define busnum_ODY_IOBNX_LSW_CFG(a) (a) 656 #define arguments_ODY_IOBNX_LSW_CFG(a) (a), -1, -1, -1 657 658 /** 659 * Register (RSL) iobn#_msix_pba# 660 * 661 * IOBN MSI-X Pending Bit Array Registers 662 * This register is the MSI-X PBA table; the bit number is indexed by the IOBN_INT_VEC_E enumeration. 663 */ 664 union ody_iobnx_msix_pbax { 665 uint64_t u; 666 struct ody_iobnx_msix_pbax_s { 667 uint64_t pend : 64; 668 } s; 669 /* struct ody_iobnx_msix_pbax_s cn; */ 670 }; 671 typedef union ody_iobnx_msix_pbax ody_iobnx_msix_pbax_t; 672 673 static inline uint64_t ODY_IOBNX_MSIX_PBAX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 674 static inline uint64_t ODY_IOBNX_MSIX_PBAX(uint64_t a, uint64_t b) 675 { 676 if ((a <= 4) && (b == 0)) 677 return 0x87e120ff0000ll + 0x1000000ll * ((a) & 0x7); 678 __ody_csr_fatal("IOBNX_MSIX_PBAX", 2, a, b, 0, 0, 0, 0); 679 } 680 681 #define typedef_ODY_IOBNX_MSIX_PBAX(a, b) ody_iobnx_msix_pbax_t 682 #define bustype_ODY_IOBNX_MSIX_PBAX(a, b) CSR_TYPE_RSL 683 #define basename_ODY_IOBNX_MSIX_PBAX(a, b) "IOBNX_MSIX_PBAX" 684 #define device_bar_ODY_IOBNX_MSIX_PBAX(a, b) 0x4 /* PF_BAR4 */ 685 #define busnum_ODY_IOBNX_MSIX_PBAX(a, b) (a) 686 #define arguments_ODY_IOBNX_MSIX_PBAX(a, b) (a), (b), -1, -1 687 688 /** 689 * Register (RSL) iobn#_msix_vec#_addr 690 * 691 * IOBN MSI-X Vector-Table Address Register 692 * This register is the MSI-X vector table, indexed by the IOBN_INT_VEC_E enumeration. 693 */ 694 union ody_iobnx_msix_vecx_addr { 695 uint64_t u; 696 struct ody_iobnx_msix_vecx_addr_s { 697 uint64_t secvec : 1; 698 uint64_t reserved_1 : 1; 699 uint64_t addr : 51; 700 uint64_t reserved_53_63 : 11; 701 } s; 702 /* struct ody_iobnx_msix_vecx_addr_s cn; */ 703 }; 704 typedef union ody_iobnx_msix_vecx_addr ody_iobnx_msix_vecx_addr_t; 705 706 static inline uint64_t ODY_IOBNX_MSIX_VECX_ADDR(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 707 static inline uint64_t ODY_IOBNX_MSIX_VECX_ADDR(uint64_t a, uint64_t b) 708 { 709 if ((a <= 4) && (b == 0)) 710 return 0x87e120f00000ll + 0x1000000ll * ((a) & 0x7); 711 __ody_csr_fatal("IOBNX_MSIX_VECX_ADDR", 2, a, b, 0, 0, 0, 0); 712 } 713 714 #define typedef_ODY_IOBNX_MSIX_VECX_ADDR(a, b) ody_iobnx_msix_vecx_addr_t 715 #define bustype_ODY_IOBNX_MSIX_VECX_ADDR(a, b) CSR_TYPE_RSL 716 #define basename_ODY_IOBNX_MSIX_VECX_ADDR(a, b) "IOBNX_MSIX_VECX_ADDR" 717 #define device_bar_ODY_IOBNX_MSIX_VECX_ADDR(a, b) 0x4 /* PF_BAR4 */ 718 #define busnum_ODY_IOBNX_MSIX_VECX_ADDR(a, b) (a) 719 #define arguments_ODY_IOBNX_MSIX_VECX_ADDR(a, b) (a), (b), -1, -1 720 721 /** 722 * Register (RSL) iobn#_msix_vec#_ctl 723 * 724 * IOBN MSI-X Vector-Table Control and Data Register 725 * This register is the MSI-X vector table, indexed by the IOBN_INT_VEC_E enumeration. 726 */ 727 union ody_iobnx_msix_vecx_ctl { 728 uint64_t u; 729 struct ody_iobnx_msix_vecx_ctl_s { 730 uint64_t data : 32; 731 uint64_t mask : 1; 732 uint64_t reserved_33_63 : 31; 733 } s; 734 /* struct ody_iobnx_msix_vecx_ctl_s cn; */ 735 }; 736 typedef union ody_iobnx_msix_vecx_ctl ody_iobnx_msix_vecx_ctl_t; 737 738 static inline uint64_t ODY_IOBNX_MSIX_VECX_CTL(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 739 static inline uint64_t ODY_IOBNX_MSIX_VECX_CTL(uint64_t a, uint64_t b) 740 { 741 if ((a <= 4) && (b == 0)) 742 return 0x87e120f00008ll + 0x1000000ll * ((a) & 0x7); 743 __ody_csr_fatal("IOBNX_MSIX_VECX_CTL", 2, a, b, 0, 0, 0, 0); 744 } 745 746 #define typedef_ODY_IOBNX_MSIX_VECX_CTL(a, b) ody_iobnx_msix_vecx_ctl_t 747 #define bustype_ODY_IOBNX_MSIX_VECX_CTL(a, b) CSR_TYPE_RSL 748 #define basename_ODY_IOBNX_MSIX_VECX_CTL(a, b) "IOBNX_MSIX_VECX_CTL" 749 #define device_bar_ODY_IOBNX_MSIX_VECX_CTL(a, b) 0x4 /* PF_BAR4 */ 750 #define busnum_ODY_IOBNX_MSIX_VECX_CTL(a, b) (a) 751 #define arguments_ODY_IOBNX_MSIX_VECX_CTL(a, b) (a), (b), -1, -1 752 753 /** 754 * Register (RSL) iobn#_ncb#_acc 755 * 756 * IOBN NCB Access Registers 757 * This register sets attributes of NCBDIDs address bits \<43:36\>. 758 * If IOBN_CONST.UNIMP_REG is set this register is not implemented. 759 * Reads will respond with zero and writes will be ignored. 760 */ 761 union ody_iobnx_ncbx_acc { 762 uint64_t u; 763 struct ody_iobnx_ncbx_acc_s { 764 uint64_t all_cmds : 1; 765 uint64_t reserved_1_63 : 63; 766 } s; 767 /* struct ody_iobnx_ncbx_acc_s cn; */ 768 }; 769 typedef union ody_iobnx_ncbx_acc ody_iobnx_ncbx_acc_t; 770 771 static inline uint64_t ODY_IOBNX_NCBX_ACC(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 772 static inline uint64_t ODY_IOBNX_NCBX_ACC(uint64_t a, uint64_t b) 773 { 774 if ((a <= 4) && (b <= 255)) 775 return 0x87e1200c0000ll + 0x1000000ll * ((a) & 0x7) + 8ll * ((b) & 0xff); 776 __ody_csr_fatal("IOBNX_NCBX_ACC", 2, a, b, 0, 0, 0, 0); 777 } 778 779 #define typedef_ODY_IOBNX_NCBX_ACC(a, b) ody_iobnx_ncbx_acc_t 780 #define bustype_ODY_IOBNX_NCBX_ACC(a, b) CSR_TYPE_RSL 781 #define basename_ODY_IOBNX_NCBX_ACC(a, b) "IOBNX_NCBX_ACC" 782 #define device_bar_ODY_IOBNX_NCBX_ACC(a, b) 0x0 /* PF_BAR0 */ 783 #define busnum_ODY_IOBNX_NCBX_ACC(a, b) (a) 784 #define arguments_ODY_IOBNX_NCBX_ACC(a, b) (a), (b), -1, -1 785 786 /** 787 * Register (RSL) iobn#_ncb#_permit 788 * 789 * IOBN NCB Bus Permit Registers 790 * This register sets the permissions for access to NCBDIDs address bits \<43:36\>. 791 * Program identically to MRML_NCB()_PERMIT. 792 * If IOBN_CONST.UNIMP_REG is set this register is not implemented. 793 * Reads will respond with zero and writes will be ignored. 794 */ 795 union ody_iobnx_ncbx_permit { 796 uint64_t u; 797 struct ody_iobnx_ncbx_permit_s { 798 uint64_t sec_dis : 1; 799 uint64_t nsec_dis : 1; 800 uint64_t xcp0_dis : 1; 801 uint64_t xcp1_dis : 1; 802 uint64_t xcp2_dis : 1; 803 uint64_t reserved_5_6 : 2; 804 uint64_t kill : 1; 805 uint64_t lock : 1; 806 uint64_t reserved_9_63 : 55; 807 } s; 808 /* struct ody_iobnx_ncbx_permit_s cn; */ 809 }; 810 typedef union ody_iobnx_ncbx_permit ody_iobnx_ncbx_permit_t; 811 812 static inline uint64_t ODY_IOBNX_NCBX_PERMIT(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 813 static inline uint64_t ODY_IOBNX_NCBX_PERMIT(uint64_t a, uint64_t b) 814 { 815 if ((a <= 4) && (b <= 255)) 816 return 0x87e1200d0000ll + 0x1000000ll * ((a) & 0x7) + 8ll * ((b) & 0xff); 817 __ody_csr_fatal("IOBNX_NCBX_PERMIT", 2, a, b, 0, 0, 0, 0); 818 } 819 820 #define typedef_ODY_IOBNX_NCBX_PERMIT(a, b) ody_iobnx_ncbx_permit_t 821 #define bustype_ODY_IOBNX_NCBX_PERMIT(a, b) CSR_TYPE_RSL 822 #define basename_ODY_IOBNX_NCBX_PERMIT(a, b) "IOBNX_NCBX_PERMIT" 823 #define device_bar_ODY_IOBNX_NCBX_PERMIT(a, b) 0x0 /* PF_BAR0 */ 824 #define busnum_ODY_IOBNX_NCBX_PERMIT(a, b) (a) 825 #define arguments_ODY_IOBNX_NCBX_PERMIT(a, b) (a), (b), -1, -1 826 827 /** 828 * Register (RSL) iobn#_ncbi#_cr_err_status 829 * 830 * IOBN NCBI Unexpected CR Error Status Register 831 * NCBI error status register logs first unexpected NCBI CR. 832 */ 833 union ody_iobnx_ncbix_cr_err_status { 834 uint64_t u; 835 struct ody_iobnx_ncbix_cr_err_status_s { 836 uint64_t narbid : 4; 837 uint64_t reserved_4_63 : 60; 838 } s; 839 /* struct ody_iobnx_ncbix_cr_err_status_s cn; */ 840 }; 841 typedef union ody_iobnx_ncbix_cr_err_status ody_iobnx_ncbix_cr_err_status_t; 842 843 static inline uint64_t ODY_IOBNX_NCBIX_CR_ERR_STATUS(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 844 static inline uint64_t ODY_IOBNX_NCBIX_CR_ERR_STATUS(uint64_t a, uint64_t b) 845 { 846 if ((a <= 4) && (b <= 3)) 847 return 0x87e120000100ll + 0x1000000ll * ((a) & 0x7) + 8ll * ((b) & 0x3); 848 __ody_csr_fatal("IOBNX_NCBIX_CR_ERR_STATUS", 2, a, b, 0, 0, 0, 0); 849 } 850 851 #define typedef_ODY_IOBNX_NCBIX_CR_ERR_STATUS(a, b) ody_iobnx_ncbix_cr_err_status_t 852 #define bustype_ODY_IOBNX_NCBIX_CR_ERR_STATUS(a, b) CSR_TYPE_RSL 853 #define basename_ODY_IOBNX_NCBIX_CR_ERR_STATUS(a, b) "IOBNX_NCBIX_CR_ERR_STATUS" 854 #define device_bar_ODY_IOBNX_NCBIX_CR_ERR_STATUS(a, b) 0x0 /* PF_BAR0 */ 855 #define busnum_ODY_IOBNX_NCBIX_CR_ERR_STATUS(a, b) (a) 856 #define arguments_ODY_IOBNX_NCBIX_CR_ERR_STATUS(a, b) (a), (b), -1, -1 857 858 /** 859 * Register (RSL) iobn#_ncbo#_cr_err_status 860 * 861 * IOBN NCBO CR Error Status Register 862 * Outbound error status register logs first data error detected on outbound path. 863 */ 864 union ody_iobnx_ncbox_cr_err_status { 865 uint64_t u; 866 struct ody_iobnx_ncbox_cr_err_status_s { 867 uint64_t address : 53; 868 uint64_t narbid : 4; 869 uint64_t reserved_57_63 : 7; 870 } s; 871 /* struct ody_iobnx_ncbox_cr_err_status_s cn; */ 872 }; 873 typedef union ody_iobnx_ncbox_cr_err_status ody_iobnx_ncbox_cr_err_status_t; 874 875 static inline uint64_t ODY_IOBNX_NCBOX_CR_ERR_STATUS(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 876 static inline uint64_t ODY_IOBNX_NCBOX_CR_ERR_STATUS(uint64_t a, uint64_t b) 877 { 878 if ((a <= 4) && (b <= 3)) 879 return 0x87e120000120ll + 0x1000000ll * ((a) & 0x7) + 8ll * ((b) & 0x3); 880 __ody_csr_fatal("IOBNX_NCBOX_CR_ERR_STATUS", 2, a, b, 0, 0, 0, 0); 881 } 882 883 #define typedef_ODY_IOBNX_NCBOX_CR_ERR_STATUS(a, b) ody_iobnx_ncbox_cr_err_status_t 884 #define bustype_ODY_IOBNX_NCBOX_CR_ERR_STATUS(a, b) CSR_TYPE_RSL 885 #define basename_ODY_IOBNX_NCBOX_CR_ERR_STATUS(a, b) "IOBNX_NCBOX_CR_ERR_STATUS" 886 #define device_bar_ODY_IOBNX_NCBOX_CR_ERR_STATUS(a, b) 0x0 /* PF_BAR0 */ 887 #define busnum_ODY_IOBNX_NCBOX_CR_ERR_STATUS(a, b) (a) 888 #define arguments_ODY_IOBNX_NCBOX_CR_ERR_STATUS(a, b) (a), (b), -1, -1 889 890 /** 891 * Register (RSL) iobn#_ncbo#_psn_status 892 * 893 * IOBN NCBO Poison Status Register 894 */ 895 union ody_iobnx_ncbox_psn_status { 896 uint64_t u; 897 struct ody_iobnx_ncbox_psn_status_s { 898 uint64_t address : 52; 899 uint64_t reserved_52_63 : 12; 900 } s; 901 /* struct ody_iobnx_ncbox_psn_status_s cn; */ 902 }; 903 typedef union ody_iobnx_ncbox_psn_status ody_iobnx_ncbox_psn_status_t; 904 905 static inline uint64_t ODY_IOBNX_NCBOX_PSN_STATUS(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 906 static inline uint64_t ODY_IOBNX_NCBOX_PSN_STATUS(uint64_t a, uint64_t b) 907 { 908 if ((a <= 4) && (b <= 3)) 909 return 0x87e120003040ll + 0x1000000ll * ((a) & 0x7) + 8ll * ((b) & 0x3); 910 __ody_csr_fatal("IOBNX_NCBOX_PSN_STATUS", 2, a, b, 0, 0, 0, 0); 911 } 912 913 #define typedef_ODY_IOBNX_NCBOX_PSN_STATUS(a, b) ody_iobnx_ncbox_psn_status_t 914 #define bustype_ODY_IOBNX_NCBOX_PSN_STATUS(a, b) CSR_TYPE_RSL 915 #define basename_ODY_IOBNX_NCBOX_PSN_STATUS(a, b) "IOBNX_NCBOX_PSN_STATUS" 916 #define device_bar_ODY_IOBNX_NCBOX_PSN_STATUS(a, b) 0x0 /* PF_BAR0 */ 917 #define busnum_ODY_IOBNX_NCBOX_PSN_STATUS(a, b) (a) 918 #define arguments_ODY_IOBNX_NCBOX_PSN_STATUS(a, b) (a), (b), -1, -1 919 920 /** 921 * Register (RSL) iobn#_ncbo_to 922 * 923 * IOBN NCBO Timeout Counter Registers 924 * This register set the counter value for expected return data on NCBI. 925 */ 926 union ody_iobnx_ncbo_to { 927 uint64_t u; 928 struct ody_iobnx_ncbo_to_s { 929 uint64_t sub_time : 32; 930 uint64_t reserved_32_63 : 32; 931 } s; 932 /* struct ody_iobnx_ncbo_to_s cn; */ 933 }; 934 typedef union ody_iobnx_ncbo_to ody_iobnx_ncbo_to_t; 935 936 static inline uint64_t ODY_IOBNX_NCBO_TO(uint64_t a) __attribute__ ((pure, always_inline)); 937 static inline uint64_t ODY_IOBNX_NCBO_TO(uint64_t a) 938 { 939 if (a <= 4) 940 return 0x87e120000008ll + 0x1000000ll * ((a) & 0x7); 941 __ody_csr_fatal("IOBNX_NCBO_TO", 1, a, 0, 0, 0, 0, 0); 942 } 943 944 #define typedef_ODY_IOBNX_NCBO_TO(a) ody_iobnx_ncbo_to_t 945 #define bustype_ODY_IOBNX_NCBO_TO(a) CSR_TYPE_RSL 946 #define basename_ODY_IOBNX_NCBO_TO(a) "IOBNX_NCBO_TO" 947 #define device_bar_ODY_IOBNX_NCBO_TO(a) 0x0 /* PF_BAR0 */ 948 #define busnum_ODY_IOBNX_NCBO_TO(a) (a) 949 #define arguments_ODY_IOBNX_NCBO_TO(a) (a), -1, -1, -1 950 951 /** 952 * Register (RSL) iobn#_ncbo_to_err# 953 * 954 * IOBN NCB Timeout Error Register 955 * This register captures error information for a nonposted request that times out on 956 * NCBO (when IOBN_INT_SUM[NCBO_TO] is set). 957 */ 958 union ody_iobnx_ncbo_to_errx { 959 uint64_t u; 960 struct ody_iobnx_ncbo_to_errx_s { 961 uint64_t arbid : 4; 962 uint64_t reserved_4_7 : 4; 963 uint64_t cpid : 9; 964 uint64_t reserved_17_63 : 47; 965 } s; 966 /* struct ody_iobnx_ncbo_to_errx_s cn; */ 967 }; 968 typedef union ody_iobnx_ncbo_to_errx ody_iobnx_ncbo_to_errx_t; 969 970 static inline uint64_t ODY_IOBNX_NCBO_TO_ERRX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 971 static inline uint64_t ODY_IOBNX_NCBO_TO_ERRX(uint64_t a, uint64_t b) 972 { 973 if ((a <= 4) && (b <= 3)) 974 return 0x87e1200a0000ll + 0x1000000ll * ((a) & 0x7) + 8ll * ((b) & 0x3); 975 __ody_csr_fatal("IOBNX_NCBO_TO_ERRX", 2, a, b, 0, 0, 0, 0); 976 } 977 978 #define typedef_ODY_IOBNX_NCBO_TO_ERRX(a, b) ody_iobnx_ncbo_to_errx_t 979 #define bustype_ODY_IOBNX_NCBO_TO_ERRX(a, b) CSR_TYPE_RSL 980 #define basename_ODY_IOBNX_NCBO_TO_ERRX(a, b) "IOBNX_NCBO_TO_ERRX" 981 #define device_bar_ODY_IOBNX_NCBO_TO_ERRX(a, b) 0x0 /* PF_BAR0 */ 982 #define busnum_ODY_IOBNX_NCBO_TO_ERRX(a, b) (a) 983 #define arguments_ODY_IOBNX_NCBO_TO_ERRX(a, b) (a), (b), -1, -1 984 985 /** 986 * Register (RSL) iobn#_outb_err_status 987 * 988 * IOBN Outbound Error Status Register 989 * Outbound error status register logs first error detected on outbound control path. 990 */ 991 union ody_iobnx_outb_err_status { 992 uint64_t u; 993 struct ody_iobnx_outb_err_status_s { 994 uint64_t err_type : 5; 995 uint64_t reserved_5_11 : 7; 996 uint64_t address : 40; 997 uint64_t reserved_52 : 1; 998 uint64_t ms : 11; 999 } s; 1000 /* struct ody_iobnx_outb_err_status_s cn; */ 1001 }; 1002 typedef union ody_iobnx_outb_err_status ody_iobnx_outb_err_status_t; 1003 1004 static inline uint64_t ODY_IOBNX_OUTB_ERR_STATUS(uint64_t a) __attribute__ ((pure, always_inline)); 1005 static inline uint64_t ODY_IOBNX_OUTB_ERR_STATUS(uint64_t a) 1006 { 1007 if (a <= 4) 1008 return 0x87e120083090ll + 0x1000000ll * ((a) & 0x7); 1009 __ody_csr_fatal("IOBNX_OUTB_ERR_STATUS", 1, a, 0, 0, 0, 0, 0); 1010 } 1011 1012 #define typedef_ODY_IOBNX_OUTB_ERR_STATUS(a) ody_iobnx_outb_err_status_t 1013 #define bustype_ODY_IOBNX_OUTB_ERR_STATUS(a) CSR_TYPE_RSL 1014 #define basename_ODY_IOBNX_OUTB_ERR_STATUS(a) "IOBNX_OUTB_ERR_STATUS" 1015 #define device_bar_ODY_IOBNX_OUTB_ERR_STATUS(a) 0x0 /* PF_BAR0 */ 1016 #define busnum_ODY_IOBNX_OUTB_ERR_STATUS(a) (a) 1017 #define arguments_ODY_IOBNX_OUTB_ERR_STATUS(a) (a), -1, -1, -1 1018 1019 /** 1020 * Register (RSL) iobn#_psn_ctl 1021 * 1022 * Poison Control Register 1023 */ 1024 union ody_iobnx_psn_ctl { 1025 uint64_t u; 1026 struct ody_iobnx_psn_ctl_s { 1027 uint64_t dispsn : 1; 1028 uint64_t reserved_1_63 : 63; 1029 } s; 1030 /* struct ody_iobnx_psn_ctl_s cn; */ 1031 }; 1032 typedef union ody_iobnx_psn_ctl ody_iobnx_psn_ctl_t; 1033 1034 static inline uint64_t ODY_IOBNX_PSN_CTL(uint64_t a) __attribute__ ((pure, always_inline)); 1035 static inline uint64_t ODY_IOBNX_PSN_CTL(uint64_t a) 1036 { 1037 if (a <= 4) 1038 return 0x87e120083050ll + 0x1000000ll * ((a) & 0x7); 1039 __ody_csr_fatal("IOBNX_PSN_CTL", 1, a, 0, 0, 0, 0, 0); 1040 } 1041 1042 #define typedef_ODY_IOBNX_PSN_CTL(a) ody_iobnx_psn_ctl_t 1043 #define bustype_ODY_IOBNX_PSN_CTL(a) CSR_TYPE_RSL 1044 #define basename_ODY_IOBNX_PSN_CTL(a) "IOBNX_PSN_CTL" 1045 #define device_bar_ODY_IOBNX_PSN_CTL(a) 0x0 /* PF_BAR0 */ 1046 #define busnum_ODY_IOBNX_PSN_CTL(a) (a) 1047 #define arguments_ODY_IOBNX_PSN_CTL(a) (a), -1, -1, -1 1048 1049 /** 1050 * Register (RSL) iobn#_rsl#_streams 1051 * 1052 * IOBN RSL Stream Permission Registers 1053 * This register sets the permissions for a NCBI transaction (which are DMA 1054 * transactions or MSI-X writes), for requests from a RSL device, i.e. 1055 * those where: 1056 * 1057 * _ stream_id\<21:8\> = PCC_DEV_CON_E::MRML\<21:8\> 1058 * (stream_id\<7:0\> + 0). 1059 * 1060 * _ stream_id\<21:8\> = PCC_DEV_CON_E::MRMLB1\<21:8\> 1061 * (stream_id\<7:0\> + 256). 1062 * 1063 * _ stream_id\<21:8\> = PCC_DEV_CON_E::MRMLB2\<21:8\> 1064 * (stream_id\<7:0\> + 512). 1065 * 1066 * _ stream_id\<21:8\> = PCC_DEV_CON_E::MRMLB3\<21:8\> 1067 * (stream_id\<7:0\> + 768). 1068 * 1069 * For each given index {a} (the RSL function number), each IOB 1070 * must be programmed to the same value. 1071 */ 1072 union ody_iobnx_rslx_streams { 1073 uint64_t u; 1074 struct ody_iobnx_rslx_streams_s { 1075 uint64_t phys_nsec : 1; 1076 uint64_t strm_nsec : 1; 1077 uint64_t reserved_2_63 : 62; 1078 } s; 1079 /* struct ody_iobnx_rslx_streams_s cn; */ 1080 }; 1081 typedef union ody_iobnx_rslx_streams ody_iobnx_rslx_streams_t; 1082 1083 static inline uint64_t ODY_IOBNX_RSLX_STREAMS(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 1084 static inline uint64_t ODY_IOBNX_RSLX_STREAMS(uint64_t a, uint64_t b) 1085 { 1086 if ((a <= 4) && (b <= 1023)) 1087 return 0x87e120004000ll + 0x1000000ll * ((a) & 0x7) + 8ll * ((b) & 0x3ff); 1088 __ody_csr_fatal("IOBNX_RSLX_STREAMS", 2, a, b, 0, 0, 0, 0); 1089 } 1090 1091 #define typedef_ODY_IOBNX_RSLX_STREAMS(a, b) ody_iobnx_rslx_streams_t 1092 #define bustype_ODY_IOBNX_RSLX_STREAMS(a, b) CSR_TYPE_RSL 1093 #define basename_ODY_IOBNX_RSLX_STREAMS(a, b) "IOBNX_RSLX_STREAMS" 1094 #define device_bar_ODY_IOBNX_RSLX_STREAMS(a, b) 0x0 /* PF_BAR0 */ 1095 #define busnum_ODY_IOBNX_RSLX_STREAMS(a, b) (a) 1096 #define arguments_ODY_IOBNX_RSLX_STREAMS(a, b) (a), (b), -1, -1 1097 1098 #endif /* __ODY_CSRS_IOBN_H__ */ 1099