1 #ifndef __ODY_CSRS_DSUUB_H__ 2 #define __ODY_CSRS_DSUUB_H__ 3 /* This file is auto-generated. Do not edit */ 4 5 /***********************license start*********************************** 6 * Copyright (C) 2021-2026 Marvell. 7 * SPDX-License-Identifier: BSD-3-Clause 8 * https://spdx.org/licenses 9 ***********************license end**************************************/ 10 11 12 /** 13 * @file 14 * 15 * Configuration and status register (CSR) address and type definitions for 16 * DSUUB. 17 * 18 * This file is auto generated. Do not edit. 19 * 20 */ 21 22 /** 23 * Enumeration dsuub_bar_e 24 * 25 * DSUUB Base Address Register Enumeration 26 * Enumerates the base address registers. 27 */ 28 #define ODY_DSUUB_BAR_E_DSUUBX_PF_BAR0(a) (0x87e2ef000000ll + 0x1000000ll * (a)) 29 #define ODY_DSUUB_BAR_E_DSUUBX_PF_BAR0_SIZE 0x1000000ull 30 31 /** 32 * Register (RSL32b) dsuub#_amcfgr 33 * 34 * Dsuub Activity Monitors Configuration Register 35 * Global configuration register for the activity monitors. 36 * 37 * Provides information on supported features, the number of counter groups implemented, the total 38 * number of activity monitor event counters implemented, and the size of the counters. AMCFGR is 39 * applicable to both the architected and the auxiliary counter groups. 40 */ 41 union ody_dsuubx_amcfgr { 42 uint32_t u; 43 struct ody_dsuubx_amcfgr_s { 44 uint32_t n : 8; 45 uint32_t size : 6; 46 uint32_t reserved_14_23 : 10; 47 uint32_t hdbg : 1; 48 uint32_t reserved_25_27 : 3; 49 uint32_t ncg : 4; 50 } s; 51 /* struct ody_dsuubx_amcfgr_s cn; */ 52 }; 53 typedef union ody_dsuubx_amcfgr ody_dsuubx_amcfgr_t; 54 55 static inline uint64_t ODY_DSUUBX_AMCFGR(uint64_t a) __attribute__ ((pure, always_inline)); 56 static inline uint64_t ODY_DSUUBX_AMCFGR(uint64_t a) 57 { 58 if (a <= 89) 59 return 0x87e2ef090e00ll + 0x1000000ll * ((a) & 0x7f); 60 __ody_csr_fatal("DSUUBX_AMCFGR", 1, a, 0, 0, 0, 0, 0); 61 } 62 63 #define typedef_ODY_DSUUBX_AMCFGR(a) ody_dsuubx_amcfgr_t 64 #define bustype_ODY_DSUUBX_AMCFGR(a) CSR_TYPE_RSL32b 65 #define basename_ODY_DSUUBX_AMCFGR(a) "DSUUBX_AMCFGR" 66 #define device_bar_ODY_DSUUBX_AMCFGR(a) 0x0 /* PF_BAR0 */ 67 #define busnum_ODY_DSUUBX_AMCFGR(a) (a) 68 #define arguments_ODY_DSUUBX_AMCFGR(a) (a), -1, -1, -1 69 70 /** 71 * Register (RSL32b) dsuub#_amcgcr 72 * 73 * Dsuub Activity Monitors Counter Group Configuration Register 74 * Provides information on the number of activity monitor event counters implemented within each 75 * counter group. 76 */ 77 union ody_dsuubx_amcgcr { 78 uint32_t u; 79 struct ody_dsuubx_amcgcr_s { 80 uint32_t cg0nc : 8; 81 uint32_t cg1nc : 8; 82 uint32_t reserved_16_31 : 16; 83 } s; 84 /* struct ody_dsuubx_amcgcr_s cn; */ 85 }; 86 typedef union ody_dsuubx_amcgcr ody_dsuubx_amcgcr_t; 87 88 static inline uint64_t ODY_DSUUBX_AMCGCR(uint64_t a) __attribute__ ((pure, always_inline)); 89 static inline uint64_t ODY_DSUUBX_AMCGCR(uint64_t a) 90 { 91 if (a <= 89) 92 return 0x87e2ef090ce0ll + 0x1000000ll * ((a) & 0x7f); 93 __ody_csr_fatal("DSUUBX_AMCGCR", 1, a, 0, 0, 0, 0, 0); 94 } 95 96 #define typedef_ODY_DSUUBX_AMCGCR(a) ody_dsuubx_amcgcr_t 97 #define bustype_ODY_DSUUBX_AMCGCR(a) CSR_TYPE_RSL32b 98 #define basename_ODY_DSUUBX_AMCGCR(a) "DSUUBX_AMCGCR" 99 #define device_bar_ODY_DSUUBX_AMCGCR(a) 0x0 /* PF_BAR0 */ 100 #define busnum_ODY_DSUUBX_AMCGCR(a) (a) 101 #define arguments_ODY_DSUUBX_AMCGCR(a) (a), -1, -1, -1 102 103 /** 104 * Register (RSL32b) dsuub#_amcidr0 105 * 106 * Dsuub Activity Monitors Component Identification Register 0 107 * Provides information to identify an activity monitors component. 108 * 109 * For more information, see 'About the Component identification scheme'. 110 */ 111 union ody_dsuubx_amcidr0 { 112 uint32_t u; 113 struct ody_dsuubx_amcidr0_s { 114 uint32_t prmbl_0 : 8; 115 uint32_t reserved_8_31 : 24; 116 } s; 117 /* struct ody_dsuubx_amcidr0_s cn; */ 118 }; 119 typedef union ody_dsuubx_amcidr0 ody_dsuubx_amcidr0_t; 120 121 static inline uint64_t ODY_DSUUBX_AMCIDR0(uint64_t a) __attribute__ ((pure, always_inline)); 122 static inline uint64_t ODY_DSUUBX_AMCIDR0(uint64_t a) 123 { 124 if (a <= 89) 125 return 0x87e2ef090ff0ll + 0x1000000ll * ((a) & 0x7f); 126 __ody_csr_fatal("DSUUBX_AMCIDR0", 1, a, 0, 0, 0, 0, 0); 127 } 128 129 #define typedef_ODY_DSUUBX_AMCIDR0(a) ody_dsuubx_amcidr0_t 130 #define bustype_ODY_DSUUBX_AMCIDR0(a) CSR_TYPE_RSL32b 131 #define basename_ODY_DSUUBX_AMCIDR0(a) "DSUUBX_AMCIDR0" 132 #define device_bar_ODY_DSUUBX_AMCIDR0(a) 0x0 /* PF_BAR0 */ 133 #define busnum_ODY_DSUUBX_AMCIDR0(a) (a) 134 #define arguments_ODY_DSUUBX_AMCIDR0(a) (a), -1, -1, -1 135 136 /** 137 * Register (RSL32b) dsuub#_amcidr1 138 * 139 * Dsuub Activity Monitors Component Identification Register 1 140 * Provides information to identify an activity monitors component. 141 * 142 * For more information, see 'About the Component identification scheme'. 143 */ 144 union ody_dsuubx_amcidr1 { 145 uint32_t u; 146 struct ody_dsuubx_amcidr1_s { 147 uint32_t prmbl_1 : 4; 148 uint32_t clas : 4; 149 uint32_t reserved_8_31 : 24; 150 } s; 151 /* struct ody_dsuubx_amcidr1_s cn; */ 152 }; 153 typedef union ody_dsuubx_amcidr1 ody_dsuubx_amcidr1_t; 154 155 static inline uint64_t ODY_DSUUBX_AMCIDR1(uint64_t a) __attribute__ ((pure, always_inline)); 156 static inline uint64_t ODY_DSUUBX_AMCIDR1(uint64_t a) 157 { 158 if (a <= 89) 159 return 0x87e2ef090ff4ll + 0x1000000ll * ((a) & 0x7f); 160 __ody_csr_fatal("DSUUBX_AMCIDR1", 1, a, 0, 0, 0, 0, 0); 161 } 162 163 #define typedef_ODY_DSUUBX_AMCIDR1(a) ody_dsuubx_amcidr1_t 164 #define bustype_ODY_DSUUBX_AMCIDR1(a) CSR_TYPE_RSL32b 165 #define basename_ODY_DSUUBX_AMCIDR1(a) "DSUUBX_AMCIDR1" 166 #define device_bar_ODY_DSUUBX_AMCIDR1(a) 0x0 /* PF_BAR0 */ 167 #define busnum_ODY_DSUUBX_AMCIDR1(a) (a) 168 #define arguments_ODY_DSUUBX_AMCIDR1(a) (a), -1, -1, -1 169 170 /** 171 * Register (RSL32b) dsuub#_amcidr2 172 * 173 * Dsuub Activity Monitors Component Identification Register 2 174 * Provides information to identify an activity monitors component. 175 * 176 * For more information, see 'About the Component identification scheme'. 177 */ 178 union ody_dsuubx_amcidr2 { 179 uint32_t u; 180 struct ody_dsuubx_amcidr2_s { 181 uint32_t prmbl_2 : 8; 182 uint32_t reserved_8_31 : 24; 183 } s; 184 /* struct ody_dsuubx_amcidr2_s cn; */ 185 }; 186 typedef union ody_dsuubx_amcidr2 ody_dsuubx_amcidr2_t; 187 188 static inline uint64_t ODY_DSUUBX_AMCIDR2(uint64_t a) __attribute__ ((pure, always_inline)); 189 static inline uint64_t ODY_DSUUBX_AMCIDR2(uint64_t a) 190 { 191 if (a <= 89) 192 return 0x87e2ef090ff8ll + 0x1000000ll * ((a) & 0x7f); 193 __ody_csr_fatal("DSUUBX_AMCIDR2", 1, a, 0, 0, 0, 0, 0); 194 } 195 196 #define typedef_ODY_DSUUBX_AMCIDR2(a) ody_dsuubx_amcidr2_t 197 #define bustype_ODY_DSUUBX_AMCIDR2(a) CSR_TYPE_RSL32b 198 #define basename_ODY_DSUUBX_AMCIDR2(a) "DSUUBX_AMCIDR2" 199 #define device_bar_ODY_DSUUBX_AMCIDR2(a) 0x0 /* PF_BAR0 */ 200 #define busnum_ODY_DSUUBX_AMCIDR2(a) (a) 201 #define arguments_ODY_DSUUBX_AMCIDR2(a) (a), -1, -1, -1 202 203 /** 204 * Register (RSL32b) dsuub#_amcidr3 205 * 206 * Dsuub Activity Monitors Component Identification Register 2 207 * Provides information to identify an activity monitors component. 208 * 209 * For more information, see 'About the Component identification scheme'. 210 */ 211 union ody_dsuubx_amcidr3 { 212 uint32_t u; 213 struct ody_dsuubx_amcidr3_s { 214 uint32_t prmbl_3 : 8; 215 uint32_t reserved_8_31 : 24; 216 } s; 217 /* struct ody_dsuubx_amcidr3_s cn; */ 218 }; 219 typedef union ody_dsuubx_amcidr3 ody_dsuubx_amcidr3_t; 220 221 static inline uint64_t ODY_DSUUBX_AMCIDR3(uint64_t a) __attribute__ ((pure, always_inline)); 222 static inline uint64_t ODY_DSUUBX_AMCIDR3(uint64_t a) 223 { 224 if (a <= 89) 225 return 0x87e2ef090ffcll + 0x1000000ll * ((a) & 0x7f); 226 __ody_csr_fatal("DSUUBX_AMCIDR3", 1, a, 0, 0, 0, 0, 0); 227 } 228 229 #define typedef_ODY_DSUUBX_AMCIDR3(a) ody_dsuubx_amcidr3_t 230 #define bustype_ODY_DSUUBX_AMCIDR3(a) CSR_TYPE_RSL32b 231 #define basename_ODY_DSUUBX_AMCIDR3(a) "DSUUBX_AMCIDR3" 232 #define device_bar_ODY_DSUUBX_AMCIDR3(a) 0x0 /* PF_BAR0 */ 233 #define busnum_ODY_DSUUBX_AMCIDR3(a) (a) 234 #define arguments_ODY_DSUUBX_AMCIDR3(a) (a), -1, -1, -1 235 236 /** 237 * Register (RSL32b) dsuub#_amcntenclr0 238 * 239 * Dsuub Activity Monitors Count Enable Clear Register 0 240 * Disable control bits for the architected activity monitors event counters, AMEVCNTR0\<n\>. 241 */ 242 union ody_dsuubx_amcntenclr0 { 243 uint32_t u; 244 struct ody_dsuubx_amcntenclr0_s { 245 uint32_t p : 32; 246 } s; 247 /* struct ody_dsuubx_amcntenclr0_s cn; */ 248 }; 249 typedef union ody_dsuubx_amcntenclr0 ody_dsuubx_amcntenclr0_t; 250 251 static inline uint64_t ODY_DSUUBX_AMCNTENCLR0(uint64_t a) __attribute__ ((pure, always_inline)); 252 static inline uint64_t ODY_DSUUBX_AMCNTENCLR0(uint64_t a) 253 { 254 if (a <= 89) 255 return 0x87e2ef090c20ll + 0x1000000ll * ((a) & 0x7f); 256 __ody_csr_fatal("DSUUBX_AMCNTENCLR0", 1, a, 0, 0, 0, 0, 0); 257 } 258 259 #define typedef_ODY_DSUUBX_AMCNTENCLR0(a) ody_dsuubx_amcntenclr0_t 260 #define bustype_ODY_DSUUBX_AMCNTENCLR0(a) CSR_TYPE_RSL32b 261 #define basename_ODY_DSUUBX_AMCNTENCLR0(a) "DSUUBX_AMCNTENCLR0" 262 #define device_bar_ODY_DSUUBX_AMCNTENCLR0(a) 0x0 /* PF_BAR0 */ 263 #define busnum_ODY_DSUUBX_AMCNTENCLR0(a) (a) 264 #define arguments_ODY_DSUUBX_AMCNTENCLR0(a) (a), -1, -1, -1 265 266 /** 267 * Register (RSL32b) dsuub#_amcntenclr1 268 * 269 * Dsuub Activity Monitors Count Enable Clear Register 1 270 * Disable control bits for the architected activity monitors event counters, AMEVCNTR1\<n\>. 271 */ 272 union ody_dsuubx_amcntenclr1 { 273 uint32_t u; 274 struct ody_dsuubx_amcntenclr1_s { 275 uint32_t p : 32; 276 } s; 277 /* struct ody_dsuubx_amcntenclr1_s cn; */ 278 }; 279 typedef union ody_dsuubx_amcntenclr1 ody_dsuubx_amcntenclr1_t; 280 281 static inline uint64_t ODY_DSUUBX_AMCNTENCLR1(uint64_t a) __attribute__ ((pure, always_inline)); 282 static inline uint64_t ODY_DSUUBX_AMCNTENCLR1(uint64_t a) 283 { 284 if (a <= 89) 285 return 0x87e2ef090c24ll + 0x1000000ll * ((a) & 0x7f); 286 __ody_csr_fatal("DSUUBX_AMCNTENCLR1", 1, a, 0, 0, 0, 0, 0); 287 } 288 289 #define typedef_ODY_DSUUBX_AMCNTENCLR1(a) ody_dsuubx_amcntenclr1_t 290 #define bustype_ODY_DSUUBX_AMCNTENCLR1(a) CSR_TYPE_RSL32b 291 #define basename_ODY_DSUUBX_AMCNTENCLR1(a) "DSUUBX_AMCNTENCLR1" 292 #define device_bar_ODY_DSUUBX_AMCNTENCLR1(a) 0x0 /* PF_BAR0 */ 293 #define busnum_ODY_DSUUBX_AMCNTENCLR1(a) (a) 294 #define arguments_ODY_DSUUBX_AMCNTENCLR1(a) (a), -1, -1, -1 295 296 /** 297 * Register (RSL32b) dsuub#_amcntenset0 298 * 299 * Dsuub Activity Monitors Count Enable Set Register 0 300 * Enable control bits for the architected activity monitors event counters, AMEVCNTR0\<n\>. 301 */ 302 union ody_dsuubx_amcntenset0 { 303 uint32_t u; 304 struct ody_dsuubx_amcntenset0_s { 305 uint32_t p : 32; 306 } s; 307 /* struct ody_dsuubx_amcntenset0_s cn; */ 308 }; 309 typedef union ody_dsuubx_amcntenset0 ody_dsuubx_amcntenset0_t; 310 311 static inline uint64_t ODY_DSUUBX_AMCNTENSET0(uint64_t a) __attribute__ ((pure, always_inline)); 312 static inline uint64_t ODY_DSUUBX_AMCNTENSET0(uint64_t a) 313 { 314 if (a <= 89) 315 return 0x87e2ef090c00ll + 0x1000000ll * ((a) & 0x7f); 316 __ody_csr_fatal("DSUUBX_AMCNTENSET0", 1, a, 0, 0, 0, 0, 0); 317 } 318 319 #define typedef_ODY_DSUUBX_AMCNTENSET0(a) ody_dsuubx_amcntenset0_t 320 #define bustype_ODY_DSUUBX_AMCNTENSET0(a) CSR_TYPE_RSL32b 321 #define basename_ODY_DSUUBX_AMCNTENSET0(a) "DSUUBX_AMCNTENSET0" 322 #define device_bar_ODY_DSUUBX_AMCNTENSET0(a) 0x0 /* PF_BAR0 */ 323 #define busnum_ODY_DSUUBX_AMCNTENSET0(a) (a) 324 #define arguments_ODY_DSUUBX_AMCNTENSET0(a) (a), -1, -1, -1 325 326 /** 327 * Register (RSL32b) dsuub#_amcntenset1 328 * 329 * Dsuub Activity Monitors Count Enable Set Register 1 330 * Enable control bits for the auxiliary activity monitors event counters, AMEVCNTR1\<n\>. 331 */ 332 union ody_dsuubx_amcntenset1 { 333 uint32_t u; 334 struct ody_dsuubx_amcntenset1_s { 335 uint32_t p : 32; 336 } s; 337 /* struct ody_dsuubx_amcntenset1_s cn; */ 338 }; 339 typedef union ody_dsuubx_amcntenset1 ody_dsuubx_amcntenset1_t; 340 341 static inline uint64_t ODY_DSUUBX_AMCNTENSET1(uint64_t a) __attribute__ ((pure, always_inline)); 342 static inline uint64_t ODY_DSUUBX_AMCNTENSET1(uint64_t a) 343 { 344 if (a <= 89) 345 return 0x87e2ef090c04ll + 0x1000000ll * ((a) & 0x7f); 346 __ody_csr_fatal("DSUUBX_AMCNTENSET1", 1, a, 0, 0, 0, 0, 0); 347 } 348 349 #define typedef_ODY_DSUUBX_AMCNTENSET1(a) ody_dsuubx_amcntenset1_t 350 #define bustype_ODY_DSUUBX_AMCNTENSET1(a) CSR_TYPE_RSL32b 351 #define basename_ODY_DSUUBX_AMCNTENSET1(a) "DSUUBX_AMCNTENSET1" 352 #define device_bar_ODY_DSUUBX_AMCNTENSET1(a) 0x0 /* PF_BAR0 */ 353 #define busnum_ODY_DSUUBX_AMCNTENSET1(a) (a) 354 #define arguments_ODY_DSUUBX_AMCNTENSET1(a) (a), -1, -1, -1 355 356 /** 357 * Register (RSL32b) dsuub#_amcr 358 * 359 * Dsuub Activity Monitors Control Register 360 * Global control register for the activity monitors implementation. AMCR is applicable to both the 361 * architected and the auxiliary counter groups. 362 */ 363 union ody_dsuubx_amcr { 364 uint32_t u; 365 struct ody_dsuubx_amcr_s { 366 uint32_t reserved_0_9 : 10; 367 uint32_t hdbg : 1; 368 uint32_t reserved_11_31 : 21; 369 } s; 370 /* struct ody_dsuubx_amcr_s cn; */ 371 }; 372 typedef union ody_dsuubx_amcr ody_dsuubx_amcr_t; 373 374 static inline uint64_t ODY_DSUUBX_AMCR(uint64_t a) __attribute__ ((pure, always_inline)); 375 static inline uint64_t ODY_DSUUBX_AMCR(uint64_t a) 376 { 377 if (a <= 89) 378 return 0x87e2ef090e04ll + 0x1000000ll * ((a) & 0x7f); 379 __ody_csr_fatal("DSUUBX_AMCR", 1, a, 0, 0, 0, 0, 0); 380 } 381 382 #define typedef_ODY_DSUUBX_AMCR(a) ody_dsuubx_amcr_t 383 #define bustype_ODY_DSUUBX_AMCR(a) CSR_TYPE_RSL32b 384 #define basename_ODY_DSUUBX_AMCR(a) "DSUUBX_AMCR" 385 #define device_bar_ODY_DSUUBX_AMCR(a) 0x0 /* PF_BAR0 */ 386 #define busnum_ODY_DSUUBX_AMCR(a) (a) 387 #define arguments_ODY_DSUUBX_AMCR(a) (a), -1, -1, -1 388 389 /** 390 * Register (RSL32b) dsuub#_amdevaff0 391 * 392 * Dsuub Activity Monitors Device Affinity Register 0 393 * Copy of the low half of the PE MPIDR_EL1 register that allows a debugger to determine which PE 394 * in a multiprocessor system the AMU component relates to. 395 */ 396 union ody_dsuubx_amdevaff0 { 397 uint32_t u; 398 struct ody_dsuubx_amdevaff0_s { 399 uint32_t mpidrel1lo : 32; 400 } s; 401 /* struct ody_dsuubx_amdevaff0_s cn; */ 402 }; 403 typedef union ody_dsuubx_amdevaff0 ody_dsuubx_amdevaff0_t; 404 405 static inline uint64_t ODY_DSUUBX_AMDEVAFF0(uint64_t a) __attribute__ ((pure, always_inline)); 406 static inline uint64_t ODY_DSUUBX_AMDEVAFF0(uint64_t a) 407 { 408 if (a <= 89) 409 return 0x87e2ef090fa8ll + 0x1000000ll * ((a) & 0x7f); 410 __ody_csr_fatal("DSUUBX_AMDEVAFF0", 1, a, 0, 0, 0, 0, 0); 411 } 412 413 #define typedef_ODY_DSUUBX_AMDEVAFF0(a) ody_dsuubx_amdevaff0_t 414 #define bustype_ODY_DSUUBX_AMDEVAFF0(a) CSR_TYPE_RSL32b 415 #define basename_ODY_DSUUBX_AMDEVAFF0(a) "DSUUBX_AMDEVAFF0" 416 #define device_bar_ODY_DSUUBX_AMDEVAFF0(a) 0x0 /* PF_BAR0 */ 417 #define busnum_ODY_DSUUBX_AMDEVAFF0(a) (a) 418 #define arguments_ODY_DSUUBX_AMDEVAFF0(a) (a), -1, -1, -1 419 420 /** 421 * Register (RSL32b) dsuub#_amdevaff1 422 * 423 * Dsuub Activity Monitors Device Affinity Register 1 424 * Copy of the high half of the PE MPIDR_EL1 register that allows a debugger to determine which PE 425 * in a multiprocessor system the AMU component relates to. 426 */ 427 union ody_dsuubx_amdevaff1 { 428 uint32_t u; 429 struct ody_dsuubx_amdevaff1_s { 430 uint32_t mpidrel1hi : 32; 431 } s; 432 /* struct ody_dsuubx_amdevaff1_s cn; */ 433 }; 434 typedef union ody_dsuubx_amdevaff1 ody_dsuubx_amdevaff1_t; 435 436 static inline uint64_t ODY_DSUUBX_AMDEVAFF1(uint64_t a) __attribute__ ((pure, always_inline)); 437 static inline uint64_t ODY_DSUUBX_AMDEVAFF1(uint64_t a) 438 { 439 if (a <= 89) 440 return 0x87e2ef090facll + 0x1000000ll * ((a) & 0x7f); 441 __ody_csr_fatal("DSUUBX_AMDEVAFF1", 1, a, 0, 0, 0, 0, 0); 442 } 443 444 #define typedef_ODY_DSUUBX_AMDEVAFF1(a) ody_dsuubx_amdevaff1_t 445 #define bustype_ODY_DSUUBX_AMDEVAFF1(a) CSR_TYPE_RSL32b 446 #define basename_ODY_DSUUBX_AMDEVAFF1(a) "DSUUBX_AMDEVAFF1" 447 #define device_bar_ODY_DSUUBX_AMDEVAFF1(a) 0x0 /* PF_BAR0 */ 448 #define busnum_ODY_DSUUBX_AMDEVAFF1(a) (a) 449 #define arguments_ODY_DSUUBX_AMDEVAFF1(a) (a), -1, -1, -1 450 451 /** 452 * Register (RSL32b) dsuub#_amdevarch 453 * 454 * Dsuub Activity Monitors Device Architecture Register 455 * Identifies the programmers' model architecture of the AMU component. 456 */ 457 union ody_dsuubx_amdevarch { 458 uint32_t u; 459 struct ody_dsuubx_amdevarch_s { 460 uint32_t archid : 16; 461 uint32_t revision : 4; 462 uint32_t present : 1; 463 uint32_t architect : 11; 464 } s; 465 /* struct ody_dsuubx_amdevarch_s cn; */ 466 }; 467 typedef union ody_dsuubx_amdevarch ody_dsuubx_amdevarch_t; 468 469 static inline uint64_t ODY_DSUUBX_AMDEVARCH(uint64_t a) __attribute__ ((pure, always_inline)); 470 static inline uint64_t ODY_DSUUBX_AMDEVARCH(uint64_t a) 471 { 472 if (a <= 89) 473 return 0x87e2ef090fbcll + 0x1000000ll * ((a) & 0x7f); 474 __ody_csr_fatal("DSUUBX_AMDEVARCH", 1, a, 0, 0, 0, 0, 0); 475 } 476 477 #define typedef_ODY_DSUUBX_AMDEVARCH(a) ody_dsuubx_amdevarch_t 478 #define bustype_ODY_DSUUBX_AMDEVARCH(a) CSR_TYPE_RSL32b 479 #define basename_ODY_DSUUBX_AMDEVARCH(a) "DSUUBX_AMDEVARCH" 480 #define device_bar_ODY_DSUUBX_AMDEVARCH(a) 0x0 /* PF_BAR0 */ 481 #define busnum_ODY_DSUUBX_AMDEVARCH(a) (a) 482 #define arguments_ODY_DSUUBX_AMDEVARCH(a) (a), -1, -1, -1 483 484 /** 485 * Register (RSL32b) dsuub#_amdevtype 486 * 487 * Dsuub Activity Monitors Device Type Register 488 * Indicates to a debugger that this component is part of a PE's performance monitor interface. 489 */ 490 union ody_dsuubx_amdevtype { 491 uint32_t u; 492 struct ody_dsuubx_amdevtype_s { 493 uint32_t major : 4; 494 uint32_t sub : 4; 495 uint32_t reserved_8_31 : 24; 496 } s; 497 /* struct ody_dsuubx_amdevtype_s cn; */ 498 }; 499 typedef union ody_dsuubx_amdevtype ody_dsuubx_amdevtype_t; 500 501 static inline uint64_t ODY_DSUUBX_AMDEVTYPE(uint64_t a) __attribute__ ((pure, always_inline)); 502 static inline uint64_t ODY_DSUUBX_AMDEVTYPE(uint64_t a) 503 { 504 if (a <= 89) 505 return 0x87e2ef090fccll + 0x1000000ll * ((a) & 0x7f); 506 __ody_csr_fatal("DSUUBX_AMDEVTYPE", 1, a, 0, 0, 0, 0, 0); 507 } 508 509 #define typedef_ODY_DSUUBX_AMDEVTYPE(a) ody_dsuubx_amdevtype_t 510 #define bustype_ODY_DSUUBX_AMDEVTYPE(a) CSR_TYPE_RSL32b 511 #define basename_ODY_DSUUBX_AMDEVTYPE(a) "DSUUBX_AMDEVTYPE" 512 #define device_bar_ODY_DSUUBX_AMDEVTYPE(a) 0x0 /* PF_BAR0 */ 513 #define busnum_ODY_DSUUBX_AMDEVTYPE(a) (a) 514 #define arguments_ODY_DSUUBX_AMDEVTYPE(a) (a), -1, -1, -1 515 516 /** 517 * Register (RSL) dsuub#_amevcntr00 518 * 519 * Dsuub Activity Monitors Event Type Registers 00 520 * Provides access to the architected activity monitor event counters. 521 */ 522 union ody_dsuubx_amevcntr00 { 523 uint64_t u; 524 struct ody_dsuubx_amevcntr00_s { 525 uint64_t acnt : 64; 526 } s; 527 /* struct ody_dsuubx_amevcntr00_s cn; */ 528 }; 529 typedef union ody_dsuubx_amevcntr00 ody_dsuubx_amevcntr00_t; 530 531 static inline uint64_t ODY_DSUUBX_AMEVCNTR00(uint64_t a) __attribute__ ((pure, always_inline)); 532 static inline uint64_t ODY_DSUUBX_AMEVCNTR00(uint64_t a) 533 { 534 if (a <= 89) 535 return 0x87e2ef090000ll + 0x1000000ll * ((a) & 0x7f); 536 __ody_csr_fatal("DSUUBX_AMEVCNTR00", 1, a, 0, 0, 0, 0, 0); 537 } 538 539 #define typedef_ODY_DSUUBX_AMEVCNTR00(a) ody_dsuubx_amevcntr00_t 540 #define bustype_ODY_DSUUBX_AMEVCNTR00(a) CSR_TYPE_RSL 541 #define basename_ODY_DSUUBX_AMEVCNTR00(a) "DSUUBX_AMEVCNTR00" 542 #define device_bar_ODY_DSUUBX_AMEVCNTR00(a) 0x0 /* PF_BAR0 */ 543 #define busnum_ODY_DSUUBX_AMEVCNTR00(a) (a) 544 #define arguments_ODY_DSUUBX_AMEVCNTR00(a) (a), -1, -1, -1 545 546 /** 547 * Register (RSL) dsuub#_amevcntr01 548 * 549 * Dsuub Activity Monitors Event Type Registers 01 550 * Provides access to the architected activity monitor event counters. 551 */ 552 union ody_dsuubx_amevcntr01 { 553 uint64_t u; 554 struct ody_dsuubx_amevcntr01_s { 555 uint64_t acnt : 64; 556 } s; 557 /* struct ody_dsuubx_amevcntr01_s cn; */ 558 }; 559 typedef union ody_dsuubx_amevcntr01 ody_dsuubx_amevcntr01_t; 560 561 static inline uint64_t ODY_DSUUBX_AMEVCNTR01(uint64_t a) __attribute__ ((pure, always_inline)); 562 static inline uint64_t ODY_DSUUBX_AMEVCNTR01(uint64_t a) 563 { 564 if (a <= 89) 565 return 0x87e2ef090008ll + 0x1000000ll * ((a) & 0x7f); 566 __ody_csr_fatal("DSUUBX_AMEVCNTR01", 1, a, 0, 0, 0, 0, 0); 567 } 568 569 #define typedef_ODY_DSUUBX_AMEVCNTR01(a) ody_dsuubx_amevcntr01_t 570 #define bustype_ODY_DSUUBX_AMEVCNTR01(a) CSR_TYPE_RSL 571 #define basename_ODY_DSUUBX_AMEVCNTR01(a) "DSUUBX_AMEVCNTR01" 572 #define device_bar_ODY_DSUUBX_AMEVCNTR01(a) 0x0 /* PF_BAR0 */ 573 #define busnum_ODY_DSUUBX_AMEVCNTR01(a) (a) 574 #define arguments_ODY_DSUUBX_AMEVCNTR01(a) (a), -1, -1, -1 575 576 /** 577 * Register (RSL) dsuub#_amevcntr02 578 * 579 * Dsuub Activity Monitors Event Type Registers 02 580 * Provides access to the architected activity monitor event counters. 581 */ 582 union ody_dsuubx_amevcntr02 { 583 uint64_t u; 584 struct ody_dsuubx_amevcntr02_s { 585 uint64_t acnt : 64; 586 } s; 587 /* struct ody_dsuubx_amevcntr02_s cn; */ 588 }; 589 typedef union ody_dsuubx_amevcntr02 ody_dsuubx_amevcntr02_t; 590 591 static inline uint64_t ODY_DSUUBX_AMEVCNTR02(uint64_t a) __attribute__ ((pure, always_inline)); 592 static inline uint64_t ODY_DSUUBX_AMEVCNTR02(uint64_t a) 593 { 594 if (a <= 89) 595 return 0x87e2ef090010ll + 0x1000000ll * ((a) & 0x7f); 596 __ody_csr_fatal("DSUUBX_AMEVCNTR02", 1, a, 0, 0, 0, 0, 0); 597 } 598 599 #define typedef_ODY_DSUUBX_AMEVCNTR02(a) ody_dsuubx_amevcntr02_t 600 #define bustype_ODY_DSUUBX_AMEVCNTR02(a) CSR_TYPE_RSL 601 #define basename_ODY_DSUUBX_AMEVCNTR02(a) "DSUUBX_AMEVCNTR02" 602 #define device_bar_ODY_DSUUBX_AMEVCNTR02(a) 0x0 /* PF_BAR0 */ 603 #define busnum_ODY_DSUUBX_AMEVCNTR02(a) (a) 604 #define arguments_ODY_DSUUBX_AMEVCNTR02(a) (a), -1, -1, -1 605 606 /** 607 * Register (RSL) dsuub#_amevcntr03 608 * 609 * Dsuub Activity Monitors Event Type Registers 03 610 * Provides access to the architected activity monitor event counters. 611 */ 612 union ody_dsuubx_amevcntr03 { 613 uint64_t u; 614 struct ody_dsuubx_amevcntr03_s { 615 uint64_t acnt : 64; 616 } s; 617 /* struct ody_dsuubx_amevcntr03_s cn; */ 618 }; 619 typedef union ody_dsuubx_amevcntr03 ody_dsuubx_amevcntr03_t; 620 621 static inline uint64_t ODY_DSUUBX_AMEVCNTR03(uint64_t a) __attribute__ ((pure, always_inline)); 622 static inline uint64_t ODY_DSUUBX_AMEVCNTR03(uint64_t a) 623 { 624 if (a <= 89) 625 return 0x87e2ef090018ll + 0x1000000ll * ((a) & 0x7f); 626 __ody_csr_fatal("DSUUBX_AMEVCNTR03", 1, a, 0, 0, 0, 0, 0); 627 } 628 629 #define typedef_ODY_DSUUBX_AMEVCNTR03(a) ody_dsuubx_amevcntr03_t 630 #define bustype_ODY_DSUUBX_AMEVCNTR03(a) CSR_TYPE_RSL 631 #define basename_ODY_DSUUBX_AMEVCNTR03(a) "DSUUBX_AMEVCNTR03" 632 #define device_bar_ODY_DSUUBX_AMEVCNTR03(a) 0x0 /* PF_BAR0 */ 633 #define busnum_ODY_DSUUBX_AMEVCNTR03(a) (a) 634 #define arguments_ODY_DSUUBX_AMEVCNTR03(a) (a), -1, -1, -1 635 636 /** 637 * Register (RSL) dsuub#_amevcntr10 638 * 639 * Dsuub Activity Monitors Event Type Registers 10 640 * Provides access to the auxiliary activity monitor event counters. 641 */ 642 union ody_dsuubx_amevcntr10 { 643 uint64_t u; 644 struct ody_dsuubx_amevcntr10_s { 645 uint64_t acnt : 64; 646 } s; 647 /* struct ody_dsuubx_amevcntr10_s cn; */ 648 }; 649 typedef union ody_dsuubx_amevcntr10 ody_dsuubx_amevcntr10_t; 650 651 static inline uint64_t ODY_DSUUBX_AMEVCNTR10(uint64_t a) __attribute__ ((pure, always_inline)); 652 static inline uint64_t ODY_DSUUBX_AMEVCNTR10(uint64_t a) 653 { 654 if (a <= 89) 655 return 0x87e2ef090100ll + 0x1000000ll * ((a) & 0x7f); 656 __ody_csr_fatal("DSUUBX_AMEVCNTR10", 1, a, 0, 0, 0, 0, 0); 657 } 658 659 #define typedef_ODY_DSUUBX_AMEVCNTR10(a) ody_dsuubx_amevcntr10_t 660 #define bustype_ODY_DSUUBX_AMEVCNTR10(a) CSR_TYPE_RSL 661 #define basename_ODY_DSUUBX_AMEVCNTR10(a) "DSUUBX_AMEVCNTR10" 662 #define device_bar_ODY_DSUUBX_AMEVCNTR10(a) 0x0 /* PF_BAR0 */ 663 #define busnum_ODY_DSUUBX_AMEVCNTR10(a) (a) 664 #define arguments_ODY_DSUUBX_AMEVCNTR10(a) (a), -1, -1, -1 665 666 /** 667 * Register (RSL) dsuub#_amevcntr11 668 * 669 * Dsuub Activity Monitors Event Type Registers 11 670 * Provides access to the auxiliary activity monitor event counters. 671 */ 672 union ody_dsuubx_amevcntr11 { 673 uint64_t u; 674 struct ody_dsuubx_amevcntr11_s { 675 uint64_t acnt : 64; 676 } s; 677 /* struct ody_dsuubx_amevcntr11_s cn; */ 678 }; 679 typedef union ody_dsuubx_amevcntr11 ody_dsuubx_amevcntr11_t; 680 681 static inline uint64_t ODY_DSUUBX_AMEVCNTR11(uint64_t a) __attribute__ ((pure, always_inline)); 682 static inline uint64_t ODY_DSUUBX_AMEVCNTR11(uint64_t a) 683 { 684 if (a <= 89) 685 return 0x87e2ef090108ll + 0x1000000ll * ((a) & 0x7f); 686 __ody_csr_fatal("DSUUBX_AMEVCNTR11", 1, a, 0, 0, 0, 0, 0); 687 } 688 689 #define typedef_ODY_DSUUBX_AMEVCNTR11(a) ody_dsuubx_amevcntr11_t 690 #define bustype_ODY_DSUUBX_AMEVCNTR11(a) CSR_TYPE_RSL 691 #define basename_ODY_DSUUBX_AMEVCNTR11(a) "DSUUBX_AMEVCNTR11" 692 #define device_bar_ODY_DSUUBX_AMEVCNTR11(a) 0x0 /* PF_BAR0 */ 693 #define busnum_ODY_DSUUBX_AMEVCNTR11(a) (a) 694 #define arguments_ODY_DSUUBX_AMEVCNTR11(a) (a), -1, -1, -1 695 696 /** 697 * Register (RSL) dsuub#_amevcntr12 698 * 699 * Dsuub Activity Monitors Event Type Registers 12 700 * Provides access to the auxiliary activity monitor event counters. 701 */ 702 union ody_dsuubx_amevcntr12 { 703 uint64_t u; 704 struct ody_dsuubx_amevcntr12_s { 705 uint64_t acnt : 64; 706 } s; 707 /* struct ody_dsuubx_amevcntr12_s cn; */ 708 }; 709 typedef union ody_dsuubx_amevcntr12 ody_dsuubx_amevcntr12_t; 710 711 static inline uint64_t ODY_DSUUBX_AMEVCNTR12(uint64_t a) __attribute__ ((pure, always_inline)); 712 static inline uint64_t ODY_DSUUBX_AMEVCNTR12(uint64_t a) 713 { 714 if (a <= 89) 715 return 0x87e2ef090110ll + 0x1000000ll * ((a) & 0x7f); 716 __ody_csr_fatal("DSUUBX_AMEVCNTR12", 1, a, 0, 0, 0, 0, 0); 717 } 718 719 #define typedef_ODY_DSUUBX_AMEVCNTR12(a) ody_dsuubx_amevcntr12_t 720 #define bustype_ODY_DSUUBX_AMEVCNTR12(a) CSR_TYPE_RSL 721 #define basename_ODY_DSUUBX_AMEVCNTR12(a) "DSUUBX_AMEVCNTR12" 722 #define device_bar_ODY_DSUUBX_AMEVCNTR12(a) 0x0 /* PF_BAR0 */ 723 #define busnum_ODY_DSUUBX_AMEVCNTR12(a) (a) 724 #define arguments_ODY_DSUUBX_AMEVCNTR12(a) (a), -1, -1, -1 725 726 /** 727 * Register (RSL32b) dsuub#_amevtyper00 728 * 729 * Dsuub Activity Monitors Event Type Registers 00 730 * Provides information on the events that an architected activity monitor event counter AArch64- 731 * AMEVCNTR00_EL0 counts. 732 */ 733 union ody_dsuubx_amevtyper00 { 734 uint32_t u; 735 struct ody_dsuubx_amevtyper00_s { 736 uint32_t evtcount : 16; 737 uint32_t reserved_16_31 : 16; 738 } s; 739 struct ody_dsuubx_amevtyper00_cn { 740 uint32_t evtcount : 16; 741 uint32_t reserved_16_24 : 9; 742 uint32_t reserved_25_31 : 7; 743 } cn; 744 }; 745 typedef union ody_dsuubx_amevtyper00 ody_dsuubx_amevtyper00_t; 746 747 static inline uint64_t ODY_DSUUBX_AMEVTYPER00(uint64_t a) __attribute__ ((pure, always_inline)); 748 static inline uint64_t ODY_DSUUBX_AMEVTYPER00(uint64_t a) 749 { 750 if (a <= 89) 751 return 0x87e2ef090400ll + 0x1000000ll * ((a) & 0x7f); 752 __ody_csr_fatal("DSUUBX_AMEVTYPER00", 1, a, 0, 0, 0, 0, 0); 753 } 754 755 #define typedef_ODY_DSUUBX_AMEVTYPER00(a) ody_dsuubx_amevtyper00_t 756 #define bustype_ODY_DSUUBX_AMEVTYPER00(a) CSR_TYPE_RSL32b 757 #define basename_ODY_DSUUBX_AMEVTYPER00(a) "DSUUBX_AMEVTYPER00" 758 #define device_bar_ODY_DSUUBX_AMEVTYPER00(a) 0x0 /* PF_BAR0 */ 759 #define busnum_ODY_DSUUBX_AMEVTYPER00(a) (a) 760 #define arguments_ODY_DSUUBX_AMEVTYPER00(a) (a), -1, -1, -1 761 762 /** 763 * Register (RSL32b) dsuub#_amevtyper01 764 * 765 * Dsuub Activity Monitors Event Type Registers 01 766 * Provides information on the events that an architected activity monitor event counter AArch64- 767 * AMEVCNTR01_EL0 counts. 768 */ 769 union ody_dsuubx_amevtyper01 { 770 uint32_t u; 771 struct ody_dsuubx_amevtyper01_s { 772 uint32_t evtcount : 16; 773 uint32_t reserved_16_31 : 16; 774 } s; 775 struct ody_dsuubx_amevtyper01_cn { 776 uint32_t evtcount : 16; 777 uint32_t reserved_16_24 : 9; 778 uint32_t reserved_25_31 : 7; 779 } cn; 780 }; 781 typedef union ody_dsuubx_amevtyper01 ody_dsuubx_amevtyper01_t; 782 783 static inline uint64_t ODY_DSUUBX_AMEVTYPER01(uint64_t a) __attribute__ ((pure, always_inline)); 784 static inline uint64_t ODY_DSUUBX_AMEVTYPER01(uint64_t a) 785 { 786 if (a <= 89) 787 return 0x87e2ef090404ll + 0x1000000ll * ((a) & 0x7f); 788 __ody_csr_fatal("DSUUBX_AMEVTYPER01", 1, a, 0, 0, 0, 0, 0); 789 } 790 791 #define typedef_ODY_DSUUBX_AMEVTYPER01(a) ody_dsuubx_amevtyper01_t 792 #define bustype_ODY_DSUUBX_AMEVTYPER01(a) CSR_TYPE_RSL32b 793 #define basename_ODY_DSUUBX_AMEVTYPER01(a) "DSUUBX_AMEVTYPER01" 794 #define device_bar_ODY_DSUUBX_AMEVTYPER01(a) 0x0 /* PF_BAR0 */ 795 #define busnum_ODY_DSUUBX_AMEVTYPER01(a) (a) 796 #define arguments_ODY_DSUUBX_AMEVTYPER01(a) (a), -1, -1, -1 797 798 /** 799 * Register (RSL32b) dsuub#_amevtyper02 800 * 801 * Dsuub Activity Monitors Event Type Registers 02 802 * Provides information on the events that an architected activity monitor event counter AArch64- 803 * AMEVCNTR02_EL0 counts. 804 */ 805 union ody_dsuubx_amevtyper02 { 806 uint32_t u; 807 struct ody_dsuubx_amevtyper02_s { 808 uint32_t evtcount : 16; 809 uint32_t reserved_16_31 : 16; 810 } s; 811 struct ody_dsuubx_amevtyper02_cn { 812 uint32_t evtcount : 16; 813 uint32_t reserved_16_24 : 9; 814 uint32_t reserved_25_31 : 7; 815 } cn; 816 }; 817 typedef union ody_dsuubx_amevtyper02 ody_dsuubx_amevtyper02_t; 818 819 static inline uint64_t ODY_DSUUBX_AMEVTYPER02(uint64_t a) __attribute__ ((pure, always_inline)); 820 static inline uint64_t ODY_DSUUBX_AMEVTYPER02(uint64_t a) 821 { 822 if (a <= 89) 823 return 0x87e2ef090408ll + 0x1000000ll * ((a) & 0x7f); 824 __ody_csr_fatal("DSUUBX_AMEVTYPER02", 1, a, 0, 0, 0, 0, 0); 825 } 826 827 #define typedef_ODY_DSUUBX_AMEVTYPER02(a) ody_dsuubx_amevtyper02_t 828 #define bustype_ODY_DSUUBX_AMEVTYPER02(a) CSR_TYPE_RSL32b 829 #define basename_ODY_DSUUBX_AMEVTYPER02(a) "DSUUBX_AMEVTYPER02" 830 #define device_bar_ODY_DSUUBX_AMEVTYPER02(a) 0x0 /* PF_BAR0 */ 831 #define busnum_ODY_DSUUBX_AMEVTYPER02(a) (a) 832 #define arguments_ODY_DSUUBX_AMEVTYPER02(a) (a), -1, -1, -1 833 834 /** 835 * Register (RSL32b) dsuub#_amevtyper03 836 * 837 * Dsuub Activity Monitors Event Type Registers 03 838 * Provides information on the events that an architected activity monitor event counter AArch64- 839 * AMEVCNTR03_EL0 counts. 840 */ 841 union ody_dsuubx_amevtyper03 { 842 uint32_t u; 843 struct ody_dsuubx_amevtyper03_s { 844 uint32_t evtcount : 16; 845 uint32_t reserved_16_31 : 16; 846 } s; 847 struct ody_dsuubx_amevtyper03_cn { 848 uint32_t evtcount : 16; 849 uint32_t reserved_16_24 : 9; 850 uint32_t reserved_25_31 : 7; 851 } cn; 852 }; 853 typedef union ody_dsuubx_amevtyper03 ody_dsuubx_amevtyper03_t; 854 855 static inline uint64_t ODY_DSUUBX_AMEVTYPER03(uint64_t a) __attribute__ ((pure, always_inline)); 856 static inline uint64_t ODY_DSUUBX_AMEVTYPER03(uint64_t a) 857 { 858 if (a <= 89) 859 return 0x87e2ef09040cll + 0x1000000ll * ((a) & 0x7f); 860 __ody_csr_fatal("DSUUBX_AMEVTYPER03", 1, a, 0, 0, 0, 0, 0); 861 } 862 863 #define typedef_ODY_DSUUBX_AMEVTYPER03(a) ody_dsuubx_amevtyper03_t 864 #define bustype_ODY_DSUUBX_AMEVTYPER03(a) CSR_TYPE_RSL32b 865 #define basename_ODY_DSUUBX_AMEVTYPER03(a) "DSUUBX_AMEVTYPER03" 866 #define device_bar_ODY_DSUUBX_AMEVTYPER03(a) 0x0 /* PF_BAR0 */ 867 #define busnum_ODY_DSUUBX_AMEVTYPER03(a) (a) 868 #define arguments_ODY_DSUUBX_AMEVTYPER03(a) (a), -1, -1, -1 869 870 /** 871 * Register (RSL32b) dsuub#_amevtyper10 872 * 873 * Dsuub Activity Monitors Event Type Registers 10 874 * Provides information on the events that an architected activity monitor event counter AArch64- 875 * AMEVCNTR10_EL0 counts. 876 */ 877 union ody_dsuubx_amevtyper10 { 878 uint32_t u; 879 struct ody_dsuubx_amevtyper10_s { 880 uint32_t evtcount : 16; 881 uint32_t reserved_16_31 : 16; 882 } s; 883 struct ody_dsuubx_amevtyper10_cn { 884 uint32_t evtcount : 16; 885 uint32_t reserved_16_24 : 9; 886 uint32_t reserved_25_31 : 7; 887 } cn; 888 }; 889 typedef union ody_dsuubx_amevtyper10 ody_dsuubx_amevtyper10_t; 890 891 static inline uint64_t ODY_DSUUBX_AMEVTYPER10(uint64_t a) __attribute__ ((pure, always_inline)); 892 static inline uint64_t ODY_DSUUBX_AMEVTYPER10(uint64_t a) 893 { 894 if (a <= 89) 895 return 0x87e2ef090480ll + 0x1000000ll * ((a) & 0x7f); 896 __ody_csr_fatal("DSUUBX_AMEVTYPER10", 1, a, 0, 0, 0, 0, 0); 897 } 898 899 #define typedef_ODY_DSUUBX_AMEVTYPER10(a) ody_dsuubx_amevtyper10_t 900 #define bustype_ODY_DSUUBX_AMEVTYPER10(a) CSR_TYPE_RSL32b 901 #define basename_ODY_DSUUBX_AMEVTYPER10(a) "DSUUBX_AMEVTYPER10" 902 #define device_bar_ODY_DSUUBX_AMEVTYPER10(a) 0x0 /* PF_BAR0 */ 903 #define busnum_ODY_DSUUBX_AMEVTYPER10(a) (a) 904 #define arguments_ODY_DSUUBX_AMEVTYPER10(a) (a), -1, -1, -1 905 906 /** 907 * Register (RSL32b) dsuub#_amevtyper11 908 * 909 * Dsuub Activity Monitors Event Type Registers 11 910 * Provides information on the events that an architected activity monitor event counter AArch64- 911 * AMEVCNTR11_EL0 counts. 912 */ 913 union ody_dsuubx_amevtyper11 { 914 uint32_t u; 915 struct ody_dsuubx_amevtyper11_s { 916 uint32_t evtcount : 16; 917 uint32_t reserved_16_31 : 16; 918 } s; 919 struct ody_dsuubx_amevtyper11_cn { 920 uint32_t evtcount : 16; 921 uint32_t reserved_16_24 : 9; 922 uint32_t reserved_25_31 : 7; 923 } cn; 924 }; 925 typedef union ody_dsuubx_amevtyper11 ody_dsuubx_amevtyper11_t; 926 927 static inline uint64_t ODY_DSUUBX_AMEVTYPER11(uint64_t a) __attribute__ ((pure, always_inline)); 928 static inline uint64_t ODY_DSUUBX_AMEVTYPER11(uint64_t a) 929 { 930 if (a <= 89) 931 return 0x87e2ef090484ll + 0x1000000ll * ((a) & 0x7f); 932 __ody_csr_fatal("DSUUBX_AMEVTYPER11", 1, a, 0, 0, 0, 0, 0); 933 } 934 935 #define typedef_ODY_DSUUBX_AMEVTYPER11(a) ody_dsuubx_amevtyper11_t 936 #define bustype_ODY_DSUUBX_AMEVTYPER11(a) CSR_TYPE_RSL32b 937 #define basename_ODY_DSUUBX_AMEVTYPER11(a) "DSUUBX_AMEVTYPER11" 938 #define device_bar_ODY_DSUUBX_AMEVTYPER11(a) 0x0 /* PF_BAR0 */ 939 #define busnum_ODY_DSUUBX_AMEVTYPER11(a) (a) 940 #define arguments_ODY_DSUUBX_AMEVTYPER11(a) (a), -1, -1, -1 941 942 /** 943 * Register (RSL32b) dsuub#_amevtyper12 944 * 945 * Dsuub Activity Monitors Event Type Registers 12 946 * Provides information on the events that an architected activity monitor event counter AArch64- 947 * AMEVCNTR12_EL0 counts. 948 */ 949 union ody_dsuubx_amevtyper12 { 950 uint32_t u; 951 struct ody_dsuubx_amevtyper12_s { 952 uint32_t evtcount : 16; 953 uint32_t reserved_16_31 : 16; 954 } s; 955 struct ody_dsuubx_amevtyper12_cn { 956 uint32_t evtcount : 16; 957 uint32_t reserved_16_24 : 9; 958 uint32_t reserved_25_31 : 7; 959 } cn; 960 }; 961 typedef union ody_dsuubx_amevtyper12 ody_dsuubx_amevtyper12_t; 962 963 static inline uint64_t ODY_DSUUBX_AMEVTYPER12(uint64_t a) __attribute__ ((pure, always_inline)); 964 static inline uint64_t ODY_DSUUBX_AMEVTYPER12(uint64_t a) 965 { 966 if (a <= 89) 967 return 0x87e2ef090488ll + 0x1000000ll * ((a) & 0x7f); 968 __ody_csr_fatal("DSUUBX_AMEVTYPER12", 1, a, 0, 0, 0, 0, 0); 969 } 970 971 #define typedef_ODY_DSUUBX_AMEVTYPER12(a) ody_dsuubx_amevtyper12_t 972 #define bustype_ODY_DSUUBX_AMEVTYPER12(a) CSR_TYPE_RSL32b 973 #define basename_ODY_DSUUBX_AMEVTYPER12(a) "DSUUBX_AMEVTYPER12" 974 #define device_bar_ODY_DSUUBX_AMEVTYPER12(a) 0x0 /* PF_BAR0 */ 975 #define busnum_ODY_DSUUBX_AMEVTYPER12(a) (a) 976 #define arguments_ODY_DSUUBX_AMEVTYPER12(a) (a), -1, -1, -1 977 978 /** 979 * Register (RSL32b) dsuub#_amiidr 980 * 981 * Dsuub Activity Monitors Implementation Identification Register 982 * Defines the implementer and revisions of the AMU. 983 */ 984 union ody_dsuubx_amiidr { 985 uint32_t u; 986 struct ody_dsuubx_amiidr_s { 987 uint32_t implementer : 12; 988 uint32_t revision : 4; 989 uint32_t variant : 4; 990 uint32_t productid : 12; 991 } s; 992 /* struct ody_dsuubx_amiidr_s cn; */ 993 }; 994 typedef union ody_dsuubx_amiidr ody_dsuubx_amiidr_t; 995 996 static inline uint64_t ODY_DSUUBX_AMIIDR(uint64_t a) __attribute__ ((pure, always_inline)); 997 static inline uint64_t ODY_DSUUBX_AMIIDR(uint64_t a) 998 { 999 if (a <= 89) 1000 return 0x87e2ef090e08ll + 0x1000000ll * ((a) & 0x7f); 1001 __ody_csr_fatal("DSUUBX_AMIIDR", 1, a, 0, 0, 0, 0, 0); 1002 } 1003 1004 #define typedef_ODY_DSUUBX_AMIIDR(a) ody_dsuubx_amiidr_t 1005 #define bustype_ODY_DSUUBX_AMIIDR(a) CSR_TYPE_RSL32b 1006 #define basename_ODY_DSUUBX_AMIIDR(a) "DSUUBX_AMIIDR" 1007 #define device_bar_ODY_DSUUBX_AMIIDR(a) 0x0 /* PF_BAR0 */ 1008 #define busnum_ODY_DSUUBX_AMIIDR(a) (a) 1009 #define arguments_ODY_DSUUBX_AMIIDR(a) (a), -1, -1, -1 1010 1011 /** 1012 * Register (RSL32b) dsuub#_ampidr0 1013 * 1014 * Dsuub Activity Monitors Peripheral Identification Register 0 1015 * Provides information to identify an activity monitors component. 1016 * 1017 * For more information, see 'About the Peripheral identification scheme'. 1018 */ 1019 union ody_dsuubx_ampidr0 { 1020 uint32_t u; 1021 struct ody_dsuubx_ampidr0_s { 1022 uint32_t part_0 : 8; 1023 uint32_t reserved_8_31 : 24; 1024 } s; 1025 /* struct ody_dsuubx_ampidr0_s cn; */ 1026 }; 1027 typedef union ody_dsuubx_ampidr0 ody_dsuubx_ampidr0_t; 1028 1029 static inline uint64_t ODY_DSUUBX_AMPIDR0(uint64_t a) __attribute__ ((pure, always_inline)); 1030 static inline uint64_t ODY_DSUUBX_AMPIDR0(uint64_t a) 1031 { 1032 if (a <= 89) 1033 return 0x87e2ef090fe0ll + 0x1000000ll * ((a) & 0x7f); 1034 __ody_csr_fatal("DSUUBX_AMPIDR0", 1, a, 0, 0, 0, 0, 0); 1035 } 1036 1037 #define typedef_ODY_DSUUBX_AMPIDR0(a) ody_dsuubx_ampidr0_t 1038 #define bustype_ODY_DSUUBX_AMPIDR0(a) CSR_TYPE_RSL32b 1039 #define basename_ODY_DSUUBX_AMPIDR0(a) "DSUUBX_AMPIDR0" 1040 #define device_bar_ODY_DSUUBX_AMPIDR0(a) 0x0 /* PF_BAR0 */ 1041 #define busnum_ODY_DSUUBX_AMPIDR0(a) (a) 1042 #define arguments_ODY_DSUUBX_AMPIDR0(a) (a), -1, -1, -1 1043 1044 /** 1045 * Register (RSL32b) dsuub#_ampidr1 1046 * 1047 * Dsuub Activity Monitors Peripheral Identification Register 1 1048 * Provides information to identify an activity monitors component. 1049 * 1050 * For more information, see 'About the Peripheral identification scheme'. 1051 */ 1052 union ody_dsuubx_ampidr1 { 1053 uint32_t u; 1054 struct ody_dsuubx_ampidr1_s { 1055 uint32_t part_1 : 4; 1056 uint32_t des_0 : 4; 1057 uint32_t reserved_8_31 : 24; 1058 } s; 1059 /* struct ody_dsuubx_ampidr1_s cn; */ 1060 }; 1061 typedef union ody_dsuubx_ampidr1 ody_dsuubx_ampidr1_t; 1062 1063 static inline uint64_t ODY_DSUUBX_AMPIDR1(uint64_t a) __attribute__ ((pure, always_inline)); 1064 static inline uint64_t ODY_DSUUBX_AMPIDR1(uint64_t a) 1065 { 1066 if (a <= 89) 1067 return 0x87e2ef090fe4ll + 0x1000000ll * ((a) & 0x7f); 1068 __ody_csr_fatal("DSUUBX_AMPIDR1", 1, a, 0, 0, 0, 0, 0); 1069 } 1070 1071 #define typedef_ODY_DSUUBX_AMPIDR1(a) ody_dsuubx_ampidr1_t 1072 #define bustype_ODY_DSUUBX_AMPIDR1(a) CSR_TYPE_RSL32b 1073 #define basename_ODY_DSUUBX_AMPIDR1(a) "DSUUBX_AMPIDR1" 1074 #define device_bar_ODY_DSUUBX_AMPIDR1(a) 0x0 /* PF_BAR0 */ 1075 #define busnum_ODY_DSUUBX_AMPIDR1(a) (a) 1076 #define arguments_ODY_DSUUBX_AMPIDR1(a) (a), -1, -1, -1 1077 1078 /** 1079 * Register (RSL32b) dsuub#_ampidr2 1080 * 1081 * Dsuub Activity Monitors Peripheral Identification Register 2 1082 * Provides information to identify an activity monitors component. 1083 * 1084 * For more information, see 'About the Peripheral identification scheme'. 1085 */ 1086 union ody_dsuubx_ampidr2 { 1087 uint32_t u; 1088 struct ody_dsuubx_ampidr2_s { 1089 uint32_t des_1 : 3; 1090 uint32_t jedec : 1; 1091 uint32_t revision : 4; 1092 uint32_t reserved_8_31 : 24; 1093 } s; 1094 /* struct ody_dsuubx_ampidr2_s cn; */ 1095 }; 1096 typedef union ody_dsuubx_ampidr2 ody_dsuubx_ampidr2_t; 1097 1098 static inline uint64_t ODY_DSUUBX_AMPIDR2(uint64_t a) __attribute__ ((pure, always_inline)); 1099 static inline uint64_t ODY_DSUUBX_AMPIDR2(uint64_t a) 1100 { 1101 if (a <= 89) 1102 return 0x87e2ef090fe8ll + 0x1000000ll * ((a) & 0x7f); 1103 __ody_csr_fatal("DSUUBX_AMPIDR2", 1, a, 0, 0, 0, 0, 0); 1104 } 1105 1106 #define typedef_ODY_DSUUBX_AMPIDR2(a) ody_dsuubx_ampidr2_t 1107 #define bustype_ODY_DSUUBX_AMPIDR2(a) CSR_TYPE_RSL32b 1108 #define basename_ODY_DSUUBX_AMPIDR2(a) "DSUUBX_AMPIDR2" 1109 #define device_bar_ODY_DSUUBX_AMPIDR2(a) 0x0 /* PF_BAR0 */ 1110 #define busnum_ODY_DSUUBX_AMPIDR2(a) (a) 1111 #define arguments_ODY_DSUUBX_AMPIDR2(a) (a), -1, -1, -1 1112 1113 /** 1114 * Register (RSL32b) dsuub#_ampidr3 1115 * 1116 * Dsuub Activity Monitors Peripheral Identification Register 3 1117 * Provides information to identify an activity monitors component. 1118 * 1119 * For more information, see 'About the Peripheral identification scheme'. 1120 */ 1121 union ody_dsuubx_ampidr3 { 1122 uint32_t u; 1123 struct ody_dsuubx_ampidr3_s { 1124 uint32_t cmod : 4; 1125 uint32_t revand : 4; 1126 uint32_t reserved_8_31 : 24; 1127 } s; 1128 /* struct ody_dsuubx_ampidr3_s cn; */ 1129 }; 1130 typedef union ody_dsuubx_ampidr3 ody_dsuubx_ampidr3_t; 1131 1132 static inline uint64_t ODY_DSUUBX_AMPIDR3(uint64_t a) __attribute__ ((pure, always_inline)); 1133 static inline uint64_t ODY_DSUUBX_AMPIDR3(uint64_t a) 1134 { 1135 if (a <= 89) 1136 return 0x87e2ef090fecll + 0x1000000ll * ((a) & 0x7f); 1137 __ody_csr_fatal("DSUUBX_AMPIDR3", 1, a, 0, 0, 0, 0, 0); 1138 } 1139 1140 #define typedef_ODY_DSUUBX_AMPIDR3(a) ody_dsuubx_ampidr3_t 1141 #define bustype_ODY_DSUUBX_AMPIDR3(a) CSR_TYPE_RSL32b 1142 #define basename_ODY_DSUUBX_AMPIDR3(a) "DSUUBX_AMPIDR3" 1143 #define device_bar_ODY_DSUUBX_AMPIDR3(a) 0x0 /* PF_BAR0 */ 1144 #define busnum_ODY_DSUUBX_AMPIDR3(a) (a) 1145 #define arguments_ODY_DSUUBX_AMPIDR3(a) (a), -1, -1, -1 1146 1147 /** 1148 * Register (RSL32b) dsuub#_ampidr4 1149 * 1150 * Dsuub Activity Monitors Peripheral Identification Register 4 1151 * Provides information to identify an activity monitors component. 1152 * 1153 * For more information, see 'About the Peripheral identification scheme'. 1154 */ 1155 union ody_dsuubx_ampidr4 { 1156 uint32_t u; 1157 struct ody_dsuubx_ampidr4_s { 1158 uint32_t des_2 : 4; 1159 uint32_t size : 4; 1160 uint32_t reserved_8_31 : 24; 1161 } s; 1162 /* struct ody_dsuubx_ampidr4_s cn; */ 1163 }; 1164 typedef union ody_dsuubx_ampidr4 ody_dsuubx_ampidr4_t; 1165 1166 static inline uint64_t ODY_DSUUBX_AMPIDR4(uint64_t a) __attribute__ ((pure, always_inline)); 1167 static inline uint64_t ODY_DSUUBX_AMPIDR4(uint64_t a) 1168 { 1169 if (a <= 89) 1170 return 0x87e2ef090fd0ll + 0x1000000ll * ((a) & 0x7f); 1171 __ody_csr_fatal("DSUUBX_AMPIDR4", 1, a, 0, 0, 0, 0, 0); 1172 } 1173 1174 #define typedef_ODY_DSUUBX_AMPIDR4(a) ody_dsuubx_ampidr4_t 1175 #define bustype_ODY_DSUUBX_AMPIDR4(a) CSR_TYPE_RSL32b 1176 #define basename_ODY_DSUUBX_AMPIDR4(a) "DSUUBX_AMPIDR4" 1177 #define device_bar_ODY_DSUUBX_AMPIDR4(a) 0x0 /* PF_BAR0 */ 1178 #define busnum_ODY_DSUUBX_AMPIDR4(a) (a) 1179 #define arguments_ODY_DSUUBX_AMPIDR4(a) (a), -1, -1, -1 1180 1181 /** 1182 * Register (RSL32b) dsuub#_cluster_ppu_aidr 1183 * 1184 * DSUUB Cluster Architecture Identification Register 1185 * This register identifies the PPU architecture revision. 1186 */ 1187 union ody_dsuubx_cluster_ppu_aidr { 1188 uint32_t u; 1189 struct ody_dsuubx_cluster_ppu_aidr_s { 1190 uint32_t arch_rev_minor : 4; 1191 uint32_t arch_rev_major : 4; 1192 uint32_t reserved_8_31 : 24; 1193 } s; 1194 /* struct ody_dsuubx_cluster_ppu_aidr_s cn; */ 1195 }; 1196 typedef union ody_dsuubx_cluster_ppu_aidr ody_dsuubx_cluster_ppu_aidr_t; 1197 1198 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_AIDR(uint64_t a) __attribute__ ((pure, always_inline)); 1199 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_AIDR(uint64_t a) 1200 { 1201 if (a <= 89) 1202 return 0x87e2ef030fccll + 0x1000000ll * ((a) & 0x7f); 1203 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_AIDR", 1, a, 0, 0, 0, 0, 0); 1204 } 1205 1206 #define typedef_ODY_DSUUBX_CLUSTER_PPU_AIDR(a) ody_dsuubx_cluster_ppu_aidr_t 1207 #define bustype_ODY_DSUUBX_CLUSTER_PPU_AIDR(a) CSR_TYPE_RSL32b 1208 #define basename_ODY_DSUUBX_CLUSTER_PPU_AIDR(a) "DSUUBX_CLUSTER_PPU_AIDR" 1209 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_AIDR(a) 0x0 /* PF_BAR0 */ 1210 #define busnum_ODY_DSUUBX_CLUSTER_PPU_AIDR(a) (a) 1211 #define arguments_ODY_DSUUBX_CLUSTER_PPU_AIDR(a) (a), -1, -1, -1 1212 1213 /** 1214 * Register (RSL32b) dsuub#_cluster_ppu_aimr 1215 * 1216 * DSUUB Cluster Additional Interrupt Mask Register 1217 * This register controls the events that assert the interrupt output. Additional event 1218 * masking controls 1219 * are in the Interrupt Mask Register (DSUUB_PPU_IMR), Input Edge Sensitivity Register 1220 * (DSUUB_PPU_IESR), 1221 * and the Operating Mode Active Edge Sensitivity Register (DSUUB_PPU_OPSR). 1222 * 1223 * When an interrupt event is masked an occurrence of the event does not set the corresponding bit 1224 * in the interrupt status register. 1225 */ 1226 union ody_dsuubx_cluster_ppu_aimr { 1227 uint32_t u; 1228 struct ody_dsuubx_cluster_ppu_aimr_s { 1229 uint32_t unspt_policy_irq_mask : 1; 1230 uint32_t dyn_accept_irq_mask : 1; 1231 uint32_t dyn_deny_irq_mask : 1; 1232 uint32_t sta_policy_pwr_irq_mask : 1; 1233 uint32_t sta_policy_op_irq_mask : 1; 1234 uint32_t reserved_5_31 : 27; 1235 } s; 1236 /* struct ody_dsuubx_cluster_ppu_aimr_s cn; */ 1237 }; 1238 typedef union ody_dsuubx_cluster_ppu_aimr ody_dsuubx_cluster_ppu_aimr_t; 1239 1240 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_AIMR(uint64_t a) __attribute__ ((pure, always_inline)); 1241 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_AIMR(uint64_t a) 1242 { 1243 if (a <= 89) 1244 return 0x87e2ef030034ll + 0x1000000ll * ((a) & 0x7f); 1245 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_AIMR", 1, a, 0, 0, 0, 0, 0); 1246 } 1247 1248 #define typedef_ODY_DSUUBX_CLUSTER_PPU_AIMR(a) ody_dsuubx_cluster_ppu_aimr_t 1249 #define bustype_ODY_DSUUBX_CLUSTER_PPU_AIMR(a) CSR_TYPE_RSL32b 1250 #define basename_ODY_DSUUBX_CLUSTER_PPU_AIMR(a) "DSUUBX_CLUSTER_PPU_AIMR" 1251 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_AIMR(a) 0x0 /* PF_BAR0 */ 1252 #define busnum_ODY_DSUUBX_CLUSTER_PPU_AIMR(a) (a) 1253 #define arguments_ODY_DSUUBX_CLUSTER_PPU_AIMR(a) (a), -1, -1, -1 1254 1255 /** 1256 * Register (RSL32b) dsuub#_cluster_ppu_aisr 1257 * 1258 * DSUUB Cluster Additional Interrupt Status Register 1259 * This register contains information about events causing the assertion of the 1260 * interrupt output. It is 1261 * also used to clear interrupt events. 1262 * 1263 * A bit set to 1 indicates the event asserted the interrupt output. Multiple events 1264 * can be active at 1265 * the same time. When an interrupt event is masked an occurrence of that event does not set the 1266 * status bit. 1267 * A write of 1 to an event bit clears that event. A write of 0 has no effect. The 1268 * interrupt output 1269 * stays HIGH until all status bits in the Interrupt Status Register (DSUUB_PPU_ISR) 1270 * and the Additional 1271 * Interrupt Status Register (PPU_AISR) are set to 0b0. 1272 * 1273 * When an interrupt status is set to 1 in this register it sets the OTHER_IRQ bit in the Interrupt 1274 * Status Register (DSUUB_PPU_ISR). Status bits in this register are only cleared by 1275 * writing to this register. 1276 */ 1277 union ody_dsuubx_cluster_ppu_aisr { 1278 uint32_t u; 1279 struct ody_dsuubx_cluster_ppu_aisr_s { 1280 uint32_t unspt_policy_irq : 1; 1281 uint32_t dyn_accept_irq : 1; 1282 uint32_t dyn_deny_irq : 1; 1283 uint32_t sta_policy_pwr_irq : 1; 1284 uint32_t sta_policy_op_irq : 1; 1285 uint32_t reserved_5_31 : 27; 1286 } s; 1287 /* struct ody_dsuubx_cluster_ppu_aisr_s cn; */ 1288 }; 1289 typedef union ody_dsuubx_cluster_ppu_aisr ody_dsuubx_cluster_ppu_aisr_t; 1290 1291 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_AISR(uint64_t a) __attribute__ ((pure, always_inline)); 1292 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_AISR(uint64_t a) 1293 { 1294 if (a <= 89) 1295 return 0x87e2ef03003cll + 0x1000000ll * ((a) & 0x7f); 1296 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_AISR", 1, a, 0, 0, 0, 0, 0); 1297 } 1298 1299 #define typedef_ODY_DSUUBX_CLUSTER_PPU_AISR(a) ody_dsuubx_cluster_ppu_aisr_t 1300 #define bustype_ODY_DSUUBX_CLUSTER_PPU_AISR(a) CSR_TYPE_RSL32b 1301 #define basename_ODY_DSUUBX_CLUSTER_PPU_AISR(a) "DSUUBX_CLUSTER_PPU_AISR" 1302 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_AISR(a) 0x0 /* PF_BAR0 */ 1303 #define busnum_ODY_DSUUBX_CLUSTER_PPU_AISR(a) (a) 1304 #define arguments_ODY_DSUUBX_CLUSTER_PPU_AISR(a) (a), -1, -1, -1 1305 1306 /** 1307 * Register (RSL32b) dsuub#_cluster_ppu_cidr0 1308 * 1309 * DSUUB Cluster PPU Component Identification Register 0 1310 * Provides CoreSight discovery information. 1311 */ 1312 union ody_dsuubx_cluster_ppu_cidr0 { 1313 uint32_t u; 1314 struct ody_dsuubx_cluster_ppu_cidr0_s { 1315 uint32_t prmbl_0 : 8; 1316 uint32_t reserved_8_31 : 24; 1317 } s; 1318 /* struct ody_dsuubx_cluster_ppu_cidr0_s cn; */ 1319 }; 1320 typedef union ody_dsuubx_cluster_ppu_cidr0 ody_dsuubx_cluster_ppu_cidr0_t; 1321 1322 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_CIDR0(uint64_t a) __attribute__ ((pure, always_inline)); 1323 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_CIDR0(uint64_t a) 1324 { 1325 if (a <= 89) 1326 return 0x87e2ef030ff0ll + 0x1000000ll * ((a) & 0x7f); 1327 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_CIDR0", 1, a, 0, 0, 0, 0, 0); 1328 } 1329 1330 #define typedef_ODY_DSUUBX_CLUSTER_PPU_CIDR0(a) ody_dsuubx_cluster_ppu_cidr0_t 1331 #define bustype_ODY_DSUUBX_CLUSTER_PPU_CIDR0(a) CSR_TYPE_RSL32b 1332 #define basename_ODY_DSUUBX_CLUSTER_PPU_CIDR0(a) "DSUUBX_CLUSTER_PPU_CIDR0" 1333 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_CIDR0(a) 0x0 /* PF_BAR0 */ 1334 #define busnum_ODY_DSUUBX_CLUSTER_PPU_CIDR0(a) (a) 1335 #define arguments_ODY_DSUUBX_CLUSTER_PPU_CIDR0(a) (a), -1, -1, -1 1336 1337 /** 1338 * Register (RSL32b) dsuub#_cluster_ppu_cidr1 1339 * 1340 * DSUUB Cluster PPU Component Identification Register 1 1341 * Provides CoreSight discovery information. 1342 */ 1343 union ody_dsuubx_cluster_ppu_cidr1 { 1344 uint32_t u; 1345 struct ody_dsuubx_cluster_ppu_cidr1_s { 1346 uint32_t prmbl_1 : 4; 1347 uint32_t clas : 4; 1348 uint32_t reserved_8_31 : 24; 1349 } s; 1350 /* struct ody_dsuubx_cluster_ppu_cidr1_s cn; */ 1351 }; 1352 typedef union ody_dsuubx_cluster_ppu_cidr1 ody_dsuubx_cluster_ppu_cidr1_t; 1353 1354 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_CIDR1(uint64_t a) __attribute__ ((pure, always_inline)); 1355 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_CIDR1(uint64_t a) 1356 { 1357 if (a <= 89) 1358 return 0x87e2ef030ff4ll + 0x1000000ll * ((a) & 0x7f); 1359 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_CIDR1", 1, a, 0, 0, 0, 0, 0); 1360 } 1361 1362 #define typedef_ODY_DSUUBX_CLUSTER_PPU_CIDR1(a) ody_dsuubx_cluster_ppu_cidr1_t 1363 #define bustype_ODY_DSUUBX_CLUSTER_PPU_CIDR1(a) CSR_TYPE_RSL32b 1364 #define basename_ODY_DSUUBX_CLUSTER_PPU_CIDR1(a) "DSUUBX_CLUSTER_PPU_CIDR1" 1365 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_CIDR1(a) 0x0 /* PF_BAR0 */ 1366 #define busnum_ODY_DSUUBX_CLUSTER_PPU_CIDR1(a) (a) 1367 #define arguments_ODY_DSUUBX_CLUSTER_PPU_CIDR1(a) (a), -1, -1, -1 1368 1369 /** 1370 * Register (RSL32b) dsuub#_cluster_ppu_cidr2 1371 * 1372 * DSUUB Cluster PPU Component Identification Register 2 1373 * Provides CoreSight discovery information. 1374 */ 1375 union ody_dsuubx_cluster_ppu_cidr2 { 1376 uint32_t u; 1377 struct ody_dsuubx_cluster_ppu_cidr2_s { 1378 uint32_t prmbl_2 : 8; 1379 uint32_t reserved_8_31 : 24; 1380 } s; 1381 /* struct ody_dsuubx_cluster_ppu_cidr2_s cn; */ 1382 }; 1383 typedef union ody_dsuubx_cluster_ppu_cidr2 ody_dsuubx_cluster_ppu_cidr2_t; 1384 1385 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_CIDR2(uint64_t a) __attribute__ ((pure, always_inline)); 1386 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_CIDR2(uint64_t a) 1387 { 1388 if (a <= 89) 1389 return 0x87e2ef030ff8ll + 0x1000000ll * ((a) & 0x7f); 1390 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_CIDR2", 1, a, 0, 0, 0, 0, 0); 1391 } 1392 1393 #define typedef_ODY_DSUUBX_CLUSTER_PPU_CIDR2(a) ody_dsuubx_cluster_ppu_cidr2_t 1394 #define bustype_ODY_DSUUBX_CLUSTER_PPU_CIDR2(a) CSR_TYPE_RSL32b 1395 #define basename_ODY_DSUUBX_CLUSTER_PPU_CIDR2(a) "DSUUBX_CLUSTER_PPU_CIDR2" 1396 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_CIDR2(a) 0x0 /* PF_BAR0 */ 1397 #define busnum_ODY_DSUUBX_CLUSTER_PPU_CIDR2(a) (a) 1398 #define arguments_ODY_DSUUBX_CLUSTER_PPU_CIDR2(a) (a), -1, -1, -1 1399 1400 /** 1401 * Register (RSL32b) dsuub#_cluster_ppu_dcdr0 1402 * 1403 * DSUUB Cluster Device Control Delay Configuration Register 0 1404 * This register is used to program device control delay parameters. 1405 */ 1406 union ody_dsuubx_cluster_ppu_dcdr0 { 1407 uint32_t u; 1408 struct ody_dsuubx_cluster_ppu_dcdr0_s { 1409 uint32_t clken_rst_dly : 8; 1410 uint32_t iso_clken_dly : 8; 1411 uint32_t rst_hwstat_dly : 8; 1412 uint32_t reserved_24_31 : 8; 1413 } s; 1414 /* struct ody_dsuubx_cluster_ppu_dcdr0_s cn; */ 1415 }; 1416 typedef union ody_dsuubx_cluster_ppu_dcdr0 ody_dsuubx_cluster_ppu_dcdr0_t; 1417 1418 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_DCDR0(uint64_t a) __attribute__ ((pure, always_inline)); 1419 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_DCDR0(uint64_t a) 1420 { 1421 if (a <= 89) 1422 return 0x87e2ef030170ll + 0x1000000ll * ((a) & 0x7f); 1423 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_DCDR0", 1, a, 0, 0, 0, 0, 0); 1424 } 1425 1426 #define typedef_ODY_DSUUBX_CLUSTER_PPU_DCDR0(a) ody_dsuubx_cluster_ppu_dcdr0_t 1427 #define bustype_ODY_DSUUBX_CLUSTER_PPU_DCDR0(a) CSR_TYPE_RSL32b 1428 #define basename_ODY_DSUUBX_CLUSTER_PPU_DCDR0(a) "DSUUBX_CLUSTER_PPU_DCDR0" 1429 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_DCDR0(a) 0x0 /* PF_BAR0 */ 1430 #define busnum_ODY_DSUUBX_CLUSTER_PPU_DCDR0(a) (a) 1431 #define arguments_ODY_DSUUBX_CLUSTER_PPU_DCDR0(a) (a), -1, -1, -1 1432 1433 /** 1434 * Register (RSL32b) dsuub#_cluster_ppu_dcdr1 1435 * 1436 * DSUUB Cluster Device Control Delay Configuration Register 1 1437 * This register is used to program device control delay parameters. 1438 */ 1439 union ody_dsuubx_cluster_ppu_dcdr1 { 1440 uint32_t u; 1441 struct ody_dsuubx_cluster_ppu_dcdr1_s { 1442 uint32_t iso_rst_dly : 8; 1443 uint32_t clken_iso_dly : 8; 1444 uint32_t reserved_16_31 : 16; 1445 } s; 1446 /* struct ody_dsuubx_cluster_ppu_dcdr1_s cn; */ 1447 }; 1448 typedef union ody_dsuubx_cluster_ppu_dcdr1 ody_dsuubx_cluster_ppu_dcdr1_t; 1449 1450 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_DCDR1(uint64_t a) __attribute__ ((pure, always_inline)); 1451 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_DCDR1(uint64_t a) 1452 { 1453 if (a <= 89) 1454 return 0x87e2ef030174ll + 0x1000000ll * ((a) & 0x7f); 1455 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_DCDR1", 1, a, 0, 0, 0, 0, 0); 1456 } 1457 1458 #define typedef_ODY_DSUUBX_CLUSTER_PPU_DCDR1(a) ody_dsuubx_cluster_ppu_dcdr1_t 1459 #define bustype_ODY_DSUUBX_CLUSTER_PPU_DCDR1(a) CSR_TYPE_RSL32b 1460 #define basename_ODY_DSUUBX_CLUSTER_PPU_DCDR1(a) "DSUUBX_CLUSTER_PPU_DCDR1" 1461 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_DCDR1(a) 0x0 /* PF_BAR0 */ 1462 #define busnum_ODY_DSUUBX_CLUSTER_PPU_DCDR1(a) (a) 1463 #define arguments_ODY_DSUUBX_CLUSTER_PPU_DCDR1(a) (a), -1, -1, -1 1464 1465 /** 1466 * Register (RSL32b) dsuub#_cluster_ppu_disr 1467 * 1468 * DSUUB Cluster Device Interface Input Current Status Register 1469 * This read-only register contains status reflecting the values of the device interface inputs. 1470 */ 1471 union ody_dsuubx_cluster_ppu_disr { 1472 uint32_t u; 1473 struct ody_dsuubx_cluster_ppu_disr_s { 1474 uint32_t pwr_devactive_status : 11; 1475 uint32_t reserved_11_23 : 13; 1476 uint32_t op_devactive_status : 3; 1477 uint32_t reserved_27_31 : 5; 1478 } s; 1479 /* struct ody_dsuubx_cluster_ppu_disr_s cn; */ 1480 }; 1481 typedef union ody_dsuubx_cluster_ppu_disr ody_dsuubx_cluster_ppu_disr_t; 1482 1483 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_DISR(uint64_t a) __attribute__ ((pure, always_inline)); 1484 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_DISR(uint64_t a) 1485 { 1486 if (a <= 89) 1487 return 0x87e2ef030010ll + 0x1000000ll * ((a) & 0x7f); 1488 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_DISR", 1, a, 0, 0, 0, 0, 0); 1489 } 1490 1491 #define typedef_ODY_DSUUBX_CLUSTER_PPU_DISR(a) ody_dsuubx_cluster_ppu_disr_t 1492 #define bustype_ODY_DSUUBX_CLUSTER_PPU_DISR(a) CSR_TYPE_RSL32b 1493 #define basename_ODY_DSUUBX_CLUSTER_PPU_DISR(a) "DSUUBX_CLUSTER_PPU_DISR" 1494 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_DISR(a) 0x0 /* PF_BAR0 */ 1495 #define busnum_ODY_DSUUBX_CLUSTER_PPU_DISR(a) (a) 1496 #define arguments_ODY_DSUUBX_CLUSTER_PPU_DISR(a) (a), -1, -1, -1 1497 1498 /** 1499 * Register (RSL32b) dsuub#_cluster_ppu_fulrr 1500 * 1501 * DSUUB Cluster Full Retention RAM Configuration Register 1502 * This register controls bits [15:8] of the PCSMPSTATE output when in FULL_RET mode. These 1503 * outputs are used by the PCSM to configure the logic regions and RAMs that are retained. 1504 */ 1505 union ody_dsuubx_cluster_ppu_fulrr { 1506 uint32_t u; 1507 struct ody_dsuubx_cluster_ppu_fulrr_s { 1508 uint32_t full_ret_ram_cfg : 8; 1509 uint32_t reserved_8_31 : 24; 1510 } s; 1511 /* struct ody_dsuubx_cluster_ppu_fulrr_s cn; */ 1512 }; 1513 typedef union ody_dsuubx_cluster_ppu_fulrr ody_dsuubx_cluster_ppu_fulrr_t; 1514 1515 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_FULRR(uint64_t a) __attribute__ ((pure, always_inline)); 1516 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_FULRR(uint64_t a) 1517 { 1518 if (a <= 89) 1519 return 0x87e2ef030054ll + 0x1000000ll * ((a) & 0x7f); 1520 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_FULRR", 1, a, 0, 0, 0, 0, 0); 1521 } 1522 1523 #define typedef_ODY_DSUUBX_CLUSTER_PPU_FULRR(a) ody_dsuubx_cluster_ppu_fulrr_t 1524 #define bustype_ODY_DSUUBX_CLUSTER_PPU_FULRR(a) CSR_TYPE_RSL32b 1525 #define basename_ODY_DSUUBX_CLUSTER_PPU_FULRR(a) "DSUUBX_CLUSTER_PPU_FULRR" 1526 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_FULRR(a) 0x0 /* PF_BAR0 */ 1527 #define busnum_ODY_DSUUBX_CLUSTER_PPU_FULRR(a) (a) 1528 #define arguments_ODY_DSUUBX_CLUSTER_PPU_FULRR(a) (a), -1, -1, -1 1529 1530 /** 1531 * Register (RSL32b) dsuub#_cluster_ppu_funrr 1532 * 1533 * DSUUB Cluster Functional Retention RAM Configuration Register 1534 * This register is reserved. 1535 */ 1536 union ody_dsuubx_cluster_ppu_funrr { 1537 uint32_t u; 1538 struct ody_dsuubx_cluster_ppu_funrr_s { 1539 uint32_t func_ret_ram_cfg : 8; 1540 uint32_t reserved_8_31 : 24; 1541 } s; 1542 /* struct ody_dsuubx_cluster_ppu_funrr_s cn; */ 1543 }; 1544 typedef union ody_dsuubx_cluster_ppu_funrr ody_dsuubx_cluster_ppu_funrr_t; 1545 1546 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_FUNRR(uint64_t a) __attribute__ ((pure, always_inline)); 1547 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_FUNRR(uint64_t a) 1548 { 1549 if (a <= 89) 1550 return 0x87e2ef030050ll + 0x1000000ll * ((a) & 0x7f); 1551 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_FUNRR", 1, a, 0, 0, 0, 0, 0); 1552 } 1553 1554 #define typedef_ODY_DSUUBX_CLUSTER_PPU_FUNRR(a) ody_dsuubx_cluster_ppu_funrr_t 1555 #define bustype_ODY_DSUUBX_CLUSTER_PPU_FUNRR(a) CSR_TYPE_RSL32b 1556 #define basename_ODY_DSUUBX_CLUSTER_PPU_FUNRR(a) "DSUUBX_CLUSTER_PPU_FUNRR" 1557 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_FUNRR(a) 0x0 /* PF_BAR0 */ 1558 #define busnum_ODY_DSUUBX_CLUSTER_PPU_FUNRR(a) (a) 1559 #define arguments_ODY_DSUUBX_CLUSTER_PPU_FUNRR(a) (a), -1, -1, -1 1560 1561 /** 1562 * Register (RSL32b) dsuub#_cluster_ppu_idr0 1563 * 1564 * DSUUB Cluster PPU Identification Register 0 1565 * This read-only register contains information on the type and number of channels on the device 1566 * interface and power and operating modes supported. 1567 * 1568 * Additional information on optional features can be found in the PPU Identification 1569 * Register 1 (DSUUB_ 1570 * PPU_IDR1). 1571 */ 1572 union ody_dsuubx_cluster_ppu_idr0 { 1573 uint32_t u; 1574 struct ody_dsuubx_cluster_ppu_idr0_s { 1575 uint32_t devchan : 4; 1576 uint32_t num_opmode : 4; 1577 uint32_t sta_off_spt : 1; 1578 uint32_t sta_off_emu_spt : 1; 1579 uint32_t sta_mem_ret_spt : 1; 1580 uint32_t sta_mem_ret_emu_spt : 1; 1581 uint32_t sta_lgc_ret_spt : 1; 1582 uint32_t sta_mem_off_spt : 1; 1583 uint32_t sta_full_ret_spt : 1; 1584 uint32_t sta_func_ret_spt : 1; 1585 uint32_t sta_on_spt : 1; 1586 uint32_t sta_wrm_rst_spt : 1; 1587 uint32_t sta_dbg_recov_spt : 1; 1588 uint32_t reserved_19 : 1; 1589 uint32_t dyn_off_spt : 1; 1590 uint32_t dyn_off_emu_spt : 1; 1591 uint32_t dyn_mem_ret_spt : 1; 1592 uint32_t dyn_mem_ret_emu_spt : 1; 1593 uint32_t dyn_lgc_ret_spt : 1; 1594 uint32_t dyn_mem_off_spt : 1; 1595 uint32_t dyn_full_ret_spt : 1; 1596 uint32_t dyn_func_ret_spt : 1; 1597 uint32_t dyn_on_spt : 1; 1598 uint32_t dyn_wrm_rst_spt : 1; 1599 uint32_t reserved_30_31 : 2; 1600 } s; 1601 /* struct ody_dsuubx_cluster_ppu_idr0_s cn; */ 1602 }; 1603 typedef union ody_dsuubx_cluster_ppu_idr0 ody_dsuubx_cluster_ppu_idr0_t; 1604 1605 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_IDR0(uint64_t a) __attribute__ ((pure, always_inline)); 1606 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_IDR0(uint64_t a) 1607 { 1608 if (a <= 89) 1609 return 0x87e2ef030fb0ll + 0x1000000ll * ((a) & 0x7f); 1610 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_IDR0", 1, a, 0, 0, 0, 0, 0); 1611 } 1612 1613 #define typedef_ODY_DSUUBX_CLUSTER_PPU_IDR0(a) ody_dsuubx_cluster_ppu_idr0_t 1614 #define bustype_ODY_DSUUBX_CLUSTER_PPU_IDR0(a) CSR_TYPE_RSL32b 1615 #define basename_ODY_DSUUBX_CLUSTER_PPU_IDR0(a) "DSUUBX_CLUSTER_PPU_IDR0" 1616 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_IDR0(a) 0x0 /* PF_BAR0 */ 1617 #define busnum_ODY_DSUUBX_CLUSTER_PPU_IDR0(a) (a) 1618 #define arguments_ODY_DSUUBX_CLUSTER_PPU_IDR0(a) (a), -1, -1, -1 1619 1620 /** 1621 * Register (RSL32b) dsuub#_cluster_ppu_idr1 1622 * 1623 * DSUUB Cluster PPU Identification Register 1 1624 * This read-only register contains information on the optional features and configurations that are 1625 * supported by this PPU. 1626 * 1627 * Additional information on optional features can be found in the PPU Identification 1628 * Register 0 (DSUUB_ 1629 * PPU_IDR0). 1630 */ 1631 union ody_dsuubx_cluster_ppu_idr1 { 1632 uint32_t u; 1633 struct ody_dsuubx_cluster_ppu_idr1_s { 1634 uint32_t pwr_mode_entry_del_spt : 1; 1635 uint32_t sw_dev_del_spt : 1; 1636 uint32_t lock_spt : 1; 1637 uint32_t reserved_3 : 1; 1638 uint32_t mem_ret_ram_reg : 1; 1639 uint32_t full_ret_ram_reg : 1; 1640 uint32_t func_ret_ram_reg : 1; 1641 uint32_t reserved_7 : 1; 1642 uint32_t sta_policy_pwr_irq_spt : 1; 1643 uint32_t sta_policy_op_irq_spt : 1; 1644 uint32_t op_active : 1; 1645 uint32_t reserved_11 : 1; 1646 uint32_t off_mem_ret_trans : 1; 1647 uint32_t reserved_13_31 : 19; 1648 } s; 1649 /* struct ody_dsuubx_cluster_ppu_idr1_s cn; */ 1650 }; 1651 typedef union ody_dsuubx_cluster_ppu_idr1 ody_dsuubx_cluster_ppu_idr1_t; 1652 1653 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_IDR1(uint64_t a) __attribute__ ((pure, always_inline)); 1654 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_IDR1(uint64_t a) 1655 { 1656 if (a <= 89) 1657 return 0x87e2ef030fb4ll + 0x1000000ll * ((a) & 0x7f); 1658 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_IDR1", 1, a, 0, 0, 0, 0, 0); 1659 } 1660 1661 #define typedef_ODY_DSUUBX_CLUSTER_PPU_IDR1(a) ody_dsuubx_cluster_ppu_idr1_t 1662 #define bustype_ODY_DSUUBX_CLUSTER_PPU_IDR1(a) CSR_TYPE_RSL32b 1663 #define basename_ODY_DSUUBX_CLUSTER_PPU_IDR1(a) "DSUUBX_CLUSTER_PPU_IDR1" 1664 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_IDR1(a) 0x0 /* PF_BAR0 */ 1665 #define busnum_ODY_DSUUBX_CLUSTER_PPU_IDR1(a) (a) 1666 #define arguments_ODY_DSUUBX_CLUSTER_PPU_IDR1(a) (a), -1, -1, -1 1667 1668 /** 1669 * Register (RSL32b) dsuub#_cluster_ppu_iesr 1670 * 1671 * DSUUB Cluster Input Edge Sensitivity Register 1672 * This register configures the transitions on the power mode DEVPACTIVE inputs that generate an 1673 * Input Edge interrupt event. 1674 * 1675 * When an event is masked an occurrence of the event does not set the corresponding bit in the 1676 * interrupt status register. 1677 */ 1678 union ody_dsuubx_cluster_ppu_iesr { 1679 uint32_t u; 1680 struct ody_dsuubx_cluster_ppu_iesr_s { 1681 uint32_t reserved_0_1 : 2; 1682 uint32_t devactive01_edge : 2; 1683 uint32_t devactive02_edge : 2; 1684 uint32_t devactive03_edge : 2; 1685 uint32_t reserved_8_13 : 6; 1686 uint32_t devactive07_edge : 2; 1687 uint32_t devactive08_edge : 2; 1688 uint32_t devactive09_edge : 2; 1689 uint32_t devactive10_edge : 2; 1690 uint32_t reserved_22_31 : 10; 1691 } s; 1692 /* struct ody_dsuubx_cluster_ppu_iesr_s cn; */ 1693 }; 1694 typedef union ody_dsuubx_cluster_ppu_iesr ody_dsuubx_cluster_ppu_iesr_t; 1695 1696 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_IESR(uint64_t a) __attribute__ ((pure, always_inline)); 1697 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_IESR(uint64_t a) 1698 { 1699 if (a <= 89) 1700 return 0x87e2ef030040ll + 0x1000000ll * ((a) & 0x7f); 1701 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_IESR", 1, a, 0, 0, 0, 0, 0); 1702 } 1703 1704 #define typedef_ODY_DSUUBX_CLUSTER_PPU_IESR(a) ody_dsuubx_cluster_ppu_iesr_t 1705 #define bustype_ODY_DSUUBX_CLUSTER_PPU_IESR(a) CSR_TYPE_RSL32b 1706 #define basename_ODY_DSUUBX_CLUSTER_PPU_IESR(a) "DSUUBX_CLUSTER_PPU_IESR" 1707 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_IESR(a) 0x0 /* PF_BAR0 */ 1708 #define busnum_ODY_DSUUBX_CLUSTER_PPU_IESR(a) (a) 1709 #define arguments_ODY_DSUUBX_CLUSTER_PPU_IESR(a) (a), -1, -1, -1 1710 1711 /** 1712 * Register (RSL32b) dsuub#_cluster_ppu_iidr 1713 * 1714 * DSUUB Cluster Implementation Identification Register 1715 * This register provides information about the implementer and implementation of the PPU. 1716 */ 1717 union ody_dsuubx_cluster_ppu_iidr { 1718 uint32_t u; 1719 struct ody_dsuubx_cluster_ppu_iidr_s { 1720 uint32_t implementer : 12; 1721 uint32_t revision : 4; 1722 uint32_t variant : 4; 1723 uint32_t product_id : 12; 1724 } s; 1725 /* struct ody_dsuubx_cluster_ppu_iidr_s cn; */ 1726 }; 1727 typedef union ody_dsuubx_cluster_ppu_iidr ody_dsuubx_cluster_ppu_iidr_t; 1728 1729 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_IIDR(uint64_t a) __attribute__ ((pure, always_inline)); 1730 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_IIDR(uint64_t a) 1731 { 1732 if (a <= 89) 1733 return 0x87e2ef030fc8ll + 0x1000000ll * ((a) & 0x7f); 1734 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_IIDR", 1, a, 0, 0, 0, 0, 0); 1735 } 1736 1737 #define typedef_ODY_DSUUBX_CLUSTER_PPU_IIDR(a) ody_dsuubx_cluster_ppu_iidr_t 1738 #define bustype_ODY_DSUUBX_CLUSTER_PPU_IIDR(a) CSR_TYPE_RSL32b 1739 #define basename_ODY_DSUUBX_CLUSTER_PPU_IIDR(a) "DSUUBX_CLUSTER_PPU_IIDR" 1740 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_IIDR(a) 0x0 /* PF_BAR0 */ 1741 #define busnum_ODY_DSUUBX_CLUSTER_PPU_IIDR(a) (a) 1742 #define arguments_ODY_DSUUBX_CLUSTER_PPU_IIDR(a) (a), -1, -1, -1 1743 1744 /** 1745 * Register (RSL32b) dsuub#_cluster_ppu_imr 1746 * 1747 * DSUUB Cluster Interrupt Mask Register 1748 * This register controls the events that assert the interrupt output. Additional event 1749 * masking controls 1750 * are in the Additional Interrupt Mask Register (DSUUB_PPU_AIMR), Input Edge 1751 * Sensitivity Register (DSUUB_ 1752 * PPU_IESR), and the Operating Mode Active Edge Sensitivity Register (DSUUB_PPU_OPSR). 1753 * 1754 * When an interrupt event is masked an occurrence of the event does not set the corresponding bit 1755 * in the interrupt status register. 1756 */ 1757 union ody_dsuubx_cluster_ppu_imr { 1758 uint32_t u; 1759 struct ody_dsuubx_cluster_ppu_imr_s { 1760 uint32_t sta_policy_trn_irq_mask : 1; 1761 uint32_t sta_accept_irq_mask : 1; 1762 uint32_t sta_deny_irq_mask : 1; 1763 uint32_t emu_accept_irq_mask : 1; 1764 uint32_t emu_deny_irq_mask : 1; 1765 uint32_t locked_irq_mask : 1; 1766 uint32_t reserved_6_31 : 26; 1767 } s; 1768 /* struct ody_dsuubx_cluster_ppu_imr_s cn; */ 1769 }; 1770 typedef union ody_dsuubx_cluster_ppu_imr ody_dsuubx_cluster_ppu_imr_t; 1771 1772 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_IMR(uint64_t a) __attribute__ ((pure, always_inline)); 1773 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_IMR(uint64_t a) 1774 { 1775 if (a <= 89) 1776 return 0x87e2ef030030ll + 0x1000000ll * ((a) & 0x7f); 1777 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_IMR", 1, a, 0, 0, 0, 0, 0); 1778 } 1779 1780 #define typedef_ODY_DSUUBX_CLUSTER_PPU_IMR(a) ody_dsuubx_cluster_ppu_imr_t 1781 #define bustype_ODY_DSUUBX_CLUSTER_PPU_IMR(a) CSR_TYPE_RSL32b 1782 #define basename_ODY_DSUUBX_CLUSTER_PPU_IMR(a) "DSUUBX_CLUSTER_PPU_IMR" 1783 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_IMR(a) 0x0 /* PF_BAR0 */ 1784 #define busnum_ODY_DSUUBX_CLUSTER_PPU_IMR(a) (a) 1785 #define arguments_ODY_DSUUBX_CLUSTER_PPU_IMR(a) (a), -1, -1, -1 1786 1787 /** 1788 * Register (RSL32b) dsuub#_cluster_ppu_isr 1789 * 1790 * DSUUB Cluster Interrupt Status Register 1791 * This register contains information about events causing the assertion of the 1792 * interrupt output. It is 1793 * also used to clear interrupt events. 1794 * 1795 * A bit set to 1 indicates the event asserted the interrupt output. Multiple events 1796 * can be active at 1797 * the same time. When an interrupt event is masked an occurrence of that event does not set the 1798 * status bit. 1799 * 1800 * A write of 1 to an event bit clears that event. A write of 0 to a bit has no 1801 * effect. The interrupt 1802 * output stays HIGH until all status bits in the Interrupt Status Register (PPU_ISR) 1803 * and the Additional 1804 * Interrupt Status Register (DSUUB_PPU_AISR) are 0b0. 1805 * 1806 * When the OTHER_IRQ bit is set, this indicates an event from the Additional Interrupt Status 1807 * Register (PPU_AISR) has caused the interrupt output to be asserted. This bit cannot be cleared by 1808 * writing to this register. It must be cleared by writing to the active event in the 1809 * Additional Interrupt 1810 * Status Register (DSUUB_PPU_AISR). 1811 */ 1812 union ody_dsuubx_cluster_ppu_isr { 1813 uint32_t u; 1814 struct ody_dsuubx_cluster_ppu_isr_s { 1815 uint32_t sta_policy_trn_irq : 1; 1816 uint32_t sta_accept_irq : 1; 1817 uint32_t sta_deny_irq : 1; 1818 uint32_t emu_accept_irq : 1; 1819 uint32_t emu_deny_irq : 1; 1820 uint32_t locked_irq : 1; 1821 uint32_t reserved_6 : 1; 1822 uint32_t other_irq : 1; 1823 uint32_t reserved_8 : 1; 1824 uint32_t pwr_active_edge_irq1 : 1; 1825 uint32_t pwr_active_edge_irq2 : 1; 1826 uint32_t pwr_active_edge_irq3 : 1; 1827 uint32_t reserved_12_14 : 3; 1828 uint32_t pwr_active_edge_irq7 : 1; 1829 uint32_t pwr_active_edge_irq8 : 1; 1830 uint32_t pwr_active_edge_irq9 : 1; 1831 uint32_t pwr_active_edge_irq10 : 1; 1832 uint32_t reserved_19_23 : 5; 1833 uint32_t op_active_edge_irq0 : 1; 1834 uint32_t op_active_edge_irq1 : 1; 1835 uint32_t op_active_edge_irq2 : 1; 1836 uint32_t reserved_27_31 : 5; 1837 } s; 1838 /* struct ody_dsuubx_cluster_ppu_isr_s cn; */ 1839 }; 1840 typedef union ody_dsuubx_cluster_ppu_isr ody_dsuubx_cluster_ppu_isr_t; 1841 1842 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_ISR(uint64_t a) __attribute__ ((pure, always_inline)); 1843 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_ISR(uint64_t a) 1844 { 1845 if (a <= 89) 1846 return 0x87e2ef030038ll + 0x1000000ll * ((a) & 0x7f); 1847 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_ISR", 1, a, 0, 0, 0, 0, 0); 1848 } 1849 1850 #define typedef_ODY_DSUUBX_CLUSTER_PPU_ISR(a) ody_dsuubx_cluster_ppu_isr_t 1851 #define bustype_ODY_DSUUBX_CLUSTER_PPU_ISR(a) CSR_TYPE_RSL32b 1852 #define basename_ODY_DSUUBX_CLUSTER_PPU_ISR(a) "DSUUBX_CLUSTER_PPU_ISR" 1853 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_ISR(a) 0x0 /* PF_BAR0 */ 1854 #define busnum_ODY_DSUUBX_CLUSTER_PPU_ISR(a) (a) 1855 #define arguments_ODY_DSUUBX_CLUSTER_PPU_ISR(a) (a), -1, -1, -1 1856 1857 /** 1858 * Register (RSL32b) dsuub#_cluster_ppu_memrr 1859 * 1860 * DSUUB Cluster Memory Retention RAM Configuration Register 1861 * This register controls bits [15:8] of the PCSMPSTATE output when in MEM_RET mode. These 1862 * outputs are used by the PCSM to configure the RAMs that are retained. 1863 */ 1864 union ody_dsuubx_cluster_ppu_memrr { 1865 uint32_t u; 1866 struct ody_dsuubx_cluster_ppu_memrr_s { 1867 uint32_t mem_ret_ram_cfg : 8; 1868 uint32_t reserved_8_31 : 24; 1869 } s; 1870 /* struct ody_dsuubx_cluster_ppu_memrr_s cn; */ 1871 }; 1872 typedef union ody_dsuubx_cluster_ppu_memrr ody_dsuubx_cluster_ppu_memrr_t; 1873 1874 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_MEMRR(uint64_t a) __attribute__ ((pure, always_inline)); 1875 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_MEMRR(uint64_t a) 1876 { 1877 if (a <= 89) 1878 return 0x87e2ef030058ll + 0x1000000ll * ((a) & 0x7f); 1879 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_MEMRR", 1, a, 0, 0, 0, 0, 0); 1880 } 1881 1882 #define typedef_ODY_DSUUBX_CLUSTER_PPU_MEMRR(a) ody_dsuubx_cluster_ppu_memrr_t 1883 #define bustype_ODY_DSUUBX_CLUSTER_PPU_MEMRR(a) CSR_TYPE_RSL32b 1884 #define basename_ODY_DSUUBX_CLUSTER_PPU_MEMRR(a) "DSUUBX_CLUSTER_PPU_MEMRR" 1885 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_MEMRR(a) 0x0 /* PF_BAR0 */ 1886 #define busnum_ODY_DSUUBX_CLUSTER_PPU_MEMRR(a) (a) 1887 #define arguments_ODY_DSUUBX_CLUSTER_PPU_MEMRR(a) (a), -1, -1, -1 1888 1889 /** 1890 * Register (RSL32b) dsuub#_cluster_ppu_misr 1891 * 1892 * DSUUB Cluster Miscellaneous Input Current Status Register 1893 * This read-only register contains status reflecting the values of miscellaneous inputs. 1894 */ 1895 union ody_dsuubx_cluster_ppu_misr { 1896 uint32_t u; 1897 struct ody_dsuubx_cluster_ppu_misr_s { 1898 uint32_t pcsmpaccept_status : 1; 1899 uint32_t reserved_1_7 : 7; 1900 uint32_t devaccept_status : 1; 1901 uint32_t reserved_9_15 : 7; 1902 uint32_t devdeny_status : 1; 1903 uint32_t reserved_17_31 : 15; 1904 } s; 1905 /* struct ody_dsuubx_cluster_ppu_misr_s cn; */ 1906 }; 1907 typedef union ody_dsuubx_cluster_ppu_misr ody_dsuubx_cluster_ppu_misr_t; 1908 1909 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_MISR(uint64_t a) __attribute__ ((pure, always_inline)); 1910 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_MISR(uint64_t a) 1911 { 1912 if (a <= 89) 1913 return 0x87e2ef030014ll + 0x1000000ll * ((a) & 0x7f); 1914 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_MISR", 1, a, 0, 0, 0, 0, 0); 1915 } 1916 1917 #define typedef_ODY_DSUUBX_CLUSTER_PPU_MISR(a) ody_dsuubx_cluster_ppu_misr_t 1918 #define bustype_ODY_DSUUBX_CLUSTER_PPU_MISR(a) CSR_TYPE_RSL32b 1919 #define basename_ODY_DSUUBX_CLUSTER_PPU_MISR(a) "DSUUBX_CLUSTER_PPU_MISR" 1920 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_MISR(a) 0x0 /* PF_BAR0 */ 1921 #define busnum_ODY_DSUUBX_CLUSTER_PPU_MISR(a) (a) 1922 #define arguments_ODY_DSUUBX_CLUSTER_PPU_MISR(a) (a), -1, -1, -1 1923 1924 /** 1925 * Register (RSL32b) dsuub#_cluster_ppu_opsr 1926 * 1927 * DSUUB Cluster Input Edge Sensitivity Register 1928 * This register configures the transitions on the operating mode DEVPACTIVE inputs that generate 1929 * an Input Edge interrupt event. 1930 * 1931 * When an event is masked an occurrence of the event does not set the corresponding bit in the 1932 * interrupt status register. 1933 */ 1934 union ody_dsuubx_cluster_ppu_opsr { 1935 uint32_t u; 1936 struct ody_dsuubx_cluster_ppu_opsr_s { 1937 uint32_t devactive16_edge : 2; 1938 uint32_t devactive17_edge : 2; 1939 uint32_t devactive18_edge : 2; 1940 uint32_t reserved_6_31 : 26; 1941 } s; 1942 /* struct ody_dsuubx_cluster_ppu_opsr_s cn; */ 1943 }; 1944 typedef union ody_dsuubx_cluster_ppu_opsr ody_dsuubx_cluster_ppu_opsr_t; 1945 1946 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_OPSR(uint64_t a) __attribute__ ((pure, always_inline)); 1947 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_OPSR(uint64_t a) 1948 { 1949 if (a <= 89) 1950 return 0x87e2ef030044ll + 0x1000000ll * ((a) & 0x7f); 1951 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_OPSR", 1, a, 0, 0, 0, 0, 0); 1952 } 1953 1954 #define typedef_ODY_DSUUBX_CLUSTER_PPU_OPSR(a) ody_dsuubx_cluster_ppu_opsr_t 1955 #define bustype_ODY_DSUUBX_CLUSTER_PPU_OPSR(a) CSR_TYPE_RSL32b 1956 #define basename_ODY_DSUUBX_CLUSTER_PPU_OPSR(a) "DSUUBX_CLUSTER_PPU_OPSR" 1957 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_OPSR(a) 0x0 /* PF_BAR0 */ 1958 #define busnum_ODY_DSUUBX_CLUSTER_PPU_OPSR(a) (a) 1959 #define arguments_ODY_DSUUBX_CLUSTER_PPU_OPSR(a) (a), -1, -1, -1 1960 1961 /** 1962 * Register (RSL32b) dsuub#_cluster_ppu_pidr0 1963 * 1964 * DSUUB Cluster PPU Peripheral Identification Register 0 1965 * Provides CoreSight discovery information. 1966 */ 1967 union ody_dsuubx_cluster_ppu_pidr0 { 1968 uint32_t u; 1969 struct ody_dsuubx_cluster_ppu_pidr0_s { 1970 uint32_t part_0 : 8; 1971 uint32_t reserved_8_31 : 24; 1972 } s; 1973 /* struct ody_dsuubx_cluster_ppu_pidr0_s cn; */ 1974 }; 1975 typedef union ody_dsuubx_cluster_ppu_pidr0 ody_dsuubx_cluster_ppu_pidr0_t; 1976 1977 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PIDR0(uint64_t a) __attribute__ ((pure, always_inline)); 1978 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PIDR0(uint64_t a) 1979 { 1980 if (a <= 89) 1981 return 0x87e2ef030fe0ll + 0x1000000ll * ((a) & 0x7f); 1982 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_PIDR0", 1, a, 0, 0, 0, 0, 0); 1983 } 1984 1985 #define typedef_ODY_DSUUBX_CLUSTER_PPU_PIDR0(a) ody_dsuubx_cluster_ppu_pidr0_t 1986 #define bustype_ODY_DSUUBX_CLUSTER_PPU_PIDR0(a) CSR_TYPE_RSL32b 1987 #define basename_ODY_DSUUBX_CLUSTER_PPU_PIDR0(a) "DSUUBX_CLUSTER_PPU_PIDR0" 1988 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_PIDR0(a) 0x0 /* PF_BAR0 */ 1989 #define busnum_ODY_DSUUBX_CLUSTER_PPU_PIDR0(a) (a) 1990 #define arguments_ODY_DSUUBX_CLUSTER_PPU_PIDR0(a) (a), -1, -1, -1 1991 1992 /** 1993 * Register (RSL32b) dsuub#_cluster_ppu_pidr1 1994 * 1995 * DSUUB Cluster PPU Peripheral Identification Register 1 1996 * Provides CoreSight discovery information. 1997 */ 1998 union ody_dsuubx_cluster_ppu_pidr1 { 1999 uint32_t u; 2000 struct ody_dsuubx_cluster_ppu_pidr1_s { 2001 uint32_t part_1 : 4; 2002 uint32_t des_0 : 4; 2003 uint32_t reserved_8_31 : 24; 2004 } s; 2005 /* struct ody_dsuubx_cluster_ppu_pidr1_s cn; */ 2006 }; 2007 typedef union ody_dsuubx_cluster_ppu_pidr1 ody_dsuubx_cluster_ppu_pidr1_t; 2008 2009 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PIDR1(uint64_t a) __attribute__ ((pure, always_inline)); 2010 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PIDR1(uint64_t a) 2011 { 2012 if (a <= 89) 2013 return 0x87e2ef030fe4ll + 0x1000000ll * ((a) & 0x7f); 2014 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_PIDR1", 1, a, 0, 0, 0, 0, 0); 2015 } 2016 2017 #define typedef_ODY_DSUUBX_CLUSTER_PPU_PIDR1(a) ody_dsuubx_cluster_ppu_pidr1_t 2018 #define bustype_ODY_DSUUBX_CLUSTER_PPU_PIDR1(a) CSR_TYPE_RSL32b 2019 #define basename_ODY_DSUUBX_CLUSTER_PPU_PIDR1(a) "DSUUBX_CLUSTER_PPU_PIDR1" 2020 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_PIDR1(a) 0x0 /* PF_BAR0 */ 2021 #define busnum_ODY_DSUUBX_CLUSTER_PPU_PIDR1(a) (a) 2022 #define arguments_ODY_DSUUBX_CLUSTER_PPU_PIDR1(a) (a), -1, -1, -1 2023 2024 /** 2025 * Register (RSL32b) dsuub#_cluster_ppu_pidr2 2026 * 2027 * DSUUB Cluster PPU Peripheral Identification Register 2 2028 * Provides CoreSight discovery information. 2029 */ 2030 union ody_dsuubx_cluster_ppu_pidr2 { 2031 uint32_t u; 2032 struct ody_dsuubx_cluster_ppu_pidr2_s { 2033 uint32_t des_1 : 3; 2034 uint32_t jedec : 1; 2035 uint32_t revision : 4; 2036 uint32_t reserved_8_31 : 24; 2037 } s; 2038 /* struct ody_dsuubx_cluster_ppu_pidr2_s cn; */ 2039 }; 2040 typedef union ody_dsuubx_cluster_ppu_pidr2 ody_dsuubx_cluster_ppu_pidr2_t; 2041 2042 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PIDR2(uint64_t a) __attribute__ ((pure, always_inline)); 2043 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PIDR2(uint64_t a) 2044 { 2045 if (a <= 89) 2046 return 0x87e2ef030fe8ll + 0x1000000ll * ((a) & 0x7f); 2047 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_PIDR2", 1, a, 0, 0, 0, 0, 0); 2048 } 2049 2050 #define typedef_ODY_DSUUBX_CLUSTER_PPU_PIDR2(a) ody_dsuubx_cluster_ppu_pidr2_t 2051 #define bustype_ODY_DSUUBX_CLUSTER_PPU_PIDR2(a) CSR_TYPE_RSL32b 2052 #define basename_ODY_DSUUBX_CLUSTER_PPU_PIDR2(a) "DSUUBX_CLUSTER_PPU_PIDR2" 2053 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_PIDR2(a) 0x0 /* PF_BAR0 */ 2054 #define busnum_ODY_DSUUBX_CLUSTER_PPU_PIDR2(a) (a) 2055 #define arguments_ODY_DSUUBX_CLUSTER_PPU_PIDR2(a) (a), -1, -1, -1 2056 2057 /** 2058 * Register (RSL32b) dsuub#_cluster_ppu_pidr3 2059 * 2060 * DSUUB Cluster PPU Peripheral Identification Register 3 2061 * Provides CoreSight discovery information. 2062 */ 2063 union ody_dsuubx_cluster_ppu_pidr3 { 2064 uint32_t u; 2065 struct ody_dsuubx_cluster_ppu_pidr3_s { 2066 uint32_t cmod : 4; 2067 uint32_t revand : 4; 2068 uint32_t reserved_8_31 : 24; 2069 } s; 2070 /* struct ody_dsuubx_cluster_ppu_pidr3_s cn; */ 2071 }; 2072 typedef union ody_dsuubx_cluster_ppu_pidr3 ody_dsuubx_cluster_ppu_pidr3_t; 2073 2074 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PIDR3(uint64_t a) __attribute__ ((pure, always_inline)); 2075 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PIDR3(uint64_t a) 2076 { 2077 if (a <= 89) 2078 return 0x87e2ef030fecll + 0x1000000ll * ((a) & 0x7f); 2079 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_PIDR3", 1, a, 0, 0, 0, 0, 0); 2080 } 2081 2082 #define typedef_ODY_DSUUBX_CLUSTER_PPU_PIDR3(a) ody_dsuubx_cluster_ppu_pidr3_t 2083 #define bustype_ODY_DSUUBX_CLUSTER_PPU_PIDR3(a) CSR_TYPE_RSL32b 2084 #define basename_ODY_DSUUBX_CLUSTER_PPU_PIDR3(a) "DSUUBX_CLUSTER_PPU_PIDR3" 2085 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_PIDR3(a) 0x0 /* PF_BAR0 */ 2086 #define busnum_ODY_DSUUBX_CLUSTER_PPU_PIDR3(a) (a) 2087 #define arguments_ODY_DSUUBX_CLUSTER_PPU_PIDR3(a) (a), -1, -1, -1 2088 2089 /** 2090 * Register (RSL32b) dsuub#_cluster_ppu_pidr4 2091 * 2092 * DSUUB Cluster PPU Peripheral Identification Register 4 2093 * Provides CoreSight discovery information. 2094 */ 2095 union ody_dsuubx_cluster_ppu_pidr4 { 2096 uint32_t u; 2097 struct ody_dsuubx_cluster_ppu_pidr4_s { 2098 uint32_t des_2 : 4; 2099 uint32_t size : 4; 2100 uint32_t reserved_8_31 : 24; 2101 } s; 2102 /* struct ody_dsuubx_cluster_ppu_pidr4_s cn; */ 2103 }; 2104 typedef union ody_dsuubx_cluster_ppu_pidr4 ody_dsuubx_cluster_ppu_pidr4_t; 2105 2106 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PIDR4(uint64_t a) __attribute__ ((pure, always_inline)); 2107 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PIDR4(uint64_t a) 2108 { 2109 if (a <= 89) 2110 return 0x87e2ef030fd0ll + 0x1000000ll * ((a) & 0x7f); 2111 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_PIDR4", 1, a, 0, 0, 0, 0, 0); 2112 } 2113 2114 #define typedef_ODY_DSUUBX_CLUSTER_PPU_PIDR4(a) ody_dsuubx_cluster_ppu_pidr4_t 2115 #define bustype_ODY_DSUUBX_CLUSTER_PPU_PIDR4(a) CSR_TYPE_RSL32b 2116 #define basename_ODY_DSUUBX_CLUSTER_PPU_PIDR4(a) "DSUUBX_CLUSTER_PPU_PIDR4" 2117 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_PIDR4(a) 0x0 /* PF_BAR0 */ 2118 #define busnum_ODY_DSUUBX_CLUSTER_PPU_PIDR4(a) (a) 2119 #define arguments_ODY_DSUUBX_CLUSTER_PPU_PIDR4(a) (a), -1, -1, -1 2120 2121 /** 2122 * Register (RSL32b) dsuub#_cluster_ppu_pidr5 2123 * 2124 * DSUUB Cluster PPU Peripheral Identification Register 5 2125 * Provides CoreSight discovery information. 2126 */ 2127 union ody_dsuubx_cluster_ppu_pidr5 { 2128 uint32_t u; 2129 struct ody_dsuubx_cluster_ppu_pidr5_s { 2130 uint32_t reserved_0_31 : 32; 2131 } s; 2132 /* struct ody_dsuubx_cluster_ppu_pidr5_s cn; */ 2133 }; 2134 typedef union ody_dsuubx_cluster_ppu_pidr5 ody_dsuubx_cluster_ppu_pidr5_t; 2135 2136 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PIDR5(uint64_t a) __attribute__ ((pure, always_inline)); 2137 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PIDR5(uint64_t a) 2138 { 2139 if (a <= 89) 2140 return 0x87e2ef030fd4ll + 0x1000000ll * ((a) & 0x7f); 2141 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_PIDR5", 1, a, 0, 0, 0, 0, 0); 2142 } 2143 2144 #define typedef_ODY_DSUUBX_CLUSTER_PPU_PIDR5(a) ody_dsuubx_cluster_ppu_pidr5_t 2145 #define bustype_ODY_DSUUBX_CLUSTER_PPU_PIDR5(a) CSR_TYPE_RSL32b 2146 #define basename_ODY_DSUUBX_CLUSTER_PPU_PIDR5(a) "DSUUBX_CLUSTER_PPU_PIDR5" 2147 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_PIDR5(a) 0x0 /* PF_BAR0 */ 2148 #define busnum_ODY_DSUUBX_CLUSTER_PPU_PIDR5(a) (a) 2149 #define arguments_ODY_DSUUBX_CLUSTER_PPU_PIDR5(a) (a), -1, -1, -1 2150 2151 /** 2152 * Register (RSL32b) dsuub#_cluster_ppu_pidr6 2153 * 2154 * DSUUB Cluster PPU Peripheral Identification Register 6 2155 * Provides CoreSight discovery information. 2156 */ 2157 union ody_dsuubx_cluster_ppu_pidr6 { 2158 uint32_t u; 2159 struct ody_dsuubx_cluster_ppu_pidr6_s { 2160 uint32_t reserved_0_31 : 32; 2161 } s; 2162 /* struct ody_dsuubx_cluster_ppu_pidr6_s cn; */ 2163 }; 2164 typedef union ody_dsuubx_cluster_ppu_pidr6 ody_dsuubx_cluster_ppu_pidr6_t; 2165 2166 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PIDR6(uint64_t a) __attribute__ ((pure, always_inline)); 2167 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PIDR6(uint64_t a) 2168 { 2169 if (a <= 89) 2170 return 0x87e2ef030fd8ll + 0x1000000ll * ((a) & 0x7f); 2171 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_PIDR6", 1, a, 0, 0, 0, 0, 0); 2172 } 2173 2174 #define typedef_ODY_DSUUBX_CLUSTER_PPU_PIDR6(a) ody_dsuubx_cluster_ppu_pidr6_t 2175 #define bustype_ODY_DSUUBX_CLUSTER_PPU_PIDR6(a) CSR_TYPE_RSL32b 2176 #define basename_ODY_DSUUBX_CLUSTER_PPU_PIDR6(a) "DSUUBX_CLUSTER_PPU_PIDR6" 2177 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_PIDR6(a) 0x0 /* PF_BAR0 */ 2178 #define busnum_ODY_DSUUBX_CLUSTER_PPU_PIDR6(a) (a) 2179 #define arguments_ODY_DSUUBX_CLUSTER_PPU_PIDR6(a) (a), -1, -1, -1 2180 2181 /** 2182 * Register (RSL32b) dsuub#_cluster_ppu_pidr7 2183 * 2184 * DSUUB Cluster PPU Peripheral Identification Register 7 2185 * Provides CoreSight discovery information. 2186 */ 2187 union ody_dsuubx_cluster_ppu_pidr7 { 2188 uint32_t u; 2189 struct ody_dsuubx_cluster_ppu_pidr7_s { 2190 uint32_t reserved_0_31 : 32; 2191 } s; 2192 /* struct ody_dsuubx_cluster_ppu_pidr7_s cn; */ 2193 }; 2194 typedef union ody_dsuubx_cluster_ppu_pidr7 ody_dsuubx_cluster_ppu_pidr7_t; 2195 2196 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PIDR7(uint64_t a) __attribute__ ((pure, always_inline)); 2197 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PIDR7(uint64_t a) 2198 { 2199 if (a <= 89) 2200 return 0x87e2ef030fdcll + 0x1000000ll * ((a) & 0x7f); 2201 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_PIDR7", 1, a, 0, 0, 0, 0, 0); 2202 } 2203 2204 #define typedef_ODY_DSUUBX_CLUSTER_PPU_PIDR7(a) ody_dsuubx_cluster_ppu_pidr7_t 2205 #define bustype_ODY_DSUUBX_CLUSTER_PPU_PIDR7(a) CSR_TYPE_RSL32b 2206 #define basename_ODY_DSUUBX_CLUSTER_PPU_PIDR7(a) "DSUUBX_CLUSTER_PPU_PIDR7" 2207 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_PIDR7(a) 0x0 /* PF_BAR0 */ 2208 #define busnum_ODY_DSUUBX_CLUSTER_PPU_PIDR7(a) (a) 2209 #define arguments_ODY_DSUUBX_CLUSTER_PPU_PIDR7(a) (a), -1, -1, -1 2210 2211 /** 2212 * Register (RSL32b) dsuub#_cluster_ppu_pmer 2213 * 2214 * DSUUB Cluster Power Mode Emulation Enable Register 2215 * This register allows software to enable entry into emulated modes. 2216 */ 2217 union ody_dsuubx_cluster_ppu_pmer { 2218 uint32_t u; 2219 struct ody_dsuubx_cluster_ppu_pmer_s { 2220 uint32_t emu_en : 1; 2221 uint32_t reserved_1_31 : 31; 2222 } s; 2223 /* struct ody_dsuubx_cluster_ppu_pmer_s cn; */ 2224 }; 2225 typedef union ody_dsuubx_cluster_ppu_pmer ody_dsuubx_cluster_ppu_pmer_t; 2226 2227 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PMER(uint64_t a) __attribute__ ((pure, always_inline)); 2228 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PMER(uint64_t a) 2229 { 2230 if (a <= 89) 2231 return 0x87e2ef030004ll + 0x1000000ll * ((a) & 0x7f); 2232 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_PMER", 1, a, 0, 0, 0, 0, 0); 2233 } 2234 2235 #define typedef_ODY_DSUUBX_CLUSTER_PPU_PMER(a) ody_dsuubx_cluster_ppu_pmer_t 2236 #define bustype_ODY_DSUUBX_CLUSTER_PPU_PMER(a) CSR_TYPE_RSL32b 2237 #define basename_ODY_DSUUBX_CLUSTER_PPU_PMER(a) "DSUUBX_CLUSTER_PPU_PMER" 2238 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_PMER(a) 0x0 /* PF_BAR0 */ 2239 #define busnum_ODY_DSUUBX_CLUSTER_PPU_PMER(a) (a) 2240 #define arguments_ODY_DSUUBX_CLUSTER_PPU_PMER(a) (a), -1, -1, -1 2241 2242 /** 2243 * Register (RSL32b) dsuub#_cluster_ppu_ptcr 2244 * 2245 * DSUUB Cluster Power Mode Transition Register 2246 * This register contains settings which affect the behaviour of certain power mode transitions. 2247 */ 2248 union ody_dsuubx_cluster_ppu_ptcr { 2249 uint32_t u; 2250 struct ody_dsuubx_cluster_ppu_ptcr_s { 2251 uint32_t warm_rst_devreqen : 1; 2252 uint32_t dbg_recov_porst_en : 1; 2253 uint32_t reserved_2_31 : 30; 2254 } s; 2255 /* struct ody_dsuubx_cluster_ppu_ptcr_s cn; */ 2256 }; 2257 typedef union ody_dsuubx_cluster_ppu_ptcr ody_dsuubx_cluster_ppu_ptcr_t; 2258 2259 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PTCR(uint64_t a) __attribute__ ((pure, always_inline)); 2260 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PTCR(uint64_t a) 2261 { 2262 if (a <= 89) 2263 return 0x87e2ef030024ll + 0x1000000ll * ((a) & 0x7f); 2264 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_PTCR", 1, a, 0, 0, 0, 0, 0); 2265 } 2266 2267 #define typedef_ODY_DSUUBX_CLUSTER_PPU_PTCR(a) ody_dsuubx_cluster_ppu_ptcr_t 2268 #define bustype_ODY_DSUUBX_CLUSTER_PPU_PTCR(a) CSR_TYPE_RSL32b 2269 #define basename_ODY_DSUUBX_CLUSTER_PPU_PTCR(a) "DSUUBX_CLUSTER_PPU_PTCR" 2270 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_PTCR(a) 0x0 /* PF_BAR0 */ 2271 #define busnum_ODY_DSUUBX_CLUSTER_PPU_PTCR(a) (a) 2272 #define arguments_ODY_DSUUBX_CLUSTER_PPU_PTCR(a) (a), -1, -1, -1 2273 2274 /** 2275 * Register (RSL32b) dsuub#_cluster_ppu_pwcr 2276 * 2277 * DSUUB Cluster Power Configuration Register 2278 * This register controls enabling and disabling of hardware control inputs to the PPU. 2279 * 2280 * Before software programs the DEVREQEN bits it must configure the PPU for static 2281 * transitions and ensure the requested power mode has been reached, this means that no 2282 * further transitions can occur, otherwise behavior is UNPREDICTABLE. 2283 * 2284 * The PWR_DEVACTIVEEN and OP_DEVACTIVEEN fields in this register control the ability of the 2285 * DEVACTIVE inputs to initiate power mode transitions, but not the ability to generate input edge 2286 * interrupt events. 2287 */ 2288 union ody_dsuubx_cluster_ppu_pwcr { 2289 uint32_t u; 2290 struct ody_dsuubx_cluster_ppu_pwcr_s { 2291 uint32_t devreqen : 1; 2292 uint32_t reserved_1_8 : 8; 2293 uint32_t pwr_devactiveen1 : 1; 2294 uint32_t pwr_devactiveen2 : 1; 2295 uint32_t pwr_devactiveen3 : 1; 2296 uint32_t reserved_12 : 1; 2297 uint32_t pwr_devactiveen5 : 1; 2298 uint32_t reserved_14 : 1; 2299 uint32_t pwr_devactiveen7 : 1; 2300 uint32_t pwr_devactiveen8 : 1; 2301 uint32_t pwr_devactiveen9 : 1; 2302 uint32_t pwr_devactiveen10 : 1; 2303 uint32_t reserved_19_23 : 5; 2304 uint32_t op_devactiveen0 : 1; 2305 uint32_t op_devactiveen1 : 1; 2306 uint32_t op_devactiveen2 : 1; 2307 uint32_t reserved_27_31 : 5; 2308 } s; 2309 /* struct ody_dsuubx_cluster_ppu_pwcr_s cn; */ 2310 }; 2311 typedef union ody_dsuubx_cluster_ppu_pwcr ody_dsuubx_cluster_ppu_pwcr_t; 2312 2313 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PWCR(uint64_t a) __attribute__ ((pure, always_inline)); 2314 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PWCR(uint64_t a) 2315 { 2316 if (a <= 89) 2317 return 0x87e2ef030020ll + 0x1000000ll * ((a) & 0x7f); 2318 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_PWCR", 1, a, 0, 0, 0, 0, 0); 2319 } 2320 2321 #define typedef_ODY_DSUUBX_CLUSTER_PPU_PWCR(a) ody_dsuubx_cluster_ppu_pwcr_t 2322 #define bustype_ODY_DSUUBX_CLUSTER_PPU_PWCR(a) CSR_TYPE_RSL32b 2323 #define basename_ODY_DSUUBX_CLUSTER_PPU_PWCR(a) "DSUUBX_CLUSTER_PPU_PWCR" 2324 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_PWCR(a) 0x0 /* PF_BAR0 */ 2325 #define busnum_ODY_DSUUBX_CLUSTER_PPU_PWCR(a) (a) 2326 #define arguments_ODY_DSUUBX_CLUSTER_PPU_PWCR(a) (a), -1, -1, -1 2327 2328 /** 2329 * Register (RSL32b) dsuub#_cluster_ppu_pwpr 2330 * 2331 * DSUUB Cluster Power Policy Register 2332 * This register enables software to program both power and operating mode policy. It also contains 2333 * related settings including the enable for dynamic transitions and the lock enable. 2334 * 2335 * This register does not reflect the current power mode value. The current power mode of the 2336 * domain is reflected in the Power Status Register (DSUUB_PPU_PWSR). 2337 */ 2338 union ody_dsuubx_cluster_ppu_pwpr { 2339 uint32_t u; 2340 struct ody_dsuubx_cluster_ppu_pwpr_s { 2341 uint32_t pwr_policy : 4; 2342 uint32_t reserved_4_7 : 4; 2343 uint32_t pwr_dyn_en : 1; 2344 uint32_t reserved_9_11 : 3; 2345 uint32_t lock_en : 1; 2346 uint32_t reserved_13_15 : 3; 2347 uint32_t op_policy : 4; 2348 uint32_t reserved_20_23 : 4; 2349 uint32_t op_dyn_en : 1; 2350 uint32_t reserved_25_31 : 7; 2351 } s; 2352 /* struct ody_dsuubx_cluster_ppu_pwpr_s cn; */ 2353 }; 2354 typedef union ody_dsuubx_cluster_ppu_pwpr ody_dsuubx_cluster_ppu_pwpr_t; 2355 2356 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PWPR(uint64_t a) __attribute__ ((pure, always_inline)); 2357 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PWPR(uint64_t a) 2358 { 2359 if (a <= 89) 2360 return 0x87e2ef030000ll + 0x1000000ll * ((a) & 0x7f); 2361 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_PWPR", 1, a, 0, 0, 0, 0, 0); 2362 } 2363 2364 #define typedef_ODY_DSUUBX_CLUSTER_PPU_PWPR(a) ody_dsuubx_cluster_ppu_pwpr_t 2365 #define bustype_ODY_DSUUBX_CLUSTER_PPU_PWPR(a) CSR_TYPE_RSL32b 2366 #define basename_ODY_DSUUBX_CLUSTER_PPU_PWPR(a) "DSUUBX_CLUSTER_PPU_PWPR" 2367 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_PWPR(a) 0x0 /* PF_BAR0 */ 2368 #define busnum_ODY_DSUUBX_CLUSTER_PPU_PWPR(a) (a) 2369 #define arguments_ODY_DSUUBX_CLUSTER_PPU_PWPR(a) (a), -1, -1, -1 2370 2371 /** 2372 * Register (RSL32b) dsuub#_cluster_ppu_pwsr 2373 * 2374 * DSUUB Cluster Power Status Register 2375 * This read-only register contains status information for the power mode, operating mode, dynamic 2376 * transitions, and lock feature. 2377 */ 2378 union ody_dsuubx_cluster_ppu_pwsr { 2379 uint32_t u; 2380 struct ody_dsuubx_cluster_ppu_pwsr_s { 2381 uint32_t pwr_status : 4; 2382 uint32_t reserved_4_7 : 4; 2383 uint32_t pwr_dyn_status : 1; 2384 uint32_t reserved_9_11 : 3; 2385 uint32_t lock_status : 1; 2386 uint32_t reserved_13_15 : 3; 2387 uint32_t op_status : 4; 2388 uint32_t reserved_20_23 : 4; 2389 uint32_t op_dyn_status : 1; 2390 uint32_t reserved_25_31 : 7; 2391 } s; 2392 /* struct ody_dsuubx_cluster_ppu_pwsr_s cn; */ 2393 }; 2394 typedef union ody_dsuubx_cluster_ppu_pwsr ody_dsuubx_cluster_ppu_pwsr_t; 2395 2396 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PWSR(uint64_t a) __attribute__ ((pure, always_inline)); 2397 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_PWSR(uint64_t a) 2398 { 2399 if (a <= 89) 2400 return 0x87e2ef030008ll + 0x1000000ll * ((a) & 0x7f); 2401 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_PWSR", 1, a, 0, 0, 0, 0, 0); 2402 } 2403 2404 #define typedef_ODY_DSUUBX_CLUSTER_PPU_PWSR(a) ody_dsuubx_cluster_ppu_pwsr_t 2405 #define bustype_ODY_DSUUBX_CLUSTER_PPU_PWSR(a) CSR_TYPE_RSL32b 2406 #define basename_ODY_DSUUBX_CLUSTER_PPU_PWSR(a) "DSUUBX_CLUSTER_PPU_PWSR" 2407 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_PWSR(a) 0x0 /* PF_BAR0 */ 2408 #define busnum_ODY_DSUUBX_CLUSTER_PPU_PWSR(a) (a) 2409 #define arguments_ODY_DSUUBX_CLUSTER_PPU_PWSR(a) (a), -1, -1, -1 2410 2411 /** 2412 * Register (RSL32b) dsuub#_cluster_ppu_stsr 2413 * 2414 * DSUUB Cluster Stored Status Register 2415 * This register is reserved for P-Channel PPUs. 2416 */ 2417 union ody_dsuubx_cluster_ppu_stsr { 2418 uint32_t u; 2419 struct ody_dsuubx_cluster_ppu_stsr_s { 2420 uint32_t stored_devdeny : 8; 2421 uint32_t reserved_8_31 : 24; 2422 } s; 2423 /* struct ody_dsuubx_cluster_ppu_stsr_s cn; */ 2424 }; 2425 typedef union ody_dsuubx_cluster_ppu_stsr ody_dsuubx_cluster_ppu_stsr_t; 2426 2427 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_STSR(uint64_t a) __attribute__ ((pure, always_inline)); 2428 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_STSR(uint64_t a) 2429 { 2430 if (a <= 89) 2431 return 0x87e2ef030018ll + 0x1000000ll * ((a) & 0x7f); 2432 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_STSR", 1, a, 0, 0, 0, 0, 0); 2433 } 2434 2435 #define typedef_ODY_DSUUBX_CLUSTER_PPU_STSR(a) ody_dsuubx_cluster_ppu_stsr_t 2436 #define bustype_ODY_DSUUBX_CLUSTER_PPU_STSR(a) CSR_TYPE_RSL32b 2437 #define basename_ODY_DSUUBX_CLUSTER_PPU_STSR(a) "DSUUBX_CLUSTER_PPU_STSR" 2438 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_STSR(a) 0x0 /* PF_BAR0 */ 2439 #define busnum_ODY_DSUUBX_CLUSTER_PPU_STSR(a) (a) 2440 #define arguments_ODY_DSUUBX_CLUSTER_PPU_STSR(a) (a), -1, -1, -1 2441 2442 /** 2443 * Register (RSL32b) dsuub#_cluster_ppu_unlk 2444 * 2445 * DSUUB Cluster Unlock Register 2446 * This register allows software to unlock the PPU from a locked power mode. 2447 */ 2448 union ody_dsuubx_cluster_ppu_unlk { 2449 uint32_t u; 2450 struct ody_dsuubx_cluster_ppu_unlk_s { 2451 uint32_t unlock : 1; 2452 uint32_t reserved_1_31 : 31; 2453 } s; 2454 /* struct ody_dsuubx_cluster_ppu_unlk_s cn; */ 2455 }; 2456 typedef union ody_dsuubx_cluster_ppu_unlk ody_dsuubx_cluster_ppu_unlk_t; 2457 2458 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_UNLK(uint64_t a) __attribute__ ((pure, always_inline)); 2459 static inline uint64_t ODY_DSUUBX_CLUSTER_PPU_UNLK(uint64_t a) 2460 { 2461 if (a <= 89) 2462 return 0x87e2ef03001cll + 0x1000000ll * ((a) & 0x7f); 2463 __ody_csr_fatal("DSUUBX_CLUSTER_PPU_UNLK", 1, a, 0, 0, 0, 0, 0); 2464 } 2465 2466 #define typedef_ODY_DSUUBX_CLUSTER_PPU_UNLK(a) ody_dsuubx_cluster_ppu_unlk_t 2467 #define bustype_ODY_DSUUBX_CLUSTER_PPU_UNLK(a) CSR_TYPE_RSL32b 2468 #define basename_ODY_DSUUBX_CLUSTER_PPU_UNLK(a) "DSUUBX_CLUSTER_PPU_UNLK" 2469 #define device_bar_ODY_DSUUBX_CLUSTER_PPU_UNLK(a) 0x0 /* PF_BAR0 */ 2470 #define busnum_ODY_DSUUBX_CLUSTER_PPU_UNLK(a) (a) 2471 #define arguments_ODY_DSUUBX_CLUSTER_PPU_UNLK(a) (a), -1, -1, -1 2472 2473 /** 2474 * Register (RSL) dsuub#_clusterbusqos 2475 * 2476 * DSUUB Cluster Bus QoS Control Register 2477 * Determines the value driven on the CHI bus QoS field. 2478 */ 2479 union ody_dsuubx_clusterbusqos { 2480 uint64_t u; 2481 struct ody_dsuubx_clusterbusqos_s { 2482 uint64_t qos : 4; 2483 uint64_t reserved_4_63 : 60; 2484 } s; 2485 /* struct ody_dsuubx_clusterbusqos_s cn; */ 2486 }; 2487 typedef union ody_dsuubx_clusterbusqos ody_dsuubx_clusterbusqos_t; 2488 2489 static inline uint64_t ODY_DSUUBX_CLUSTERBUSQOS(uint64_t a) __attribute__ ((pure, always_inline)); 2490 static inline uint64_t ODY_DSUUBX_CLUSTERBUSQOS(uint64_t a) 2491 { 2492 if (a <= 89) 2493 return 0x87e2ef000048ll + 0x1000000ll * ((a) & 0x7f); 2494 __ody_csr_fatal("DSUUBX_CLUSTERBUSQOS", 1, a, 0, 0, 0, 0, 0); 2495 } 2496 2497 #define typedef_ODY_DSUUBX_CLUSTERBUSQOS(a) ody_dsuubx_clusterbusqos_t 2498 #define bustype_ODY_DSUUBX_CLUSTERBUSQOS(a) CSR_TYPE_RSL 2499 #define basename_ODY_DSUUBX_CLUSTERBUSQOS(a) "DSUUBX_CLUSTERBUSQOS" 2500 #define device_bar_ODY_DSUUBX_CLUSTERBUSQOS(a) 0x0 /* PF_BAR0 */ 2501 #define busnum_ODY_DSUUBX_CLUSTERBUSQOS(a) (a) 2502 #define arguments_ODY_DSUUBX_CLUSTERBUSQOS(a) (a), -1, -1, -1 2503 2504 /** 2505 * Register (RSL) dsuub#_clustercfr 2506 * 2507 * DSUUB Cluster Configuration Register 2508 * Contains details of the hardware configuration of the cluster. 2509 */ 2510 union ody_dsuubx_clustercfr { 2511 uint64_t u; 2512 struct ody_dsuubx_clustercfr_s { 2513 uint64_t numcore : 3; 2514 uint64_t reserved_3 : 1; 2515 uint64_t numpe : 4; 2516 uint64_t reserved_8 : 1; 2517 uint64_t l3 : 1; 2518 uint64_t wrlat : 2; 2519 uint64_t rdlat : 1; 2520 uint64_t rdslc : 1; 2521 uint64_t ecc : 1; 2522 uint64_t nummas : 2; 2523 uint64_t mas : 1; 2524 uint64_t reserved_18 : 1; 2525 uint64_t acpw : 1; 2526 uint64_t acp : 1; 2527 uint64_t reserved_21 : 1; 2528 uint64_t ppw : 1; 2529 uint64_t pp : 1; 2530 uint64_t reserved_24 : 1; 2531 uint64_t trsh : 2; 2532 uint64_t trsv : 2; 2533 uint64_t crs : 16; 2534 uint64_t reserved_45_50 : 6; 2535 uint64_t l3slc : 3; 2536 uint64_t reserved_54 : 1; 2537 uint64_t sfidx : 4; 2538 uint64_t sfway : 2; 2539 uint64_t nodes : 3; 2540 } s; 2541 /* struct ody_dsuubx_clustercfr_s cn; */ 2542 }; 2543 typedef union ody_dsuubx_clustercfr ody_dsuubx_clustercfr_t; 2544 2545 static inline uint64_t ODY_DSUUBX_CLUSTERCFR(uint64_t a) __attribute__ ((pure, always_inline)); 2546 static inline uint64_t ODY_DSUUBX_CLUSTERCFR(uint64_t a) 2547 { 2548 if (a <= 89) 2549 return 0x87e2ef000050ll + 0x1000000ll * ((a) & 0x7f); 2550 __ody_csr_fatal("DSUUBX_CLUSTERCFR", 1, a, 0, 0, 0, 0, 0); 2551 } 2552 2553 #define typedef_ODY_DSUUBX_CLUSTERCFR(a) ody_dsuubx_clustercfr_t 2554 #define bustype_ODY_DSUUBX_CLUSTERCFR(a) CSR_TYPE_RSL 2555 #define basename_ODY_DSUUBX_CLUSTERCFR(a) "DSUUBX_CLUSTERCFR" 2556 #define device_bar_ODY_DSUUBX_CLUSTERCFR(a) 0x0 /* PF_BAR0 */ 2557 #define busnum_ODY_DSUUBX_CLUSTERCFR(a) (a) 2558 #define arguments_ODY_DSUUBX_CLUSTERCFR(a) (a), -1, -1, -1 2559 2560 /** 2561 * Register (RSL) dsuub#_clusterectlr 2562 * 2563 * DSUUB Cluster Extended Control Register 2564 * This register should be used for dynamically changing implementation specific 2565 * control bits. 2566 */ 2567 union ody_dsuubx_clusterectlr { 2568 uint64_t u; 2569 struct ody_dsuubx_clusterectlr_s { 2570 uint64_t reserved_0 : 1; 2571 uint64_t enpoisnpp : 1; 2572 uint64_t disevpwr : 1; 2573 uint64_t disevict : 1; 2574 uint64_t enpoisn : 1; 2575 uint64_t nol3stash : 2; 2576 uint64_t disatom : 1; 2577 uint64_t pfmtch : 3; 2578 uint64_t reserved_11_14 : 4; 2579 uint64_t l3wrlat : 2; 2580 uint64_t l3rdlat : 1; 2581 uint64_t reserved_18_41 : 24; 2582 uint64_t dsfp : 1; 2583 uint64_t efc : 1; 2584 uint64_t dcc : 2; 2585 uint64_t reserved_46_63 : 18; 2586 } s; 2587 /* struct ody_dsuubx_clusterectlr_s cn; */ 2588 }; 2589 typedef union ody_dsuubx_clusterectlr ody_dsuubx_clusterectlr_t; 2590 2591 static inline uint64_t ODY_DSUUBX_CLUSTERECTLR(uint64_t a) __attribute__ ((pure, always_inline)); 2592 static inline uint64_t ODY_DSUUBX_CLUSTERECTLR(uint64_t a) 2593 { 2594 if (a <= 89) 2595 return 0x87e2ef000060ll + 0x1000000ll * ((a) & 0x7f); 2596 __ody_csr_fatal("DSUUBX_CLUSTERECTLR", 1, a, 0, 0, 0, 0, 0); 2597 } 2598 2599 #define typedef_ODY_DSUUBX_CLUSTERECTLR(a) ody_dsuubx_clusterectlr_t 2600 #define bustype_ODY_DSUUBX_CLUSTERECTLR(a) CSR_TYPE_RSL 2601 #define basename_ODY_DSUUBX_CLUSTERECTLR(a) "DSUUBX_CLUSTERECTLR" 2602 #define device_bar_ODY_DSUUBX_CLUSTERECTLR(a) 0x0 /* PF_BAR0 */ 2603 #define busnum_ODY_DSUUBX_CLUSTERECTLR(a) (a) 2604 #define arguments_ODY_DSUUBX_CLUSTERECTLR(a) (a), -1, -1, -1 2605 2606 /** 2607 * Register (RSL) dsuub#_clusteridr 2608 * 2609 * DSUUB Cluster Main Revision Register 2610 * Holds the revision and patch level of the cluster. 2611 */ 2612 union ody_dsuubx_clusteridr { 2613 uint64_t u; 2614 struct ody_dsuubx_clusteridr_s { 2615 uint64_t revision : 4; 2616 uint64_t variant : 4; 2617 uint64_t reserved_8_63 : 56; 2618 } s; 2619 /* struct ody_dsuubx_clusteridr_s cn; */ 2620 }; 2621 typedef union ody_dsuubx_clusteridr ody_dsuubx_clusteridr_t; 2622 2623 static inline uint64_t ODY_DSUUBX_CLUSTERIDR(uint64_t a) __attribute__ ((pure, always_inline)); 2624 static inline uint64_t ODY_DSUUBX_CLUSTERIDR(uint64_t a) 2625 { 2626 if (a <= 89) 2627 return 0x87e2ef000000ll + 0x1000000ll * ((a) & 0x7f); 2628 __ody_csr_fatal("DSUUBX_CLUSTERIDR", 1, a, 0, 0, 0, 0, 0); 2629 } 2630 2631 #define typedef_ODY_DSUUBX_CLUSTERIDR(a) ody_dsuubx_clusteridr_t 2632 #define bustype_ODY_DSUUBX_CLUSTERIDR(a) CSR_TYPE_RSL 2633 #define basename_ODY_DSUUBX_CLUSTERIDR(a) "DSUUBX_CLUSTERIDR" 2634 #define device_bar_ODY_DSUUBX_CLUSTERIDR(a) 0x0 /* PF_BAR0 */ 2635 #define busnum_ODY_DSUUBX_CLUSTERIDR(a) (a) 2636 #define arguments_ODY_DSUUBX_CLUSTERIDR(a) (a), -1, -1, -1 2637 2638 /** 2639 * Register (RSL) dsuub#_clusterl3dnth0 2640 * 2641 * DSUUB Cluster L3 Downsize Threshold0 Register 2642 * This register is intended for use in algorithms for determining when to power up or 2643 * down cache portions. 2644 */ 2645 union ody_dsuubx_clusterl3dnth0 { 2646 uint64_t u; 2647 struct ody_dsuubx_clusterl3dnth0_s { 2648 uint64_t dnth0 : 32; 2649 uint64_t reserved_32_63 : 32; 2650 } s; 2651 /* struct ody_dsuubx_clusterl3dnth0_s cn; */ 2652 }; 2653 typedef union ody_dsuubx_clusterl3dnth0 ody_dsuubx_clusterl3dnth0_t; 2654 2655 static inline uint64_t ODY_DSUUBX_CLUSTERL3DNTH0(uint64_t a) __attribute__ ((pure, always_inline)); 2656 static inline uint64_t ODY_DSUUBX_CLUSTERL3DNTH0(uint64_t a) 2657 { 2658 if (a <= 89) 2659 return 0x87e2ef000028ll + 0x1000000ll * ((a) & 0x7f); 2660 __ody_csr_fatal("DSUUBX_CLUSTERL3DNTH0", 1, a, 0, 0, 0, 0, 0); 2661 } 2662 2663 #define typedef_ODY_DSUUBX_CLUSTERL3DNTH0(a) ody_dsuubx_clusterl3dnth0_t 2664 #define bustype_ODY_DSUUBX_CLUSTERL3DNTH0(a) CSR_TYPE_RSL 2665 #define basename_ODY_DSUUBX_CLUSTERL3DNTH0(a) "DSUUBX_CLUSTERL3DNTH0" 2666 #define device_bar_ODY_DSUUBX_CLUSTERL3DNTH0(a) 0x0 /* PF_BAR0 */ 2667 #define busnum_ODY_DSUUBX_CLUSTERL3DNTH0(a) (a) 2668 #define arguments_ODY_DSUUBX_CLUSTERL3DNTH0(a) (a), -1, -1, -1 2669 2670 /** 2671 * Register (RSL) dsuub#_clusterl3dnth1 2672 * 2673 * DSUUB Cluster L3 Downsize Threshold1 Register 2674 * This register is intended for use in algorithms for determining when to power up or 2675 * down cache portions. 2676 */ 2677 union ody_dsuubx_clusterl3dnth1 { 2678 uint64_t u; 2679 struct ody_dsuubx_clusterl3dnth1_s { 2680 uint64_t dnth0 : 32; 2681 uint64_t reserved_32_63 : 32; 2682 } s; 2683 /* struct ody_dsuubx_clusterl3dnth1_s cn; */ 2684 }; 2685 typedef union ody_dsuubx_clusterl3dnth1 ody_dsuubx_clusterl3dnth1_t; 2686 2687 static inline uint64_t ODY_DSUUBX_CLUSTERL3DNTH1(uint64_t a) __attribute__ ((pure, always_inline)); 2688 static inline uint64_t ODY_DSUUBX_CLUSTERL3DNTH1(uint64_t a) 2689 { 2690 if (a <= 89) 2691 return 0x87e2ef000030ll + 0x1000000ll * ((a) & 0x7f); 2692 __ody_csr_fatal("DSUUBX_CLUSTERL3DNTH1", 1, a, 0, 0, 0, 0, 0); 2693 } 2694 2695 #define typedef_ODY_DSUUBX_CLUSTERL3DNTH1(a) ody_dsuubx_clusterl3dnth1_t 2696 #define bustype_ODY_DSUUBX_CLUSTERL3DNTH1(a) CSR_TYPE_RSL 2697 #define basename_ODY_DSUUBX_CLUSTERL3DNTH1(a) "DSUUBX_CLUSTERL3DNTH1" 2698 #define device_bar_ODY_DSUUBX_CLUSTERL3DNTH1(a) 0x0 /* PF_BAR0 */ 2699 #define busnum_ODY_DSUUBX_CLUSTERL3DNTH1(a) (a) 2700 #define arguments_ODY_DSUUBX_CLUSTERL3DNTH1(a) (a), -1, -1, -1 2701 2702 /** 2703 * Register (RSL) dsuub#_clusterl3hit 2704 * 2705 * DSUUB Cluster L3 Hit Counter Register 2706 * This register is intended for use in algorithms for determining when to power up or 2707 * down cache portions. 2708 */ 2709 union ody_dsuubx_clusterl3hit { 2710 uint64_t u; 2711 struct ody_dsuubx_clusterl3hit_s { 2712 uint64_t hitcnt : 32; 2713 uint64_t reserved_32_63 : 32; 2714 } s; 2715 /* struct ody_dsuubx_clusterl3hit_s cn; */ 2716 }; 2717 typedef union ody_dsuubx_clusterl3hit ody_dsuubx_clusterl3hit_t; 2718 2719 static inline uint64_t ODY_DSUUBX_CLUSTERL3HIT(uint64_t a) __attribute__ ((pure, always_inline)); 2720 static inline uint64_t ODY_DSUUBX_CLUSTERL3HIT(uint64_t a) 2721 { 2722 if (a <= 89) 2723 return 0x87e2ef000018ll + 0x1000000ll * ((a) & 0x7f); 2724 __ody_csr_fatal("DSUUBX_CLUSTERL3HIT", 1, a, 0, 0, 0, 0, 0); 2725 } 2726 2727 #define typedef_ODY_DSUUBX_CLUSTERL3HIT(a) ody_dsuubx_clusterl3hit_t 2728 #define bustype_ODY_DSUUBX_CLUSTERL3HIT(a) CSR_TYPE_RSL 2729 #define basename_ODY_DSUUBX_CLUSTERL3HIT(a) "DSUUBX_CLUSTERL3HIT" 2730 #define device_bar_ODY_DSUUBX_CLUSTERL3HIT(a) 0x0 /* PF_BAR0 */ 2731 #define busnum_ODY_DSUUBX_CLUSTERL3HIT(a) (a) 2732 #define arguments_ODY_DSUUBX_CLUSTERL3HIT(a) (a), -1, -1, -1 2733 2734 /** 2735 * Register (RSL) dsuub#_clusterl3miss 2736 * 2737 * DSUUB Cluster L3 Miss Counter Register 2738 * This register is intended for use in algorithms for determining when to power up or 2739 * down cache portions. 2740 */ 2741 union ody_dsuubx_clusterl3miss { 2742 uint64_t u; 2743 struct ody_dsuubx_clusterl3miss_s { 2744 uint64_t misscnt : 32; 2745 uint64_t reserved_32_63 : 32; 2746 } s; 2747 /* struct ody_dsuubx_clusterl3miss_s cn; */ 2748 }; 2749 typedef union ody_dsuubx_clusterl3miss ody_dsuubx_clusterl3miss_t; 2750 2751 static inline uint64_t ODY_DSUUBX_CLUSTERL3MISS(uint64_t a) __attribute__ ((pure, always_inline)); 2752 static inline uint64_t ODY_DSUUBX_CLUSTERL3MISS(uint64_t a) 2753 { 2754 if (a <= 89) 2755 return 0x87e2ef000020ll + 0x1000000ll * ((a) & 0x7f); 2756 __ody_csr_fatal("DSUUBX_CLUSTERL3MISS", 1, a, 0, 0, 0, 0, 0); 2757 } 2758 2759 #define typedef_ODY_DSUUBX_CLUSTERL3MISS(a) ody_dsuubx_clusterl3miss_t 2760 #define bustype_ODY_DSUUBX_CLUSTERL3MISS(a) CSR_TYPE_RSL 2761 #define basename_ODY_DSUUBX_CLUSTERL3MISS(a) "DSUUBX_CLUSTERL3MISS" 2762 #define device_bar_ODY_DSUUBX_CLUSTERL3MISS(a) 0x0 /* PF_BAR0 */ 2763 #define busnum_ODY_DSUUBX_CLUSTERL3MISS(a) (a) 2764 #define arguments_ODY_DSUUBX_CLUSTERL3MISS(a) (a), -1, -1, -1 2765 2766 /** 2767 * Register (RSL) dsuub#_clusterl3upth0 2768 * 2769 * DSUUB Cluster L3 Upsize Threshold0 Register 2770 * This register is intended for use in algorithms for determining when to power up or 2771 * down cache portions. 2772 */ 2773 union ody_dsuubx_clusterl3upth0 { 2774 uint64_t u; 2775 struct ody_dsuubx_clusterl3upth0_s { 2776 uint64_t upth0 : 32; 2777 uint64_t reserved_32_63 : 32; 2778 } s; 2779 /* struct ody_dsuubx_clusterl3upth0_s cn; */ 2780 }; 2781 typedef union ody_dsuubx_clusterl3upth0 ody_dsuubx_clusterl3upth0_t; 2782 2783 static inline uint64_t ODY_DSUUBX_CLUSTERL3UPTH0(uint64_t a) __attribute__ ((pure, always_inline)); 2784 static inline uint64_t ODY_DSUUBX_CLUSTERL3UPTH0(uint64_t a) 2785 { 2786 if (a <= 89) 2787 return 0x87e2ef000038ll + 0x1000000ll * ((a) & 0x7f); 2788 __ody_csr_fatal("DSUUBX_CLUSTERL3UPTH0", 1, a, 0, 0, 0, 0, 0); 2789 } 2790 2791 #define typedef_ODY_DSUUBX_CLUSTERL3UPTH0(a) ody_dsuubx_clusterl3upth0_t 2792 #define bustype_ODY_DSUUBX_CLUSTERL3UPTH0(a) CSR_TYPE_RSL 2793 #define basename_ODY_DSUUBX_CLUSTERL3UPTH0(a) "DSUUBX_CLUSTERL3UPTH0" 2794 #define device_bar_ODY_DSUUBX_CLUSTERL3UPTH0(a) 0x0 /* PF_BAR0 */ 2795 #define busnum_ODY_DSUUBX_CLUSTERL3UPTH0(a) (a) 2796 #define arguments_ODY_DSUUBX_CLUSTERL3UPTH0(a) (a), -1, -1, -1 2797 2798 /** 2799 * Register (RSL) dsuub#_clusterl3upth1 2800 * 2801 * DSUUB Cluster L3 Upsize Threshold1 Register 2802 * This register is intended for use in algorithms for determining when to power up or 2803 * down cache portions. 2804 */ 2805 union ody_dsuubx_clusterl3upth1 { 2806 uint64_t u; 2807 struct ody_dsuubx_clusterl3upth1_s { 2808 uint64_t upth1 : 32; 2809 uint64_t reserved_32_63 : 32; 2810 } s; 2811 /* struct ody_dsuubx_clusterl3upth1_s cn; */ 2812 }; 2813 typedef union ody_dsuubx_clusterl3upth1 ody_dsuubx_clusterl3upth1_t; 2814 2815 static inline uint64_t ODY_DSUUBX_CLUSTERL3UPTH1(uint64_t a) __attribute__ ((pure, always_inline)); 2816 static inline uint64_t ODY_DSUUBX_CLUSTERL3UPTH1(uint64_t a) 2817 { 2818 if (a <= 89) 2819 return 0x87e2ef000040ll + 0x1000000ll * ((a) & 0x7f); 2820 __ody_csr_fatal("DSUUBX_CLUSTERL3UPTH1", 1, a, 0, 0, 0, 0, 0); 2821 } 2822 2823 #define typedef_ODY_DSUUBX_CLUSTERL3UPTH1(a) ody_dsuubx_clusterl3upth1_t 2824 #define bustype_ODY_DSUUBX_CLUSTERL3UPTH1(a) CSR_TYPE_RSL 2825 #define basename_ODY_DSUUBX_CLUSTERL3UPTH1(a) "DSUUBX_CLUSTERL3UPTH1" 2826 #define device_bar_ODY_DSUUBX_CLUSTERL3UPTH1(a) 0x0 /* PF_BAR0 */ 2827 #define busnum_ODY_DSUUBX_CLUSTERL3UPTH1(a) (a) 2828 #define arguments_ODY_DSUUBX_CLUSTERL3UPTH1(a) (a), -1, -1, -1 2829 2830 /** 2831 * Register (RSL) dsuub#_clusterpwrctlr 2832 * 2833 * DSUUB Cluster Power Control Register 2834 * This register controls power features of the cluster. 2835 */ 2836 union ody_dsuubx_clusterpwrctlr { 2837 uint64_t u; 2838 struct ody_dsuubx_clusterpwrctlr_s { 2839 uint64_t retctl : 3; 2840 uint64_t reserved_3 : 1; 2841 uint64_t prtnrq : 2; 2842 uint64_t slcrq : 1; 2843 uint64_t reserved_7_11 : 5; 2844 uint64_t autoprtn : 3; 2845 uint64_t reserved_15_17 : 3; 2846 uint64_t lslp : 1; 2847 uint64_t reserved_19_63 : 45; 2848 } s; 2849 /* struct ody_dsuubx_clusterpwrctlr_s cn; */ 2850 }; 2851 typedef union ody_dsuubx_clusterpwrctlr ody_dsuubx_clusterpwrctlr_t; 2852 2853 static inline uint64_t ODY_DSUUBX_CLUSTERPWRCTLR(uint64_t a) __attribute__ ((pure, always_inline)); 2854 static inline uint64_t ODY_DSUUBX_CLUSTERPWRCTLR(uint64_t a) 2855 { 2856 if (a <= 89) 2857 return 0x87e2ef000010ll + 0x1000000ll * ((a) & 0x7f); 2858 __ody_csr_fatal("DSUUBX_CLUSTERPWRCTLR", 1, a, 0, 0, 0, 0, 0); 2859 } 2860 2861 #define typedef_ODY_DSUUBX_CLUSTERPWRCTLR(a) ody_dsuubx_clusterpwrctlr_t 2862 #define bustype_ODY_DSUUBX_CLUSTERPWRCTLR(a) CSR_TYPE_RSL 2863 #define basename_ODY_DSUUBX_CLUSTERPWRCTLR(a) "DSUUBX_CLUSTERPWRCTLR" 2864 #define device_bar_ODY_DSUUBX_CLUSTERPWRCTLR(a) 0x0 /* PF_BAR0 */ 2865 #define busnum_ODY_DSUUBX_CLUSTERPWRCTLR(a) (a) 2866 #define arguments_ODY_DSUUBX_CLUSTERPWRCTLR(a) (a), -1, -1, -1 2867 2868 /** 2869 * Register (RSL) dsuub#_clusterrevidr 2870 * 2871 * DSUUB Cluster ECO ID Register 2872 * Enables ECO patches to be applied to the cluster level to be identified by software. 2873 */ 2874 union ody_dsuubx_clusterrevidr { 2875 uint64_t u; 2876 struct ody_dsuubx_clusterrevidr_s { 2877 uint64_t ecoid : 64; 2878 } s; 2879 /* struct ody_dsuubx_clusterrevidr_s cn; */ 2880 }; 2881 typedef union ody_dsuubx_clusterrevidr ody_dsuubx_clusterrevidr_t; 2882 2883 static inline uint64_t ODY_DSUUBX_CLUSTERREVIDR(uint64_t a) __attribute__ ((pure, always_inline)); 2884 static inline uint64_t ODY_DSUUBX_CLUSTERREVIDR(uint64_t a) 2885 { 2886 if (a <= 89) 2887 return 0x87e2ef000008ll + 0x1000000ll * ((a) & 0x7f); 2888 __ody_csr_fatal("DSUUBX_CLUSTERREVIDR", 1, a, 0, 0, 0, 0, 0); 2889 } 2890 2891 #define typedef_ODY_DSUUBX_CLUSTERREVIDR(a) ody_dsuubx_clusterrevidr_t 2892 #define bustype_ODY_DSUUBX_CLUSTERREVIDR(a) CSR_TYPE_RSL 2893 #define basename_ODY_DSUUBX_CLUSTERREVIDR(a) "DSUUBX_CLUSTERREVIDR" 2894 #define device_bar_ODY_DSUUBX_CLUSTERREVIDR(a) 0x0 /* PF_BAR0 */ 2895 #define busnum_ODY_DSUUBX_CLUSTERREVIDR(a) (a) 2896 #define arguments_ODY_DSUUBX_CLUSTERREVIDR(a) (a), -1, -1, -1 2897 2898 /** 2899 * Register (RSL32b) dsuub#_core_ppu_aidr 2900 * 2901 * DSUUB Core Architecture Identification Register 2902 * This register identifies the PPU architecture revision. 2903 */ 2904 union ody_dsuubx_core_ppu_aidr { 2905 uint32_t u; 2906 struct ody_dsuubx_core_ppu_aidr_s { 2907 uint32_t arch_rev_minor : 4; 2908 uint32_t arch_rev_major : 4; 2909 uint32_t reserved_8_31 : 24; 2910 } s; 2911 /* struct ody_dsuubx_core_ppu_aidr_s cn; */ 2912 }; 2913 typedef union ody_dsuubx_core_ppu_aidr ody_dsuubx_core_ppu_aidr_t; 2914 2915 static inline uint64_t ODY_DSUUBX_CORE_PPU_AIDR(uint64_t a) __attribute__ ((pure, always_inline)); 2916 static inline uint64_t ODY_DSUUBX_CORE_PPU_AIDR(uint64_t a) 2917 { 2918 if (a <= 89) 2919 return 0x87e2ef080fccll + 0x1000000ll * ((a) & 0x7f); 2920 __ody_csr_fatal("DSUUBX_CORE_PPU_AIDR", 1, a, 0, 0, 0, 0, 0); 2921 } 2922 2923 #define typedef_ODY_DSUUBX_CORE_PPU_AIDR(a) ody_dsuubx_core_ppu_aidr_t 2924 #define bustype_ODY_DSUUBX_CORE_PPU_AIDR(a) CSR_TYPE_RSL32b 2925 #define basename_ODY_DSUUBX_CORE_PPU_AIDR(a) "DSUUBX_CORE_PPU_AIDR" 2926 #define device_bar_ODY_DSUUBX_CORE_PPU_AIDR(a) 0x0 /* PF_BAR0 */ 2927 #define busnum_ODY_DSUUBX_CORE_PPU_AIDR(a) (a) 2928 #define arguments_ODY_DSUUBX_CORE_PPU_AIDR(a) (a), -1, -1, -1 2929 2930 /** 2931 * Register (RSL32b) dsuub#_core_ppu_aimr 2932 * 2933 * DSUUB Core Additional Interrupt Mask Register 2934 * This register controls the events that assert the interrupt output. Additional event 2935 * masking controls 2936 * are in the Interrupt Mask Register (PPU_IMR), Input Edge Sensitivity Register (PPU_IESR), and the 2937 * Operating Mode Active Edge Sensitivity Register (PPU_OPSR). 2938 * 2939 * When an interrupt event is masked an occurrence of the event does not set the corresponding bit 2940 * in the interrupt status register. 2941 */ 2942 union ody_dsuubx_core_ppu_aimr { 2943 uint32_t u; 2944 struct ody_dsuubx_core_ppu_aimr_s { 2945 uint32_t unspt_policy_irq_mask : 1; 2946 uint32_t dyn_accept_irq_mask : 1; 2947 uint32_t dyn_deny_irq_mask : 1; 2948 uint32_t reserved_3_31 : 29; 2949 } s; 2950 /* struct ody_dsuubx_core_ppu_aimr_s cn; */ 2951 }; 2952 typedef union ody_dsuubx_core_ppu_aimr ody_dsuubx_core_ppu_aimr_t; 2953 2954 static inline uint64_t ODY_DSUUBX_CORE_PPU_AIMR(uint64_t a) __attribute__ ((pure, always_inline)); 2955 static inline uint64_t ODY_DSUUBX_CORE_PPU_AIMR(uint64_t a) 2956 { 2957 if (a <= 89) 2958 return 0x87e2ef080034ll + 0x1000000ll * ((a) & 0x7f); 2959 __ody_csr_fatal("DSUUBX_CORE_PPU_AIMR", 1, a, 0, 0, 0, 0, 0); 2960 } 2961 2962 #define typedef_ODY_DSUUBX_CORE_PPU_AIMR(a) ody_dsuubx_core_ppu_aimr_t 2963 #define bustype_ODY_DSUUBX_CORE_PPU_AIMR(a) CSR_TYPE_RSL32b 2964 #define basename_ODY_DSUUBX_CORE_PPU_AIMR(a) "DSUUBX_CORE_PPU_AIMR" 2965 #define device_bar_ODY_DSUUBX_CORE_PPU_AIMR(a) 0x0 /* PF_BAR0 */ 2966 #define busnum_ODY_DSUUBX_CORE_PPU_AIMR(a) (a) 2967 #define arguments_ODY_DSUUBX_CORE_PPU_AIMR(a) (a), -1, -1, -1 2968 2969 /** 2970 * Register (RSL32b) dsuub#_core_ppu_aisr 2971 * 2972 * DSUUB Core Additional Interrupt Status Register 2973 * This register contains information about events causing the assertion of the 2974 * interrupt output. It is 2975 * also used to clear interrupt events. 2976 * 2977 * A bit set to 1 indicates the event asserted the interrupt output. Multiple events can be active 2978 * at the same time. When an interrupt event is masked by the corresponding bit in PPU_AIMR, an 2979 * occurrence of that event does not set the status bit. 2980 * A write of 1 to a set event bit clears that event. A write of 0 has no effect. The interrupt 2981 * output stays HIGH until all status bits in the Interrupt Status Register (PPU_ISR) 2982 * and the Additional 2983 * Interrupt Status Register (PPU_AISR) are set to 0b0. 2984 * 2985 * When an interrupt status is set to 1 in this register it sets the OTHER_IRQ bit in the Interrupt 2986 * Status Register (PPU_ISR). Status bits in this register (PPU_AISR) are only cleared 2987 * by writing to this 2988 * register. 2989 */ 2990 union ody_dsuubx_core_ppu_aisr { 2991 uint32_t u; 2992 struct ody_dsuubx_core_ppu_aisr_s { 2993 uint32_t unspt_policy_irq : 1; 2994 uint32_t dyn_accept_irq : 1; 2995 uint32_t dyn_deny_irq : 1; 2996 uint32_t reserved_3_31 : 29; 2997 } s; 2998 /* struct ody_dsuubx_core_ppu_aisr_s cn; */ 2999 }; 3000 typedef union ody_dsuubx_core_ppu_aisr ody_dsuubx_core_ppu_aisr_t; 3001 3002 static inline uint64_t ODY_DSUUBX_CORE_PPU_AISR(uint64_t a) __attribute__ ((pure, always_inline)); 3003 static inline uint64_t ODY_DSUUBX_CORE_PPU_AISR(uint64_t a) 3004 { 3005 if (a <= 89) 3006 return 0x87e2ef08003cll + 0x1000000ll * ((a) & 0x7f); 3007 __ody_csr_fatal("DSUUBX_CORE_PPU_AISR", 1, a, 0, 0, 0, 0, 0); 3008 } 3009 3010 #define typedef_ODY_DSUUBX_CORE_PPU_AISR(a) ody_dsuubx_core_ppu_aisr_t 3011 #define bustype_ODY_DSUUBX_CORE_PPU_AISR(a) CSR_TYPE_RSL32b 3012 #define basename_ODY_DSUUBX_CORE_PPU_AISR(a) "DSUUBX_CORE_PPU_AISR" 3013 #define device_bar_ODY_DSUUBX_CORE_PPU_AISR(a) 0x0 /* PF_BAR0 */ 3014 #define busnum_ODY_DSUUBX_CORE_PPU_AISR(a) (a) 3015 #define arguments_ODY_DSUUBX_CORE_PPU_AISR(a) (a), -1, -1, -1 3016 3017 /** 3018 * Register (RSL32b) dsuub#_core_ppu_cidr0 3019 * 3020 * DSUUB Core PPU Component Identification Register 0 3021 * Provides CoreSight discovery information. 3022 */ 3023 union ody_dsuubx_core_ppu_cidr0 { 3024 uint32_t u; 3025 struct ody_dsuubx_core_ppu_cidr0_s { 3026 uint32_t prmbl_0 : 8; 3027 uint32_t reserved_8_31 : 24; 3028 } s; 3029 /* struct ody_dsuubx_core_ppu_cidr0_s cn; */ 3030 }; 3031 typedef union ody_dsuubx_core_ppu_cidr0 ody_dsuubx_core_ppu_cidr0_t; 3032 3033 static inline uint64_t ODY_DSUUBX_CORE_PPU_CIDR0(uint64_t a) __attribute__ ((pure, always_inline)); 3034 static inline uint64_t ODY_DSUUBX_CORE_PPU_CIDR0(uint64_t a) 3035 { 3036 if (a <= 89) 3037 return 0x87e2ef080ff0ll + 0x1000000ll * ((a) & 0x7f); 3038 __ody_csr_fatal("DSUUBX_CORE_PPU_CIDR0", 1, a, 0, 0, 0, 0, 0); 3039 } 3040 3041 #define typedef_ODY_DSUUBX_CORE_PPU_CIDR0(a) ody_dsuubx_core_ppu_cidr0_t 3042 #define bustype_ODY_DSUUBX_CORE_PPU_CIDR0(a) CSR_TYPE_RSL32b 3043 #define basename_ODY_DSUUBX_CORE_PPU_CIDR0(a) "DSUUBX_CORE_PPU_CIDR0" 3044 #define device_bar_ODY_DSUUBX_CORE_PPU_CIDR0(a) 0x0 /* PF_BAR0 */ 3045 #define busnum_ODY_DSUUBX_CORE_PPU_CIDR0(a) (a) 3046 #define arguments_ODY_DSUUBX_CORE_PPU_CIDR0(a) (a), -1, -1, -1 3047 3048 /** 3049 * Register (RSL32b) dsuub#_core_ppu_cidr1 3050 * 3051 * DSUUB Core PPU Component Identification Register 1 3052 * Provides CoreSight discovery information. 3053 */ 3054 union ody_dsuubx_core_ppu_cidr1 { 3055 uint32_t u; 3056 struct ody_dsuubx_core_ppu_cidr1_s { 3057 uint32_t prmbl_1 : 4; 3058 uint32_t clas : 4; 3059 uint32_t reserved_8_31 : 24; 3060 } s; 3061 /* struct ody_dsuubx_core_ppu_cidr1_s cn; */ 3062 }; 3063 typedef union ody_dsuubx_core_ppu_cidr1 ody_dsuubx_core_ppu_cidr1_t; 3064 3065 static inline uint64_t ODY_DSUUBX_CORE_PPU_CIDR1(uint64_t a) __attribute__ ((pure, always_inline)); 3066 static inline uint64_t ODY_DSUUBX_CORE_PPU_CIDR1(uint64_t a) 3067 { 3068 if (a <= 89) 3069 return 0x87e2ef080ff4ll + 0x1000000ll * ((a) & 0x7f); 3070 __ody_csr_fatal("DSUUBX_CORE_PPU_CIDR1", 1, a, 0, 0, 0, 0, 0); 3071 } 3072 3073 #define typedef_ODY_DSUUBX_CORE_PPU_CIDR1(a) ody_dsuubx_core_ppu_cidr1_t 3074 #define bustype_ODY_DSUUBX_CORE_PPU_CIDR1(a) CSR_TYPE_RSL32b 3075 #define basename_ODY_DSUUBX_CORE_PPU_CIDR1(a) "DSUUBX_CORE_PPU_CIDR1" 3076 #define device_bar_ODY_DSUUBX_CORE_PPU_CIDR1(a) 0x0 /* PF_BAR0 */ 3077 #define busnum_ODY_DSUUBX_CORE_PPU_CIDR1(a) (a) 3078 #define arguments_ODY_DSUUBX_CORE_PPU_CIDR1(a) (a), -1, -1, -1 3079 3080 /** 3081 * Register (RSL32b) dsuub#_core_ppu_cidr2 3082 * 3083 * DSUUB Core PPU Component Identification Register 2 3084 * Provides CoreSight discovery information. 3085 */ 3086 union ody_dsuubx_core_ppu_cidr2 { 3087 uint32_t u; 3088 struct ody_dsuubx_core_ppu_cidr2_s { 3089 uint32_t prmbl_2 : 8; 3090 uint32_t reserved_8_31 : 24; 3091 } s; 3092 /* struct ody_dsuubx_core_ppu_cidr2_s cn; */ 3093 }; 3094 typedef union ody_dsuubx_core_ppu_cidr2 ody_dsuubx_core_ppu_cidr2_t; 3095 3096 static inline uint64_t ODY_DSUUBX_CORE_PPU_CIDR2(uint64_t a) __attribute__ ((pure, always_inline)); 3097 static inline uint64_t ODY_DSUUBX_CORE_PPU_CIDR2(uint64_t a) 3098 { 3099 if (a <= 89) 3100 return 0x87e2ef080ff8ll + 0x1000000ll * ((a) & 0x7f); 3101 __ody_csr_fatal("DSUUBX_CORE_PPU_CIDR2", 1, a, 0, 0, 0, 0, 0); 3102 } 3103 3104 #define typedef_ODY_DSUUBX_CORE_PPU_CIDR2(a) ody_dsuubx_core_ppu_cidr2_t 3105 #define bustype_ODY_DSUUBX_CORE_PPU_CIDR2(a) CSR_TYPE_RSL32b 3106 #define basename_ODY_DSUUBX_CORE_PPU_CIDR2(a) "DSUUBX_CORE_PPU_CIDR2" 3107 #define device_bar_ODY_DSUUBX_CORE_PPU_CIDR2(a) 0x0 /* PF_BAR0 */ 3108 #define busnum_ODY_DSUUBX_CORE_PPU_CIDR2(a) (a) 3109 #define arguments_ODY_DSUUBX_CORE_PPU_CIDR2(a) (a), -1, -1, -1 3110 3111 /** 3112 * Register (RSL32b) dsuub#_core_ppu_dcdr0 3113 * 3114 * DSUUB Core Device Control Delay Configuration Register 0 3115 * This register is used to program device control delay parameters. 3116 */ 3117 union ody_dsuubx_core_ppu_dcdr0 { 3118 uint32_t u; 3119 struct ody_dsuubx_core_ppu_dcdr0_s { 3120 uint32_t clken_rst_dly : 8; 3121 uint32_t iso_clken_dly : 8; 3122 uint32_t rst_hwstat_dly : 8; 3123 uint32_t reserved_24_31 : 8; 3124 } s; 3125 /* struct ody_dsuubx_core_ppu_dcdr0_s cn; */ 3126 }; 3127 typedef union ody_dsuubx_core_ppu_dcdr0 ody_dsuubx_core_ppu_dcdr0_t; 3128 3129 static inline uint64_t ODY_DSUUBX_CORE_PPU_DCDR0(uint64_t a) __attribute__ ((pure, always_inline)); 3130 static inline uint64_t ODY_DSUUBX_CORE_PPU_DCDR0(uint64_t a) 3131 { 3132 if (a <= 89) 3133 return 0x87e2ef080170ll + 0x1000000ll * ((a) & 0x7f); 3134 __ody_csr_fatal("DSUUBX_CORE_PPU_DCDR0", 1, a, 0, 0, 0, 0, 0); 3135 } 3136 3137 #define typedef_ODY_DSUUBX_CORE_PPU_DCDR0(a) ody_dsuubx_core_ppu_dcdr0_t 3138 #define bustype_ODY_DSUUBX_CORE_PPU_DCDR0(a) CSR_TYPE_RSL32b 3139 #define basename_ODY_DSUUBX_CORE_PPU_DCDR0(a) "DSUUBX_CORE_PPU_DCDR0" 3140 #define device_bar_ODY_DSUUBX_CORE_PPU_DCDR0(a) 0x0 /* PF_BAR0 */ 3141 #define busnum_ODY_DSUUBX_CORE_PPU_DCDR0(a) (a) 3142 #define arguments_ODY_DSUUBX_CORE_PPU_DCDR0(a) (a), -1, -1, -1 3143 3144 /** 3145 * Register (RSL32b) dsuub#_core_ppu_dcdr1 3146 * 3147 * DSUUB Core Device Control Delay Configuration Register 1 3148 * This register is used to program device control delay parameters. 3149 */ 3150 union ody_dsuubx_core_ppu_dcdr1 { 3151 uint32_t u; 3152 struct ody_dsuubx_core_ppu_dcdr1_s { 3153 uint32_t iso_rst_dly : 8; 3154 uint32_t clken_iso_dly : 8; 3155 uint32_t reserved_16_31 : 16; 3156 } s; 3157 /* struct ody_dsuubx_core_ppu_dcdr1_s cn; */ 3158 }; 3159 typedef union ody_dsuubx_core_ppu_dcdr1 ody_dsuubx_core_ppu_dcdr1_t; 3160 3161 static inline uint64_t ODY_DSUUBX_CORE_PPU_DCDR1(uint64_t a) __attribute__ ((pure, always_inline)); 3162 static inline uint64_t ODY_DSUUBX_CORE_PPU_DCDR1(uint64_t a) 3163 { 3164 if (a <= 89) 3165 return 0x87e2ef080174ll + 0x1000000ll * ((a) & 0x7f); 3166 __ody_csr_fatal("DSUUBX_CORE_PPU_DCDR1", 1, a, 0, 0, 0, 0, 0); 3167 } 3168 3169 #define typedef_ODY_DSUUBX_CORE_PPU_DCDR1(a) ody_dsuubx_core_ppu_dcdr1_t 3170 #define bustype_ODY_DSUUBX_CORE_PPU_DCDR1(a) CSR_TYPE_RSL32b 3171 #define basename_ODY_DSUUBX_CORE_PPU_DCDR1(a) "DSUUBX_CORE_PPU_DCDR1" 3172 #define device_bar_ODY_DSUUBX_CORE_PPU_DCDR1(a) 0x0 /* PF_BAR0 */ 3173 #define busnum_ODY_DSUUBX_CORE_PPU_DCDR1(a) (a) 3174 #define arguments_ODY_DSUUBX_CORE_PPU_DCDR1(a) (a), -1, -1, -1 3175 3176 /** 3177 * Register (RSL32b) dsuub#_core_ppu_disr 3178 * 3179 * DSUUB Core Device Interface Input Current Status Register 3180 * This read-only register contains status reflecting the values of the device interface inputs. 3181 */ 3182 union ody_dsuubx_core_ppu_disr { 3183 uint32_t u; 3184 struct ody_dsuubx_core_ppu_disr_s { 3185 uint32_t pwr_devactive_status : 11; 3186 uint32_t reserved_11_31 : 21; 3187 } s; 3188 /* struct ody_dsuubx_core_ppu_disr_s cn; */ 3189 }; 3190 typedef union ody_dsuubx_core_ppu_disr ody_dsuubx_core_ppu_disr_t; 3191 3192 static inline uint64_t ODY_DSUUBX_CORE_PPU_DISR(uint64_t a) __attribute__ ((pure, always_inline)); 3193 static inline uint64_t ODY_DSUUBX_CORE_PPU_DISR(uint64_t a) 3194 { 3195 if (a <= 89) 3196 return 0x87e2ef080010ll + 0x1000000ll * ((a) & 0x7f); 3197 __ody_csr_fatal("DSUUBX_CORE_PPU_DISR", 1, a, 0, 0, 0, 0, 0); 3198 } 3199 3200 #define typedef_ODY_DSUUBX_CORE_PPU_DISR(a) ody_dsuubx_core_ppu_disr_t 3201 #define bustype_ODY_DSUUBX_CORE_PPU_DISR(a) CSR_TYPE_RSL32b 3202 #define basename_ODY_DSUUBX_CORE_PPU_DISR(a) "DSUUBX_CORE_PPU_DISR" 3203 #define device_bar_ODY_DSUUBX_CORE_PPU_DISR(a) 0x0 /* PF_BAR0 */ 3204 #define busnum_ODY_DSUUBX_CORE_PPU_DISR(a) (a) 3205 #define arguments_ODY_DSUUBX_CORE_PPU_DISR(a) (a), -1, -1, -1 3206 3207 /** 3208 * Register (RSL32b) dsuub#_core_ppu_fulrr 3209 * 3210 * DSUUB Core Full Retention RAM Configuration Register 3211 * This register controls bits [15:8] of the PCSMPSTATE output when in FULL_RET mode. These 3212 * outputs are used by the PCSM to configure the logic regions and RAMs that are retained. 3213 */ 3214 union ody_dsuubx_core_ppu_fulrr { 3215 uint32_t u; 3216 struct ody_dsuubx_core_ppu_fulrr_s { 3217 uint32_t full_ret_ram_cfg : 8; 3218 uint32_t reserved_8_31 : 24; 3219 } s; 3220 /* struct ody_dsuubx_core_ppu_fulrr_s cn; */ 3221 }; 3222 typedef union ody_dsuubx_core_ppu_fulrr ody_dsuubx_core_ppu_fulrr_t; 3223 3224 static inline uint64_t ODY_DSUUBX_CORE_PPU_FULRR(uint64_t a) __attribute__ ((pure, always_inline)); 3225 static inline uint64_t ODY_DSUUBX_CORE_PPU_FULRR(uint64_t a) 3226 { 3227 if (a <= 89) 3228 return 0x87e2ef080054ll + 0x1000000ll * ((a) & 0x7f); 3229 __ody_csr_fatal("DSUUBX_CORE_PPU_FULRR", 1, a, 0, 0, 0, 0, 0); 3230 } 3231 3232 #define typedef_ODY_DSUUBX_CORE_PPU_FULRR(a) ody_dsuubx_core_ppu_fulrr_t 3233 #define bustype_ODY_DSUUBX_CORE_PPU_FULRR(a) CSR_TYPE_RSL32b 3234 #define basename_ODY_DSUUBX_CORE_PPU_FULRR(a) "DSUUBX_CORE_PPU_FULRR" 3235 #define device_bar_ODY_DSUUBX_CORE_PPU_FULRR(a) 0x0 /* PF_BAR0 */ 3236 #define busnum_ODY_DSUUBX_CORE_PPU_FULRR(a) (a) 3237 #define arguments_ODY_DSUUBX_CORE_PPU_FULRR(a) (a), -1, -1, -1 3238 3239 /** 3240 * Register (RSL32b) dsuub#_core_ppu_funrr 3241 * 3242 * DSUUB Core Functional Retention RAM Configuration Register 3243 * This register is reserved. 3244 */ 3245 union ody_dsuubx_core_ppu_funrr { 3246 uint32_t u; 3247 struct ody_dsuubx_core_ppu_funrr_s { 3248 uint32_t func_ret_ram_cfg : 8; 3249 uint32_t reserved_8_31 : 24; 3250 } s; 3251 /* struct ody_dsuubx_core_ppu_funrr_s cn; */ 3252 }; 3253 typedef union ody_dsuubx_core_ppu_funrr ody_dsuubx_core_ppu_funrr_t; 3254 3255 static inline uint64_t ODY_DSUUBX_CORE_PPU_FUNRR(uint64_t a) __attribute__ ((pure, always_inline)); 3256 static inline uint64_t ODY_DSUUBX_CORE_PPU_FUNRR(uint64_t a) 3257 { 3258 if (a <= 89) 3259 return 0x87e2ef080050ll + 0x1000000ll * ((a) & 0x7f); 3260 __ody_csr_fatal("DSUUBX_CORE_PPU_FUNRR", 1, a, 0, 0, 0, 0, 0); 3261 } 3262 3263 #define typedef_ODY_DSUUBX_CORE_PPU_FUNRR(a) ody_dsuubx_core_ppu_funrr_t 3264 #define bustype_ODY_DSUUBX_CORE_PPU_FUNRR(a) CSR_TYPE_RSL32b 3265 #define basename_ODY_DSUUBX_CORE_PPU_FUNRR(a) "DSUUBX_CORE_PPU_FUNRR" 3266 #define device_bar_ODY_DSUUBX_CORE_PPU_FUNRR(a) 0x0 /* PF_BAR0 */ 3267 #define busnum_ODY_DSUUBX_CORE_PPU_FUNRR(a) (a) 3268 #define arguments_ODY_DSUUBX_CORE_PPU_FUNRR(a) (a), -1, -1, -1 3269 3270 /** 3271 * Register (RSL32b) dsuub#_core_ppu_idr0 3272 * 3273 * DSUUB Core PPU Identification Register 0 3274 * This read-only register contains information on the type and number of channels on the device 3275 * interface and power and operating modes supported. 3276 * 3277 * Additional information on optional features can be found in the PPU Identification Register 1 3278 * (PPU_IDR1). 3279 */ 3280 union ody_dsuubx_core_ppu_idr0 { 3281 uint32_t u; 3282 struct ody_dsuubx_core_ppu_idr0_s { 3283 uint32_t devchan : 4; 3284 uint32_t num_opmode : 4; 3285 uint32_t sta_off_spt : 1; 3286 uint32_t sta_off_emu_spt : 1; 3287 uint32_t sta_mem_ret_spt : 1; 3288 uint32_t sta_mem_ret_emu_spt : 1; 3289 uint32_t sta_lgc_ret_spt : 1; 3290 uint32_t sta_mem_off_spt : 1; 3291 uint32_t sta_full_ret_spt : 1; 3292 uint32_t sta_func_ret_spt : 1; 3293 uint32_t sta_on_spt : 1; 3294 uint32_t sta_wrm_rst_spt : 1; 3295 uint32_t sta_dbg_recov_spt : 1; 3296 uint32_t reserved_19 : 1; 3297 uint32_t dyn_off_spt : 1; 3298 uint32_t dyn_off_emu_spt : 1; 3299 uint32_t dyn_mem_ret_spt : 1; 3300 uint32_t dyn_mem_ret_emu_spt : 1; 3301 uint32_t dyn_lgc_ret_spt : 1; 3302 uint32_t dyn_mem_off_spt : 1; 3303 uint32_t dyn_full_ret_spt : 1; 3304 uint32_t dyn_func_ret_spt : 1; 3305 uint32_t dyn_on_spt : 1; 3306 uint32_t dyn_wrm_rst_spt : 1; 3307 uint32_t reserved_30_31 : 2; 3308 } s; 3309 /* struct ody_dsuubx_core_ppu_idr0_s cn; */ 3310 }; 3311 typedef union ody_dsuubx_core_ppu_idr0 ody_dsuubx_core_ppu_idr0_t; 3312 3313 static inline uint64_t ODY_DSUUBX_CORE_PPU_IDR0(uint64_t a) __attribute__ ((pure, always_inline)); 3314 static inline uint64_t ODY_DSUUBX_CORE_PPU_IDR0(uint64_t a) 3315 { 3316 if (a <= 89) 3317 return 0x87e2ef080fb0ll + 0x1000000ll * ((a) & 0x7f); 3318 __ody_csr_fatal("DSUUBX_CORE_PPU_IDR0", 1, a, 0, 0, 0, 0, 0); 3319 } 3320 3321 #define typedef_ODY_DSUUBX_CORE_PPU_IDR0(a) ody_dsuubx_core_ppu_idr0_t 3322 #define bustype_ODY_DSUUBX_CORE_PPU_IDR0(a) CSR_TYPE_RSL32b 3323 #define basename_ODY_DSUUBX_CORE_PPU_IDR0(a) "DSUUBX_CORE_PPU_IDR0" 3324 #define device_bar_ODY_DSUUBX_CORE_PPU_IDR0(a) 0x0 /* PF_BAR0 */ 3325 #define busnum_ODY_DSUUBX_CORE_PPU_IDR0(a) (a) 3326 #define arguments_ODY_DSUUBX_CORE_PPU_IDR0(a) (a), -1, -1, -1 3327 3328 /** 3329 * Register (RSL32b) dsuub#_core_ppu_idr1 3330 * 3331 * DSUUB Core PPU Identification Register 1 3332 * This read-only register contains information on the optional features and configurations that are 3333 * supported by this PPU. 3334 * 3335 * Additional information on optional features can be found in the PPU Identification Register 0 3336 * (PPU_IDR0). 3337 */ 3338 union ody_dsuubx_core_ppu_idr1 { 3339 uint32_t u; 3340 struct ody_dsuubx_core_ppu_idr1_s { 3341 uint32_t pwr_mode_entry_del_spt : 1; 3342 uint32_t sw_dev_del_spt : 1; 3343 uint32_t lock_spt : 1; 3344 uint32_t reserved_3 : 1; 3345 uint32_t mem_ret_ram_reg : 1; 3346 uint32_t full_ret_ram_reg : 1; 3347 uint32_t func_ret_ram_reg : 1; 3348 uint32_t reserved_7 : 1; 3349 uint32_t sta_policy_pwr_irq_spt : 1; 3350 uint32_t reserved_9_11 : 3; 3351 uint32_t off_mem_ret_trans : 1; 3352 uint32_t reserved_13_31 : 19; 3353 } s; 3354 /* struct ody_dsuubx_core_ppu_idr1_s cn; */ 3355 }; 3356 typedef union ody_dsuubx_core_ppu_idr1 ody_dsuubx_core_ppu_idr1_t; 3357 3358 static inline uint64_t ODY_DSUUBX_CORE_PPU_IDR1(uint64_t a) __attribute__ ((pure, always_inline)); 3359 static inline uint64_t ODY_DSUUBX_CORE_PPU_IDR1(uint64_t a) 3360 { 3361 if (a <= 89) 3362 return 0x87e2ef080fb4ll + 0x1000000ll * ((a) & 0x7f); 3363 __ody_csr_fatal("DSUUBX_CORE_PPU_IDR1", 1, a, 0, 0, 0, 0, 0); 3364 } 3365 3366 #define typedef_ODY_DSUUBX_CORE_PPU_IDR1(a) ody_dsuubx_core_ppu_idr1_t 3367 #define bustype_ODY_DSUUBX_CORE_PPU_IDR1(a) CSR_TYPE_RSL32b 3368 #define basename_ODY_DSUUBX_CORE_PPU_IDR1(a) "DSUUBX_CORE_PPU_IDR1" 3369 #define device_bar_ODY_DSUUBX_CORE_PPU_IDR1(a) 0x0 /* PF_BAR0 */ 3370 #define busnum_ODY_DSUUBX_CORE_PPU_IDR1(a) (a) 3371 #define arguments_ODY_DSUUBX_CORE_PPU_IDR1(a) (a), -1, -1, -1 3372 3373 /** 3374 * Register (RSL32b) dsuub#_core_ppu_iesr 3375 * 3376 * DSUUB Core Input Edge Sensitivity Register 3377 * This register configures the transitions on the power mode DEVPACTIVE inputs that generate an 3378 * Input Edge interrupt event. 3379 * 3380 * When an event is masked an occurrence of the event does not set the corresponding bit in the 3381 * interrupt status register. 3382 */ 3383 union ody_dsuubx_core_ppu_iesr { 3384 uint32_t u; 3385 struct ody_dsuubx_core_ppu_iesr_s { 3386 uint32_t reserved_0_1 : 2; 3387 uint32_t devactive01_edge : 2; 3388 uint32_t reserved_4_9 : 6; 3389 uint32_t devactive05_edge : 2; 3390 uint32_t reserved_12_13 : 2; 3391 uint32_t devactive07_edge : 2; 3392 uint32_t devactive08_edge : 2; 3393 uint32_t devactive09_edge : 2; 3394 uint32_t devactive10_edge : 2; 3395 uint32_t reserved_22_31 : 10; 3396 } s; 3397 /* struct ody_dsuubx_core_ppu_iesr_s cn; */ 3398 }; 3399 typedef union ody_dsuubx_core_ppu_iesr ody_dsuubx_core_ppu_iesr_t; 3400 3401 static inline uint64_t ODY_DSUUBX_CORE_PPU_IESR(uint64_t a) __attribute__ ((pure, always_inline)); 3402 static inline uint64_t ODY_DSUUBX_CORE_PPU_IESR(uint64_t a) 3403 { 3404 if (a <= 89) 3405 return 0x87e2ef080040ll + 0x1000000ll * ((a) & 0x7f); 3406 __ody_csr_fatal("DSUUBX_CORE_PPU_IESR", 1, a, 0, 0, 0, 0, 0); 3407 } 3408 3409 #define typedef_ODY_DSUUBX_CORE_PPU_IESR(a) ody_dsuubx_core_ppu_iesr_t 3410 #define bustype_ODY_DSUUBX_CORE_PPU_IESR(a) CSR_TYPE_RSL32b 3411 #define basename_ODY_DSUUBX_CORE_PPU_IESR(a) "DSUUBX_CORE_PPU_IESR" 3412 #define device_bar_ODY_DSUUBX_CORE_PPU_IESR(a) 0x0 /* PF_BAR0 */ 3413 #define busnum_ODY_DSUUBX_CORE_PPU_IESR(a) (a) 3414 #define arguments_ODY_DSUUBX_CORE_PPU_IESR(a) (a), -1, -1, -1 3415 3416 /** 3417 * Register (RSL32b) dsuub#_core_ppu_iidr 3418 * 3419 * DSUUB Core Implementation Identification Register 3420 * This register provides information about the implementer and implementation of the PPU. 3421 */ 3422 union ody_dsuubx_core_ppu_iidr { 3423 uint32_t u; 3424 struct ody_dsuubx_core_ppu_iidr_s { 3425 uint32_t implementer : 12; 3426 uint32_t revision : 4; 3427 uint32_t variant : 4; 3428 uint32_t product_id : 12; 3429 } s; 3430 /* struct ody_dsuubx_core_ppu_iidr_s cn; */ 3431 }; 3432 typedef union ody_dsuubx_core_ppu_iidr ody_dsuubx_core_ppu_iidr_t; 3433 3434 static inline uint64_t ODY_DSUUBX_CORE_PPU_IIDR(uint64_t a) __attribute__ ((pure, always_inline)); 3435 static inline uint64_t ODY_DSUUBX_CORE_PPU_IIDR(uint64_t a) 3436 { 3437 if (a <= 89) 3438 return 0x87e2ef080fc8ll + 0x1000000ll * ((a) & 0x7f); 3439 __ody_csr_fatal("DSUUBX_CORE_PPU_IIDR", 1, a, 0, 0, 0, 0, 0); 3440 } 3441 3442 #define typedef_ODY_DSUUBX_CORE_PPU_IIDR(a) ody_dsuubx_core_ppu_iidr_t 3443 #define bustype_ODY_DSUUBX_CORE_PPU_IIDR(a) CSR_TYPE_RSL32b 3444 #define basename_ODY_DSUUBX_CORE_PPU_IIDR(a) "DSUUBX_CORE_PPU_IIDR" 3445 #define device_bar_ODY_DSUUBX_CORE_PPU_IIDR(a) 0x0 /* PF_BAR0 */ 3446 #define busnum_ODY_DSUUBX_CORE_PPU_IIDR(a) (a) 3447 #define arguments_ODY_DSUUBX_CORE_PPU_IIDR(a) (a), -1, -1, -1 3448 3449 /** 3450 * Register (RSL32b) dsuub#_core_ppu_imr 3451 * 3452 * DSUUB Core Interrupt Mask Register 3453 * This register controls the events that assert the interrupt output. Additional event 3454 * masking controls 3455 * are in the Additional Interrupt Mask Register (DSUUB_PPU_AIMR), Input Edge 3456 * Sensitivity Register (DSUUB_ 3457 * PPU_IESR), and the Operating Mode Active Edge Sensitivity Register (DSUUB_PPU_OPSR). 3458 * 3459 * When an interrupt event is masked an occurrence of the event does not set the corresponding bit 3460 * in the interrupt status register. 3461 */ 3462 union ody_dsuubx_core_ppu_imr { 3463 uint32_t u; 3464 struct ody_dsuubx_core_ppu_imr_s { 3465 uint32_t sta_policy_trn_irq_mask : 1; 3466 uint32_t sta_accept_irq_mask : 1; 3467 uint32_t sta_deny_irq_mask : 1; 3468 uint32_t emu_accept_irq_mask : 1; 3469 uint32_t emu_deny_irq_mask : 1; 3470 uint32_t locked_irq_mask : 1; 3471 uint32_t reserved_6_31 : 26; 3472 } s; 3473 /* struct ody_dsuubx_core_ppu_imr_s cn; */ 3474 }; 3475 typedef union ody_dsuubx_core_ppu_imr ody_dsuubx_core_ppu_imr_t; 3476 3477 static inline uint64_t ODY_DSUUBX_CORE_PPU_IMR(uint64_t a) __attribute__ ((pure, always_inline)); 3478 static inline uint64_t ODY_DSUUBX_CORE_PPU_IMR(uint64_t a) 3479 { 3480 if (a <= 89) 3481 return 0x87e2ef080030ll + 0x1000000ll * ((a) & 0x7f); 3482 __ody_csr_fatal("DSUUBX_CORE_PPU_IMR", 1, a, 0, 0, 0, 0, 0); 3483 } 3484 3485 #define typedef_ODY_DSUUBX_CORE_PPU_IMR(a) ody_dsuubx_core_ppu_imr_t 3486 #define bustype_ODY_DSUUBX_CORE_PPU_IMR(a) CSR_TYPE_RSL32b 3487 #define basename_ODY_DSUUBX_CORE_PPU_IMR(a) "DSUUBX_CORE_PPU_IMR" 3488 #define device_bar_ODY_DSUUBX_CORE_PPU_IMR(a) 0x0 /* PF_BAR0 */ 3489 #define busnum_ODY_DSUUBX_CORE_PPU_IMR(a) (a) 3490 #define arguments_ODY_DSUUBX_CORE_PPU_IMR(a) (a), -1, -1, -1 3491 3492 /** 3493 * Register (RSL32b) dsuub#_core_ppu_isr 3494 * 3495 * DSUUB Core Interrupt Status Register 3496 * This register contains information about events causing the assertion of the 3497 * interrupt output. It is 3498 * also used to clear interrupt events. 3499 * 3500 * A bit set to 1 indicates the event asserted the interrupt output. Multiple events 3501 * can be active at 3502 * the same time. When an interrupt event is masked an occurrence of that event does not set the 3503 * status bit. 3504 * 3505 * A write of 1 to an event bit clears that event. A write of 0 to a bit has no 3506 * effect. The interrupt 3507 * output stays HIGH until all status bits in the Interrupt Status Register (PPU_ISR) 3508 * and the Additional 3509 * Interrupt Status Register (PPU_AISR) are 0b0. 3510 * 3511 * When the OTHER_IRQ bit is set, this indicates an event from the Additional Interrupt Status 3512 * Register (PPU_AISR) has caused the interrupt output to be asserted. This bit cannot be cleared by 3513 * writing to this register. It must be cleared by writing to the active event in the 3514 * Additional Interrupt 3515 * Status Register (PPU_AISR). 3516 */ 3517 union ody_dsuubx_core_ppu_isr { 3518 uint32_t u; 3519 struct ody_dsuubx_core_ppu_isr_s { 3520 uint32_t sta_policy_trn_irq : 1; 3521 uint32_t sta_accept_irq : 1; 3522 uint32_t sta_deny_irq : 1; 3523 uint32_t emu_accept_irq : 1; 3524 uint32_t emu_deny_irq : 1; 3525 uint32_t locked_irq : 1; 3526 uint32_t reserved_6 : 1; 3527 uint32_t other_irq : 1; 3528 uint32_t reserved_8 : 1; 3529 uint32_t pwr_active_edge_irq1 : 1; 3530 uint32_t reserved_10_12 : 3; 3531 uint32_t pwr_active_edge_irq5 : 1; 3532 uint32_t reserved_14 : 1; 3533 uint32_t pwr_active_edge_irq7 : 1; 3534 uint32_t pwr_active_edge_irq8 : 1; 3535 uint32_t pwr_active_edge_irq9 : 1; 3536 uint32_t pwr_active_edge_irq10 : 1; 3537 uint32_t reserved_19_31 : 13; 3538 } s; 3539 /* struct ody_dsuubx_core_ppu_isr_s cn; */ 3540 }; 3541 typedef union ody_dsuubx_core_ppu_isr ody_dsuubx_core_ppu_isr_t; 3542 3543 static inline uint64_t ODY_DSUUBX_CORE_PPU_ISR(uint64_t a) __attribute__ ((pure, always_inline)); 3544 static inline uint64_t ODY_DSUUBX_CORE_PPU_ISR(uint64_t a) 3545 { 3546 if (a <= 89) 3547 return 0x87e2ef080038ll + 0x1000000ll * ((a) & 0x7f); 3548 __ody_csr_fatal("DSUUBX_CORE_PPU_ISR", 1, a, 0, 0, 0, 0, 0); 3549 } 3550 3551 #define typedef_ODY_DSUUBX_CORE_PPU_ISR(a) ody_dsuubx_core_ppu_isr_t 3552 #define bustype_ODY_DSUUBX_CORE_PPU_ISR(a) CSR_TYPE_RSL32b 3553 #define basename_ODY_DSUUBX_CORE_PPU_ISR(a) "DSUUBX_CORE_PPU_ISR" 3554 #define device_bar_ODY_DSUUBX_CORE_PPU_ISR(a) 0x0 /* PF_BAR0 */ 3555 #define busnum_ODY_DSUUBX_CORE_PPU_ISR(a) (a) 3556 #define arguments_ODY_DSUUBX_CORE_PPU_ISR(a) (a), -1, -1, -1 3557 3558 /** 3559 * Register (RSL32b) dsuub#_core_ppu_memrr 3560 * 3561 * DSUUB Core Memory Retention RAM Configuration Register 3562 * This register controls bits [15:8] of the PCSMPSTATE output when in MEM_RET mode. These 3563 * outputs are used by the PCSM to configure the RAMs that are retained. 3564 */ 3565 union ody_dsuubx_core_ppu_memrr { 3566 uint32_t u; 3567 struct ody_dsuubx_core_ppu_memrr_s { 3568 uint32_t reserved_0_31 : 32; 3569 } s; 3570 /* struct ody_dsuubx_core_ppu_memrr_s cn; */ 3571 }; 3572 typedef union ody_dsuubx_core_ppu_memrr ody_dsuubx_core_ppu_memrr_t; 3573 3574 static inline uint64_t ODY_DSUUBX_CORE_PPU_MEMRR(uint64_t a) __attribute__ ((pure, always_inline)); 3575 static inline uint64_t ODY_DSUUBX_CORE_PPU_MEMRR(uint64_t a) 3576 { 3577 if (a <= 89) 3578 return 0x87e2ef080058ll + 0x1000000ll * ((a) & 0x7f); 3579 __ody_csr_fatal("DSUUBX_CORE_PPU_MEMRR", 1, a, 0, 0, 0, 0, 0); 3580 } 3581 3582 #define typedef_ODY_DSUUBX_CORE_PPU_MEMRR(a) ody_dsuubx_core_ppu_memrr_t 3583 #define bustype_ODY_DSUUBX_CORE_PPU_MEMRR(a) CSR_TYPE_RSL32b 3584 #define basename_ODY_DSUUBX_CORE_PPU_MEMRR(a) "DSUUBX_CORE_PPU_MEMRR" 3585 #define device_bar_ODY_DSUUBX_CORE_PPU_MEMRR(a) 0x0 /* PF_BAR0 */ 3586 #define busnum_ODY_DSUUBX_CORE_PPU_MEMRR(a) (a) 3587 #define arguments_ODY_DSUUBX_CORE_PPU_MEMRR(a) (a), -1, -1, -1 3588 3589 /** 3590 * Register (RSL32b) dsuub#_core_ppu_misr 3591 * 3592 * DSUUB Core Miscellaneous Input Current Status Register 3593 * This read-only register contains status reflecting the values of miscellaneous inputs. 3594 */ 3595 union ody_dsuubx_core_ppu_misr { 3596 uint32_t u; 3597 struct ody_dsuubx_core_ppu_misr_s { 3598 uint32_t pcsmpaccept_status : 1; 3599 uint32_t reserved_1_7 : 7; 3600 uint32_t devaccept_status : 1; 3601 uint32_t reserved_9_15 : 7; 3602 uint32_t devdeny_status : 1; 3603 uint32_t reserved_17_31 : 15; 3604 } s; 3605 /* struct ody_dsuubx_core_ppu_misr_s cn; */ 3606 }; 3607 typedef union ody_dsuubx_core_ppu_misr ody_dsuubx_core_ppu_misr_t; 3608 3609 static inline uint64_t ODY_DSUUBX_CORE_PPU_MISR(uint64_t a) __attribute__ ((pure, always_inline)); 3610 static inline uint64_t ODY_DSUUBX_CORE_PPU_MISR(uint64_t a) 3611 { 3612 if (a <= 89) 3613 return 0x87e2ef080014ll + 0x1000000ll * ((a) & 0x7f); 3614 __ody_csr_fatal("DSUUBX_CORE_PPU_MISR", 1, a, 0, 0, 0, 0, 0); 3615 } 3616 3617 #define typedef_ODY_DSUUBX_CORE_PPU_MISR(a) ody_dsuubx_core_ppu_misr_t 3618 #define bustype_ODY_DSUUBX_CORE_PPU_MISR(a) CSR_TYPE_RSL32b 3619 #define basename_ODY_DSUUBX_CORE_PPU_MISR(a) "DSUUBX_CORE_PPU_MISR" 3620 #define device_bar_ODY_DSUUBX_CORE_PPU_MISR(a) 0x0 /* PF_BAR0 */ 3621 #define busnum_ODY_DSUUBX_CORE_PPU_MISR(a) (a) 3622 #define arguments_ODY_DSUUBX_CORE_PPU_MISR(a) (a), -1, -1, -1 3623 3624 /** 3625 * Register (RSL32b) dsuub#_core_ppu_opsr 3626 * 3627 * DSUUB Core Input Edge Sensitivity Register 3628 * This register configures the transitions on the operating mode DEVPACTIVE inputs that generate 3629 * an Input Edge interrupt event. 3630 * 3631 * When an event is masked an occurrence of the event does not set the corresponding bit in the 3632 * interrupt status register. 3633 */ 3634 union ody_dsuubx_core_ppu_opsr { 3635 uint32_t u; 3636 struct ody_dsuubx_core_ppu_opsr_s { 3637 uint32_t reserved_0_31 : 32; 3638 } s; 3639 /* struct ody_dsuubx_core_ppu_opsr_s cn; */ 3640 }; 3641 typedef union ody_dsuubx_core_ppu_opsr ody_dsuubx_core_ppu_opsr_t; 3642 3643 static inline uint64_t ODY_DSUUBX_CORE_PPU_OPSR(uint64_t a) __attribute__ ((pure, always_inline)); 3644 static inline uint64_t ODY_DSUUBX_CORE_PPU_OPSR(uint64_t a) 3645 { 3646 if (a <= 89) 3647 return 0x87e2ef080044ll + 0x1000000ll * ((a) & 0x7f); 3648 __ody_csr_fatal("DSUUBX_CORE_PPU_OPSR", 1, a, 0, 0, 0, 0, 0); 3649 } 3650 3651 #define typedef_ODY_DSUUBX_CORE_PPU_OPSR(a) ody_dsuubx_core_ppu_opsr_t 3652 #define bustype_ODY_DSUUBX_CORE_PPU_OPSR(a) CSR_TYPE_RSL32b 3653 #define basename_ODY_DSUUBX_CORE_PPU_OPSR(a) "DSUUBX_CORE_PPU_OPSR" 3654 #define device_bar_ODY_DSUUBX_CORE_PPU_OPSR(a) 0x0 /* PF_BAR0 */ 3655 #define busnum_ODY_DSUUBX_CORE_PPU_OPSR(a) (a) 3656 #define arguments_ODY_DSUUBX_CORE_PPU_OPSR(a) (a), -1, -1, -1 3657 3658 /** 3659 * Register (RSL32b) dsuub#_core_ppu_pidr0 3660 * 3661 * DSUUB Core PPU Peripheral Identification Register 0 3662 * Provides CoreSight discovery information. 3663 */ 3664 union ody_dsuubx_core_ppu_pidr0 { 3665 uint32_t u; 3666 struct ody_dsuubx_core_ppu_pidr0_s { 3667 uint32_t part_0 : 8; 3668 uint32_t reserved_8_31 : 24; 3669 } s; 3670 /* struct ody_dsuubx_core_ppu_pidr0_s cn; */ 3671 }; 3672 typedef union ody_dsuubx_core_ppu_pidr0 ody_dsuubx_core_ppu_pidr0_t; 3673 3674 static inline uint64_t ODY_DSUUBX_CORE_PPU_PIDR0(uint64_t a) __attribute__ ((pure, always_inline)); 3675 static inline uint64_t ODY_DSUUBX_CORE_PPU_PIDR0(uint64_t a) 3676 { 3677 if (a <= 89) 3678 return 0x87e2ef080fe0ll + 0x1000000ll * ((a) & 0x7f); 3679 __ody_csr_fatal("DSUUBX_CORE_PPU_PIDR0", 1, a, 0, 0, 0, 0, 0); 3680 } 3681 3682 #define typedef_ODY_DSUUBX_CORE_PPU_PIDR0(a) ody_dsuubx_core_ppu_pidr0_t 3683 #define bustype_ODY_DSUUBX_CORE_PPU_PIDR0(a) CSR_TYPE_RSL32b 3684 #define basename_ODY_DSUUBX_CORE_PPU_PIDR0(a) "DSUUBX_CORE_PPU_PIDR0" 3685 #define device_bar_ODY_DSUUBX_CORE_PPU_PIDR0(a) 0x0 /* PF_BAR0 */ 3686 #define busnum_ODY_DSUUBX_CORE_PPU_PIDR0(a) (a) 3687 #define arguments_ODY_DSUUBX_CORE_PPU_PIDR0(a) (a), -1, -1, -1 3688 3689 /** 3690 * Register (RSL32b) dsuub#_core_ppu_pidr1 3691 * 3692 * DSUUB Core PPU Peripheral Identification Register 1 3693 * Provides CoreSight discovery information. 3694 */ 3695 union ody_dsuubx_core_ppu_pidr1 { 3696 uint32_t u; 3697 struct ody_dsuubx_core_ppu_pidr1_s { 3698 uint32_t part_1 : 4; 3699 uint32_t des_0 : 4; 3700 uint32_t reserved_8_31 : 24; 3701 } s; 3702 /* struct ody_dsuubx_core_ppu_pidr1_s cn; */ 3703 }; 3704 typedef union ody_dsuubx_core_ppu_pidr1 ody_dsuubx_core_ppu_pidr1_t; 3705 3706 static inline uint64_t ODY_DSUUBX_CORE_PPU_PIDR1(uint64_t a) __attribute__ ((pure, always_inline)); 3707 static inline uint64_t ODY_DSUUBX_CORE_PPU_PIDR1(uint64_t a) 3708 { 3709 if (a <= 89) 3710 return 0x87e2ef080fe4ll + 0x1000000ll * ((a) & 0x7f); 3711 __ody_csr_fatal("DSUUBX_CORE_PPU_PIDR1", 1, a, 0, 0, 0, 0, 0); 3712 } 3713 3714 #define typedef_ODY_DSUUBX_CORE_PPU_PIDR1(a) ody_dsuubx_core_ppu_pidr1_t 3715 #define bustype_ODY_DSUUBX_CORE_PPU_PIDR1(a) CSR_TYPE_RSL32b 3716 #define basename_ODY_DSUUBX_CORE_PPU_PIDR1(a) "DSUUBX_CORE_PPU_PIDR1" 3717 #define device_bar_ODY_DSUUBX_CORE_PPU_PIDR1(a) 0x0 /* PF_BAR0 */ 3718 #define busnum_ODY_DSUUBX_CORE_PPU_PIDR1(a) (a) 3719 #define arguments_ODY_DSUUBX_CORE_PPU_PIDR1(a) (a), -1, -1, -1 3720 3721 /** 3722 * Register (RSL32b) dsuub#_core_ppu_pidr2 3723 * 3724 * DSUUB Core PPU Peripheral Identification Register 2 3725 * Provides CoreSight discovery information. 3726 */ 3727 union ody_dsuubx_core_ppu_pidr2 { 3728 uint32_t u; 3729 struct ody_dsuubx_core_ppu_pidr2_s { 3730 uint32_t des_1 : 3; 3731 uint32_t jedec : 1; 3732 uint32_t revision : 4; 3733 uint32_t reserved_8_31 : 24; 3734 } s; 3735 /* struct ody_dsuubx_core_ppu_pidr2_s cn; */ 3736 }; 3737 typedef union ody_dsuubx_core_ppu_pidr2 ody_dsuubx_core_ppu_pidr2_t; 3738 3739 static inline uint64_t ODY_DSUUBX_CORE_PPU_PIDR2(uint64_t a) __attribute__ ((pure, always_inline)); 3740 static inline uint64_t ODY_DSUUBX_CORE_PPU_PIDR2(uint64_t a) 3741 { 3742 if (a <= 89) 3743 return 0x87e2ef080fe8ll + 0x1000000ll * ((a) & 0x7f); 3744 __ody_csr_fatal("DSUUBX_CORE_PPU_PIDR2", 1, a, 0, 0, 0, 0, 0); 3745 } 3746 3747 #define typedef_ODY_DSUUBX_CORE_PPU_PIDR2(a) ody_dsuubx_core_ppu_pidr2_t 3748 #define bustype_ODY_DSUUBX_CORE_PPU_PIDR2(a) CSR_TYPE_RSL32b 3749 #define basename_ODY_DSUUBX_CORE_PPU_PIDR2(a) "DSUUBX_CORE_PPU_PIDR2" 3750 #define device_bar_ODY_DSUUBX_CORE_PPU_PIDR2(a) 0x0 /* PF_BAR0 */ 3751 #define busnum_ODY_DSUUBX_CORE_PPU_PIDR2(a) (a) 3752 #define arguments_ODY_DSUUBX_CORE_PPU_PIDR2(a) (a), -1, -1, -1 3753 3754 /** 3755 * Register (RSL32b) dsuub#_core_ppu_pidr3 3756 * 3757 * DSUUB Core PPU Peripheral Identification Register 3 3758 * Provides CoreSight discovery information. 3759 */ 3760 union ody_dsuubx_core_ppu_pidr3 { 3761 uint32_t u; 3762 struct ody_dsuubx_core_ppu_pidr3_s { 3763 uint32_t cmod : 4; 3764 uint32_t revand : 4; 3765 uint32_t reserved_8_31 : 24; 3766 } s; 3767 /* struct ody_dsuubx_core_ppu_pidr3_s cn; */ 3768 }; 3769 typedef union ody_dsuubx_core_ppu_pidr3 ody_dsuubx_core_ppu_pidr3_t; 3770 3771 static inline uint64_t ODY_DSUUBX_CORE_PPU_PIDR3(uint64_t a) __attribute__ ((pure, always_inline)); 3772 static inline uint64_t ODY_DSUUBX_CORE_PPU_PIDR3(uint64_t a) 3773 { 3774 if (a <= 89) 3775 return 0x87e2ef080fecll + 0x1000000ll * ((a) & 0x7f); 3776 __ody_csr_fatal("DSUUBX_CORE_PPU_PIDR3", 1, a, 0, 0, 0, 0, 0); 3777 } 3778 3779 #define typedef_ODY_DSUUBX_CORE_PPU_PIDR3(a) ody_dsuubx_core_ppu_pidr3_t 3780 #define bustype_ODY_DSUUBX_CORE_PPU_PIDR3(a) CSR_TYPE_RSL32b 3781 #define basename_ODY_DSUUBX_CORE_PPU_PIDR3(a) "DSUUBX_CORE_PPU_PIDR3" 3782 #define device_bar_ODY_DSUUBX_CORE_PPU_PIDR3(a) 0x0 /* PF_BAR0 */ 3783 #define busnum_ODY_DSUUBX_CORE_PPU_PIDR3(a) (a) 3784 #define arguments_ODY_DSUUBX_CORE_PPU_PIDR3(a) (a), -1, -1, -1 3785 3786 /** 3787 * Register (RSL32b) dsuub#_core_ppu_pidr4 3788 * 3789 * DSUUB Core PPU Peripheral Identification Register 4 3790 * Provides CoreSight discovery information. 3791 */ 3792 union ody_dsuubx_core_ppu_pidr4 { 3793 uint32_t u; 3794 struct ody_dsuubx_core_ppu_pidr4_s { 3795 uint32_t des_2 : 4; 3796 uint32_t size : 4; 3797 uint32_t reserved_8_31 : 24; 3798 } s; 3799 /* struct ody_dsuubx_core_ppu_pidr4_s cn; */ 3800 }; 3801 typedef union ody_dsuubx_core_ppu_pidr4 ody_dsuubx_core_ppu_pidr4_t; 3802 3803 static inline uint64_t ODY_DSUUBX_CORE_PPU_PIDR4(uint64_t a) __attribute__ ((pure, always_inline)); 3804 static inline uint64_t ODY_DSUUBX_CORE_PPU_PIDR4(uint64_t a) 3805 { 3806 if (a <= 89) 3807 return 0x87e2ef080fd0ll + 0x1000000ll * ((a) & 0x7f); 3808 __ody_csr_fatal("DSUUBX_CORE_PPU_PIDR4", 1, a, 0, 0, 0, 0, 0); 3809 } 3810 3811 #define typedef_ODY_DSUUBX_CORE_PPU_PIDR4(a) ody_dsuubx_core_ppu_pidr4_t 3812 #define bustype_ODY_DSUUBX_CORE_PPU_PIDR4(a) CSR_TYPE_RSL32b 3813 #define basename_ODY_DSUUBX_CORE_PPU_PIDR4(a) "DSUUBX_CORE_PPU_PIDR4" 3814 #define device_bar_ODY_DSUUBX_CORE_PPU_PIDR4(a) 0x0 /* PF_BAR0 */ 3815 #define busnum_ODY_DSUUBX_CORE_PPU_PIDR4(a) (a) 3816 #define arguments_ODY_DSUUBX_CORE_PPU_PIDR4(a) (a), -1, -1, -1 3817 3818 /** 3819 * Register (RSL32b) dsuub#_core_ppu_pidr5 3820 * 3821 * DSUUB Core PPU Peripheral Identification Register 5 3822 * Provides CoreSight discovery information. 3823 */ 3824 union ody_dsuubx_core_ppu_pidr5 { 3825 uint32_t u; 3826 struct ody_dsuubx_core_ppu_pidr5_s { 3827 uint32_t reserved_0_31 : 32; 3828 } s; 3829 /* struct ody_dsuubx_core_ppu_pidr5_s cn; */ 3830 }; 3831 typedef union ody_dsuubx_core_ppu_pidr5 ody_dsuubx_core_ppu_pidr5_t; 3832 3833 static inline uint64_t ODY_DSUUBX_CORE_PPU_PIDR5(uint64_t a) __attribute__ ((pure, always_inline)); 3834 static inline uint64_t ODY_DSUUBX_CORE_PPU_PIDR5(uint64_t a) 3835 { 3836 if (a <= 89) 3837 return 0x87e2ef080fd4ll + 0x1000000ll * ((a) & 0x7f); 3838 __ody_csr_fatal("DSUUBX_CORE_PPU_PIDR5", 1, a, 0, 0, 0, 0, 0); 3839 } 3840 3841 #define typedef_ODY_DSUUBX_CORE_PPU_PIDR5(a) ody_dsuubx_core_ppu_pidr5_t 3842 #define bustype_ODY_DSUUBX_CORE_PPU_PIDR5(a) CSR_TYPE_RSL32b 3843 #define basename_ODY_DSUUBX_CORE_PPU_PIDR5(a) "DSUUBX_CORE_PPU_PIDR5" 3844 #define device_bar_ODY_DSUUBX_CORE_PPU_PIDR5(a) 0x0 /* PF_BAR0 */ 3845 #define busnum_ODY_DSUUBX_CORE_PPU_PIDR5(a) (a) 3846 #define arguments_ODY_DSUUBX_CORE_PPU_PIDR5(a) (a), -1, -1, -1 3847 3848 /** 3849 * Register (RSL32b) dsuub#_core_ppu_pidr6 3850 * 3851 * DSUUB Core PPU Peripheral Identification Register 6 3852 * Provides CoreSight discovery information. 3853 */ 3854 union ody_dsuubx_core_ppu_pidr6 { 3855 uint32_t u; 3856 struct ody_dsuubx_core_ppu_pidr6_s { 3857 uint32_t reserved_0_31 : 32; 3858 } s; 3859 /* struct ody_dsuubx_core_ppu_pidr6_s cn; */ 3860 }; 3861 typedef union ody_dsuubx_core_ppu_pidr6 ody_dsuubx_core_ppu_pidr6_t; 3862 3863 static inline uint64_t ODY_DSUUBX_CORE_PPU_PIDR6(uint64_t a) __attribute__ ((pure, always_inline)); 3864 static inline uint64_t ODY_DSUUBX_CORE_PPU_PIDR6(uint64_t a) 3865 { 3866 if (a <= 89) 3867 return 0x87e2ef080fd8ll + 0x1000000ll * ((a) & 0x7f); 3868 __ody_csr_fatal("DSUUBX_CORE_PPU_PIDR6", 1, a, 0, 0, 0, 0, 0); 3869 } 3870 3871 #define typedef_ODY_DSUUBX_CORE_PPU_PIDR6(a) ody_dsuubx_core_ppu_pidr6_t 3872 #define bustype_ODY_DSUUBX_CORE_PPU_PIDR6(a) CSR_TYPE_RSL32b 3873 #define basename_ODY_DSUUBX_CORE_PPU_PIDR6(a) "DSUUBX_CORE_PPU_PIDR6" 3874 #define device_bar_ODY_DSUUBX_CORE_PPU_PIDR6(a) 0x0 /* PF_BAR0 */ 3875 #define busnum_ODY_DSUUBX_CORE_PPU_PIDR6(a) (a) 3876 #define arguments_ODY_DSUUBX_CORE_PPU_PIDR6(a) (a), -1, -1, -1 3877 3878 /** 3879 * Register (RSL32b) dsuub#_core_ppu_pidr7 3880 * 3881 * DSUUB Core PPU Peripheral Identification Register 7 3882 * Provides CoreSight discovery information. 3883 */ 3884 union ody_dsuubx_core_ppu_pidr7 { 3885 uint32_t u; 3886 struct ody_dsuubx_core_ppu_pidr7_s { 3887 uint32_t reserved_0_31 : 32; 3888 } s; 3889 /* struct ody_dsuubx_core_ppu_pidr7_s cn; */ 3890 }; 3891 typedef union ody_dsuubx_core_ppu_pidr7 ody_dsuubx_core_ppu_pidr7_t; 3892 3893 static inline uint64_t ODY_DSUUBX_CORE_PPU_PIDR7(uint64_t a) __attribute__ ((pure, always_inline)); 3894 static inline uint64_t ODY_DSUUBX_CORE_PPU_PIDR7(uint64_t a) 3895 { 3896 if (a <= 89) 3897 return 0x87e2ef080fdcll + 0x1000000ll * ((a) & 0x7f); 3898 __ody_csr_fatal("DSUUBX_CORE_PPU_PIDR7", 1, a, 0, 0, 0, 0, 0); 3899 } 3900 3901 #define typedef_ODY_DSUUBX_CORE_PPU_PIDR7(a) ody_dsuubx_core_ppu_pidr7_t 3902 #define bustype_ODY_DSUUBX_CORE_PPU_PIDR7(a) CSR_TYPE_RSL32b 3903 #define basename_ODY_DSUUBX_CORE_PPU_PIDR7(a) "DSUUBX_CORE_PPU_PIDR7" 3904 #define device_bar_ODY_DSUUBX_CORE_PPU_PIDR7(a) 0x0 /* PF_BAR0 */ 3905 #define busnum_ODY_DSUUBX_CORE_PPU_PIDR7(a) (a) 3906 #define arguments_ODY_DSUUBX_CORE_PPU_PIDR7(a) (a), -1, -1, -1 3907 3908 /** 3909 * Register (RSL32b) dsuub#_core_ppu_pmer 3910 * 3911 * DSUUB Core Power Mode Emulation Enable Register 3912 * This register allows software to enable entry into emulated modes. 3913 */ 3914 union ody_dsuubx_core_ppu_pmer { 3915 uint32_t u; 3916 struct ody_dsuubx_core_ppu_pmer_s { 3917 uint32_t emu_en : 1; 3918 uint32_t reserved_1_31 : 31; 3919 } s; 3920 /* struct ody_dsuubx_core_ppu_pmer_s cn; */ 3921 }; 3922 typedef union ody_dsuubx_core_ppu_pmer ody_dsuubx_core_ppu_pmer_t; 3923 3924 static inline uint64_t ODY_DSUUBX_CORE_PPU_PMER(uint64_t a) __attribute__ ((pure, always_inline)); 3925 static inline uint64_t ODY_DSUUBX_CORE_PPU_PMER(uint64_t a) 3926 { 3927 if (a <= 89) 3928 return 0x87e2ef080004ll + 0x1000000ll * ((a) & 0x7f); 3929 __ody_csr_fatal("DSUUBX_CORE_PPU_PMER", 1, a, 0, 0, 0, 0, 0); 3930 } 3931 3932 #define typedef_ODY_DSUUBX_CORE_PPU_PMER(a) ody_dsuubx_core_ppu_pmer_t 3933 #define bustype_ODY_DSUUBX_CORE_PPU_PMER(a) CSR_TYPE_RSL32b 3934 #define basename_ODY_DSUUBX_CORE_PPU_PMER(a) "DSUUBX_CORE_PPU_PMER" 3935 #define device_bar_ODY_DSUUBX_CORE_PPU_PMER(a) 0x0 /* PF_BAR0 */ 3936 #define busnum_ODY_DSUUBX_CORE_PPU_PMER(a) (a) 3937 #define arguments_ODY_DSUUBX_CORE_PPU_PMER(a) (a), -1, -1, -1 3938 3939 /** 3940 * Register (RSL32b) dsuub#_core_ppu_ptcr 3941 * 3942 * DSUUB Core Power Mode Transition Register 3943 * This register contains settings which affect the behaviour of certain power mode transitions. 3944 */ 3945 union ody_dsuubx_core_ppu_ptcr { 3946 uint32_t u; 3947 struct ody_dsuubx_core_ppu_ptcr_s { 3948 uint32_t warm_rst_devreqen : 1; 3949 uint32_t dbg_recov_porst_en : 1; 3950 uint32_t reserved_2_31 : 30; 3951 } s; 3952 /* struct ody_dsuubx_core_ppu_ptcr_s cn; */ 3953 }; 3954 typedef union ody_dsuubx_core_ppu_ptcr ody_dsuubx_core_ppu_ptcr_t; 3955 3956 static inline uint64_t ODY_DSUUBX_CORE_PPU_PTCR(uint64_t a) __attribute__ ((pure, always_inline)); 3957 static inline uint64_t ODY_DSUUBX_CORE_PPU_PTCR(uint64_t a) 3958 { 3959 if (a <= 89) 3960 return 0x87e2ef080024ll + 0x1000000ll * ((a) & 0x7f); 3961 __ody_csr_fatal("DSUUBX_CORE_PPU_PTCR", 1, a, 0, 0, 0, 0, 0); 3962 } 3963 3964 #define typedef_ODY_DSUUBX_CORE_PPU_PTCR(a) ody_dsuubx_core_ppu_ptcr_t 3965 #define bustype_ODY_DSUUBX_CORE_PPU_PTCR(a) CSR_TYPE_RSL32b 3966 #define basename_ODY_DSUUBX_CORE_PPU_PTCR(a) "DSUUBX_CORE_PPU_PTCR" 3967 #define device_bar_ODY_DSUUBX_CORE_PPU_PTCR(a) 0x0 /* PF_BAR0 */ 3968 #define busnum_ODY_DSUUBX_CORE_PPU_PTCR(a) (a) 3969 #define arguments_ODY_DSUUBX_CORE_PPU_PTCR(a) (a), -1, -1, -1 3970 3971 /** 3972 * Register (RSL32b) dsuub#_core_ppu_pwcr 3973 * 3974 * DSUUB Core Power Configuration Register 3975 * This register controls enabling and disabling of hardware control inputs to the PPU. 3976 * 3977 * Before software programs the DEVREQEN bits it must configure the PPU for static 3978 * transitions and ensure the requested power mode has been reached, this means that no 3979 * further transitions can occur, otherwise behavior is UNPREDICTABLE. 3980 * 3981 * The PWR_DEVACTIVEEN and OP_DEVACTIVEEN fields in this register control the ability of the 3982 * DEVACTIVE inputs to initiate power mode transitions, but not the ability to generate input edge 3983 * interrupt events. 3984 */ 3985 union ody_dsuubx_core_ppu_pwcr { 3986 uint32_t u; 3987 struct ody_dsuubx_core_ppu_pwcr_s { 3988 uint32_t devreqen : 1; 3989 uint32_t reserved_1_8 : 8; 3990 uint32_t pwr_devactiveen1 : 1; 3991 uint32_t reserved_10_12 : 3; 3992 uint32_t pwr_devactiveen5 : 1; 3993 uint32_t reserved_14 : 1; 3994 uint32_t pwr_devactiveen7 : 1; 3995 uint32_t pwr_devactiveen8 : 1; 3996 uint32_t pwr_devactiveen9 : 1; 3997 uint32_t pwr_devactiveen10 : 1; 3998 uint32_t reserved_19_31 : 13; 3999 } s; 4000 /* struct ody_dsuubx_core_ppu_pwcr_s cn; */ 4001 }; 4002 typedef union ody_dsuubx_core_ppu_pwcr ody_dsuubx_core_ppu_pwcr_t; 4003 4004 static inline uint64_t ODY_DSUUBX_CORE_PPU_PWCR(uint64_t a) __attribute__ ((pure, always_inline)); 4005 static inline uint64_t ODY_DSUUBX_CORE_PPU_PWCR(uint64_t a) 4006 { 4007 if (a <= 89) 4008 return 0x87e2ef080020ll + 0x1000000ll * ((a) & 0x7f); 4009 __ody_csr_fatal("DSUUBX_CORE_PPU_PWCR", 1, a, 0, 0, 0, 0, 0); 4010 } 4011 4012 #define typedef_ODY_DSUUBX_CORE_PPU_PWCR(a) ody_dsuubx_core_ppu_pwcr_t 4013 #define bustype_ODY_DSUUBX_CORE_PPU_PWCR(a) CSR_TYPE_RSL32b 4014 #define basename_ODY_DSUUBX_CORE_PPU_PWCR(a) "DSUUBX_CORE_PPU_PWCR" 4015 #define device_bar_ODY_DSUUBX_CORE_PPU_PWCR(a) 0x0 /* PF_BAR0 */ 4016 #define busnum_ODY_DSUUBX_CORE_PPU_PWCR(a) (a) 4017 #define arguments_ODY_DSUUBX_CORE_PPU_PWCR(a) (a), -1, -1, -1 4018 4019 /** 4020 * Register (RSL32b) dsuub#_core_ppu_pwpr 4021 * 4022 * DSUUB Core Power Policy Register 4023 * This register enables software to program both power and operating mode policy. It also contains 4024 * related settings including the enable for dynamic transitions and the lock enable. 4025 * 4026 * This register does not reflect the current power mode value. The current power mode of the 4027 * domain is reflected in the Power Status Register (PPU_PWSR). 4028 */ 4029 union ody_dsuubx_core_ppu_pwpr { 4030 uint32_t u; 4031 struct ody_dsuubx_core_ppu_pwpr_s { 4032 uint32_t pwr_policy : 4; 4033 uint32_t reserved_4_7 : 4; 4034 uint32_t pwr_dyn_en : 1; 4035 uint32_t reserved_9_11 : 3; 4036 uint32_t lock_en : 1; 4037 uint32_t reserved_13_31 : 19; 4038 } s; 4039 /* struct ody_dsuubx_core_ppu_pwpr_s cn; */ 4040 }; 4041 typedef union ody_dsuubx_core_ppu_pwpr ody_dsuubx_core_ppu_pwpr_t; 4042 4043 static inline uint64_t ODY_DSUUBX_CORE_PPU_PWPR(uint64_t a) __attribute__ ((pure, always_inline)); 4044 static inline uint64_t ODY_DSUUBX_CORE_PPU_PWPR(uint64_t a) 4045 { 4046 if (a <= 89) 4047 return 0x87e2ef080000ll + 0x1000000ll * ((a) & 0x7f); 4048 __ody_csr_fatal("DSUUBX_CORE_PPU_PWPR", 1, a, 0, 0, 0, 0, 0); 4049 } 4050 4051 #define typedef_ODY_DSUUBX_CORE_PPU_PWPR(a) ody_dsuubx_core_ppu_pwpr_t 4052 #define bustype_ODY_DSUUBX_CORE_PPU_PWPR(a) CSR_TYPE_RSL32b 4053 #define basename_ODY_DSUUBX_CORE_PPU_PWPR(a) "DSUUBX_CORE_PPU_PWPR" 4054 #define device_bar_ODY_DSUUBX_CORE_PPU_PWPR(a) 0x0 /* PF_BAR0 */ 4055 #define busnum_ODY_DSUUBX_CORE_PPU_PWPR(a) (a) 4056 #define arguments_ODY_DSUUBX_CORE_PPU_PWPR(a) (a), -1, -1, -1 4057 4058 /** 4059 * Register (RSL32b) dsuub#_core_ppu_pwsr 4060 * 4061 * DSUUB Core Power Status Register 4062 * This read-only register contains status information for the power mode, operating mode, dynamic 4063 * transitions, and lock feature. 4064 */ 4065 union ody_dsuubx_core_ppu_pwsr { 4066 uint32_t u; 4067 struct ody_dsuubx_core_ppu_pwsr_s { 4068 uint32_t pwr_status : 4; 4069 uint32_t reserved_4_7 : 4; 4070 uint32_t pwr_dyn_status : 1; 4071 uint32_t reserved_9_11 : 3; 4072 uint32_t lock_status : 1; 4073 uint32_t reserved_13_31 : 19; 4074 } s; 4075 /* struct ody_dsuubx_core_ppu_pwsr_s cn; */ 4076 }; 4077 typedef union ody_dsuubx_core_ppu_pwsr ody_dsuubx_core_ppu_pwsr_t; 4078 4079 static inline uint64_t ODY_DSUUBX_CORE_PPU_PWSR(uint64_t a) __attribute__ ((pure, always_inline)); 4080 static inline uint64_t ODY_DSUUBX_CORE_PPU_PWSR(uint64_t a) 4081 { 4082 if (a <= 89) 4083 return 0x87e2ef080008ll + 0x1000000ll * ((a) & 0x7f); 4084 __ody_csr_fatal("DSUUBX_CORE_PPU_PWSR", 1, a, 0, 0, 0, 0, 0); 4085 } 4086 4087 #define typedef_ODY_DSUUBX_CORE_PPU_PWSR(a) ody_dsuubx_core_ppu_pwsr_t 4088 #define bustype_ODY_DSUUBX_CORE_PPU_PWSR(a) CSR_TYPE_RSL32b 4089 #define basename_ODY_DSUUBX_CORE_PPU_PWSR(a) "DSUUBX_CORE_PPU_PWSR" 4090 #define device_bar_ODY_DSUUBX_CORE_PPU_PWSR(a) 0x0 /* PF_BAR0 */ 4091 #define busnum_ODY_DSUUBX_CORE_PPU_PWSR(a) (a) 4092 #define arguments_ODY_DSUUBX_CORE_PPU_PWSR(a) (a), -1, -1, -1 4093 4094 /** 4095 * Register (RSL32b) dsuub#_core_ppu_stsr 4096 * 4097 * DSUUB Core Stored Status Register 4098 * This register is reserved for P-Channel PPUs. 4099 */ 4100 union ody_dsuubx_core_ppu_stsr { 4101 uint32_t u; 4102 struct ody_dsuubx_core_ppu_stsr_s { 4103 uint32_t stored_devdeny : 8; 4104 uint32_t reserved_8_31 : 24; 4105 } s; 4106 /* struct ody_dsuubx_core_ppu_stsr_s cn; */ 4107 }; 4108 typedef union ody_dsuubx_core_ppu_stsr ody_dsuubx_core_ppu_stsr_t; 4109 4110 static inline uint64_t ODY_DSUUBX_CORE_PPU_STSR(uint64_t a) __attribute__ ((pure, always_inline)); 4111 static inline uint64_t ODY_DSUUBX_CORE_PPU_STSR(uint64_t a) 4112 { 4113 if (a <= 89) 4114 return 0x87e2ef080018ll + 0x1000000ll * ((a) & 0x7f); 4115 __ody_csr_fatal("DSUUBX_CORE_PPU_STSR", 1, a, 0, 0, 0, 0, 0); 4116 } 4117 4118 #define typedef_ODY_DSUUBX_CORE_PPU_STSR(a) ody_dsuubx_core_ppu_stsr_t 4119 #define bustype_ODY_DSUUBX_CORE_PPU_STSR(a) CSR_TYPE_RSL32b 4120 #define basename_ODY_DSUUBX_CORE_PPU_STSR(a) "DSUUBX_CORE_PPU_STSR" 4121 #define device_bar_ODY_DSUUBX_CORE_PPU_STSR(a) 0x0 /* PF_BAR0 */ 4122 #define busnum_ODY_DSUUBX_CORE_PPU_STSR(a) (a) 4123 #define arguments_ODY_DSUUBX_CORE_PPU_STSR(a) (a), -1, -1, -1 4124 4125 /** 4126 * Register (RSL32b) dsuub#_core_ppu_unlk 4127 * 4128 * DSUUB Core Unlock Register 4129 * This register allows software to unlock the PPU from a locked power mode. 4130 */ 4131 union ody_dsuubx_core_ppu_unlk { 4132 uint32_t u; 4133 struct ody_dsuubx_core_ppu_unlk_s { 4134 uint32_t unlock : 1; 4135 uint32_t reserved_1_31 : 31; 4136 } s; 4137 /* struct ody_dsuubx_core_ppu_unlk_s cn; */ 4138 }; 4139 typedef union ody_dsuubx_core_ppu_unlk ody_dsuubx_core_ppu_unlk_t; 4140 4141 static inline uint64_t ODY_DSUUBX_CORE_PPU_UNLK(uint64_t a) __attribute__ ((pure, always_inline)); 4142 static inline uint64_t ODY_DSUUBX_CORE_PPU_UNLK(uint64_t a) 4143 { 4144 if (a <= 89) 4145 return 0x87e2ef08001cll + 0x1000000ll * ((a) & 0x7f); 4146 __ody_csr_fatal("DSUUBX_CORE_PPU_UNLK", 1, a, 0, 0, 0, 0, 0); 4147 } 4148 4149 #define typedef_ODY_DSUUBX_CORE_PPU_UNLK(a) ody_dsuubx_core_ppu_unlk_t 4150 #define bustype_ODY_DSUUBX_CORE_PPU_UNLK(a) CSR_TYPE_RSL32b 4151 #define basename_ODY_DSUUBX_CORE_PPU_UNLK(a) "DSUUBX_CORE_PPU_UNLK" 4152 #define device_bar_ODY_DSUUBX_CORE_PPU_UNLK(a) 0x0 /* PF_BAR0 */ 4153 #define busnum_ODY_DSUUBX_CORE_PPU_UNLK(a) (a) 4154 #define arguments_ODY_DSUUBX_CORE_PPU_UNLK(a) (a), -1, -1, -1 4155 4156 /** 4157 * Register (RSL) dsuub#_cpumpmmcr_el3 4158 * 4159 * Dsuub MPMM Control Register 4160 * This register controls whether MPMM is enabled and selects the currently active MPMM "gear." 4161 */ 4162 union ody_dsuubx_cpumpmmcr_el3 { 4163 uint64_t u; 4164 struct ody_dsuubx_cpumpmmcr_el3_s { 4165 uint64_t mpmm_en : 1; 4166 uint64_t mpmm_gear : 2; 4167 uint64_t reserved_3_63 : 61; 4168 } s; 4169 /* struct ody_dsuubx_cpumpmmcr_el3_s cn; */ 4170 }; 4171 typedef union ody_dsuubx_cpumpmmcr_el3 ody_dsuubx_cpumpmmcr_el3_t; 4172 4173 static inline uint64_t ODY_DSUUBX_CPUMPMMCR_EL3(uint64_t a) __attribute__ ((pure, always_inline)); 4174 static inline uint64_t ODY_DSUUBX_CPUMPMMCR_EL3(uint64_t a) 4175 { 4176 if (a <= 89) 4177 return 0x87e2ef0b0010ll + 0x1000000ll * ((a) & 0x7f); 4178 __ody_csr_fatal("DSUUBX_CPUMPMMCR_EL3", 1, a, 0, 0, 0, 0, 0); 4179 } 4180 4181 #define typedef_ODY_DSUUBX_CPUMPMMCR_EL3(a) ody_dsuubx_cpumpmmcr_el3_t 4182 #define bustype_ODY_DSUUBX_CPUMPMMCR_EL3(a) CSR_TYPE_RSL 4183 #define basename_ODY_DSUUBX_CPUMPMMCR_EL3(a) "DSUUBX_CPUMPMMCR_EL3" 4184 #define device_bar_ODY_DSUUBX_CPUMPMMCR_EL3(a) 0x0 /* PF_BAR0 */ 4185 #define busnum_ODY_DSUUBX_CPUMPMMCR_EL3(a) (a) 4186 #define arguments_ODY_DSUUBX_CPUMPMMCR_EL3(a) (a), -1, -1, -1 4187 4188 /** 4189 * Register (RSL) dsuub#_cpuppmcr_el3 4190 * 4191 * Dsuub Global PPM Configuration Register 4192 * This register controls global PPM features and allows discovery of the PPM implementation details. 4193 */ 4194 union ody_dsuubx_cpuppmcr_el3 { 4195 uint64_t u; 4196 struct ody_dsuubx_cpuppmcr_el3_s { 4197 uint64_t mpmmpinctl : 1; 4198 uint64_t pdppinctl : 1; 4199 uint64_t reserved_2_7 : 6; 4200 uint64_t mpmm_gears : 3; 4201 uint64_t reserved_11_15 : 5; 4202 uint64_t pdp_setps : 2; 4203 uint64_t pdp_extms : 1; 4204 uint64_t reserved_19_63 : 45; 4205 } s; 4206 /* struct ody_dsuubx_cpuppmcr_el3_s cn; */ 4207 }; 4208 typedef union ody_dsuubx_cpuppmcr_el3 ody_dsuubx_cpuppmcr_el3_t; 4209 4210 static inline uint64_t ODY_DSUUBX_CPUPPMCR_EL3(uint64_t a) __attribute__ ((pure, always_inline)); 4211 static inline uint64_t ODY_DSUUBX_CPUPPMCR_EL3(uint64_t a) 4212 { 4213 if (a <= 89) 4214 return 0x87e2ef0b0000ll + 0x1000000ll * ((a) & 0x7f); 4215 __ody_csr_fatal("DSUUBX_CPUPPMCR_EL3", 1, a, 0, 0, 0, 0, 0); 4216 } 4217 4218 #define typedef_ODY_DSUUBX_CPUPPMCR_EL3(a) ody_dsuubx_cpuppmcr_el3_t 4219 #define bustype_ODY_DSUUBX_CPUPPMCR_EL3(a) CSR_TYPE_RSL 4220 #define basename_ODY_DSUUBX_CPUPPMCR_EL3(a) "DSUUBX_CPUPPMCR_EL3" 4221 #define device_bar_ODY_DSUUBX_CPUPPMCR_EL3(a) 0x0 /* PF_BAR0 */ 4222 #define busnum_ODY_DSUUBX_CPUPPMCR_EL3(a) (a) 4223 #define arguments_ODY_DSUUBX_CPUPPMCR_EL3(a) (a), -1, -1, -1 4224 4225 /** 4226 * Register (RSL) dsuub#_cpuppmpdpcr_el1 4227 * 4228 * Dsuub PDP Control Register 4229 * This register controls the aggressiveness of the PDP feature. The core and external memory 4230 * system reduction features may be independently controlled. 4231 */ 4232 union ody_dsuubx_cpuppmpdpcr_el1 { 4233 uint64_t u; 4234 struct ody_dsuubx_cpuppmpdpcr_el1_s { 4235 uint64_t pdp_core_set : 2; 4236 uint64_t reserved_2_31 : 30; 4237 uint64_t pdp_extms_set : 2; 4238 uint64_t reserved_34_63 : 30; 4239 } s; 4240 /* struct ody_dsuubx_cpuppmpdpcr_el1_s cn; */ 4241 }; 4242 typedef union ody_dsuubx_cpuppmpdpcr_el1 ody_dsuubx_cpuppmpdpcr_el1_t; 4243 4244 static inline uint64_t ODY_DSUUBX_CPUPPMPDPCR_EL1(uint64_t a) __attribute__ ((pure, always_inline)); 4245 static inline uint64_t ODY_DSUUBX_CPUPPMPDPCR_EL1(uint64_t a) 4246 { 4247 if (a <= 89) 4248 return 0x87e2ef0b0020ll + 0x1000000ll * ((a) & 0x7f); 4249 __ody_csr_fatal("DSUUBX_CPUPPMPDPCR_EL1", 1, a, 0, 0, 0, 0, 0); 4250 } 4251 4252 #define typedef_ODY_DSUUBX_CPUPPMPDPCR_EL1(a) ody_dsuubx_cpuppmpdpcr_el1_t 4253 #define bustype_ODY_DSUUBX_CPUPPMPDPCR_EL1(a) CSR_TYPE_RSL 4254 #define basename_ODY_DSUUBX_CPUPPMPDPCR_EL1(a) "DSUUBX_CPUPPMPDPCR_EL1" 4255 #define device_bar_ODY_DSUUBX_CPUPPMPDPCR_EL1(a) 0x0 /* PF_BAR0 */ 4256 #define busnum_ODY_DSUUBX_CPUPPMPDPCR_EL1(a) (a) 4257 #define arguments_ODY_DSUUBX_CPUPPMPDPCR_EL1(a) (a), -1, -1, -1 4258 4259 #endif /* __ODY_CSRS_DSUUB_H__ */ 4260