1 #ifndef __ODY_CSRS_CPC_H__ 2 #define __ODY_CSRS_CPC_H__ 3 /* This file is auto-generated. Do not edit */ 4 5 /***********************license start*********************************** 6 * Copyright (C) 2021-2026 Marvell. 7 * SPDX-License-Identifier: BSD-3-Clause 8 * https://spdx.org/licenses 9 ***********************license end**************************************/ 10 11 12 /** 13 * @file 14 * 15 * Configuration and status register (CSR) address and type definitions for 16 * CPC. 17 * 18 * This file is auto generated. Do not edit. 19 * 20 */ 21 22 /** 23 * Enumeration cpc_bar_e 24 * 25 * CPC Base Address Register Enumeration 26 * Enumerates the base address registers. 27 */ 28 #define ODY_CPC_BAR_E_CPC_PF_BAR0 (0x86d000000000ll) 29 #define ODY_CPC_BAR_E_CPC_PF_BAR0_SIZE 0x800000ull 30 31 /** 32 * Enumeration cpc_permit_e 33 * 34 * CPC Permit Enumeration 35 * Enumerates the permissions for CPC access. 36 */ 37 #define ODY_CPC_PERMIT_E_CCP_DIS (4) 38 #define ODY_CPC_PERMIT_E_EHSM_DIS (5) 39 #define ODY_CPC_PERMIT_E_MCP_DIS (1) 40 #define ODY_CPC_PERMIT_E_NSEC_DIS (3) 41 #define ODY_CPC_PERMIT_E_SCP_DIS (0) 42 #define ODY_CPC_PERMIT_E_SEC_DIS (2) 43 44 /** 45 * Enumeration cpc_xcp_map_e 46 * 47 * CPC XCP Number Mapping Enumeration 48 * Enumerates the XCP mapping. 49 */ 50 #define ODY_CPC_XCP_MAP_E_CCP (2) 51 #define ODY_CPC_XCP_MAP_E_MCP (1) 52 #define ODY_CPC_XCP_MAP_E_SCP (0) 53 54 /** 55 * Register (NCB32b) cpc_boot_owner# 56 * 57 * CPC Boot Owner Registers 58 * These registers control an external arbiter for the boot device (SPI/eMMC) 59 * across multiple external devices. There is a register for each requester: 60 * _ \<0\> - SCP - reset on SCP reset. 61 * _ \<1\> - MCP - reset on MCP reset. 62 * _ \<2\> - AP Secure - reset on core reset. 63 * _ \<3\> - AP Nonsecure - reset on core reset. 64 * _ \<4\> - CCP - reset on CCP reset. 65 * 66 * These register is only writable to the corresponding requestor(s) permitted with CPC_PERMIT. 67 */ 68 union ody_cpc_boot_ownerx { 69 uint32_t u; 70 struct ody_cpc_boot_ownerx_s { 71 uint32_t boot_req : 1; 72 uint32_t reserved_1_7 : 7; 73 uint32_t boot_wait : 1; 74 uint32_t reserved_9_31 : 23; 75 } s; 76 /* struct ody_cpc_boot_ownerx_s cn; */ 77 }; 78 typedef union ody_cpc_boot_ownerx ody_cpc_boot_ownerx_t; 79 80 static inline uint64_t ODY_CPC_BOOT_OWNERX(uint64_t a) __attribute__ ((pure, always_inline)); 81 static inline uint64_t ODY_CPC_BOOT_OWNERX(uint64_t a) 82 { 83 if (a <= 4) 84 return 0x86d0000001c0ll + 8ll * ((a) & 0x7); 85 __ody_csr_fatal("CPC_BOOT_OWNERX", 1, a, 0, 0, 0, 0, 0); 86 } 87 88 #define typedef_ODY_CPC_BOOT_OWNERX(a) ody_cpc_boot_ownerx_t 89 #define bustype_ODY_CPC_BOOT_OWNERX(a) CSR_TYPE_NCB32b 90 #define basename_ODY_CPC_BOOT_OWNERX(a) "CPC_BOOT_OWNERX" 91 #define device_bar_ODY_CPC_BOOT_OWNERX(a) 0x0 /* PF_BAR0 */ 92 #define busnum_ODY_CPC_BOOT_OWNERX(a) (a) 93 #define arguments_ODY_CPC_BOOT_OWNERX(a) (a), -1, -1, -1 94 95 /** 96 * Register (NCB32b) cpc_boot_rom_limit 97 * 98 * CPC Boot ROM Limit Register 99 * This register contains the address limit in the internal boot ROM that non-XCP processors can 100 * access. 101 * 102 * This register is only writable to the requestor(s) permitted with CPC_PERMIT. 103 * 104 * This register is reset on chip reset. 105 */ 106 union ody_cpc_boot_rom_limit { 107 uint32_t u; 108 struct ody_cpc_boot_rom_limit_s { 109 uint32_t reserved_0_2 : 3; 110 uint32_t addr : 14; 111 uint32_t reserved_17_31 : 15; 112 } s; 113 /* struct ody_cpc_boot_rom_limit_s cn; */ 114 }; 115 typedef union ody_cpc_boot_rom_limit ody_cpc_boot_rom_limit_t; 116 117 #define ODY_CPC_BOOT_ROM_LIMIT ODY_CPC_BOOT_ROM_LIMIT_FUNC() 118 static inline uint64_t ODY_CPC_BOOT_ROM_LIMIT_FUNC(void) __attribute__ ((pure, always_inline)); 119 static inline uint64_t ODY_CPC_BOOT_ROM_LIMIT_FUNC(void) 120 { 121 return 0x86d000000158ll; 122 } 123 124 #define typedef_ODY_CPC_BOOT_ROM_LIMIT ody_cpc_boot_rom_limit_t 125 #define bustype_ODY_CPC_BOOT_ROM_LIMIT CSR_TYPE_NCB32b 126 #define basename_ODY_CPC_BOOT_ROM_LIMIT "CPC_BOOT_ROM_LIMIT" 127 #define device_bar_ODY_CPC_BOOT_ROM_LIMIT 0x0 /* PF_BAR0 */ 128 #define busnum_ODY_CPC_BOOT_ROM_LIMIT 0 129 #define arguments_ODY_CPC_BOOT_ROM_LIMIT -1, -1, -1, -1 130 131 /** 132 * Register (NCB32b) cpc_ccp_boot_rom_limit 133 * 134 * CPC CCP Boot ROM Limit Register 135 * This register contains the address limit in the internal boot ROM that CCP can access. 136 * 137 * This register is only accessible to the requestor(s) permitted with CPC_PERMIT. 138 * 139 * This register is reset on chip reset and ccp_reset. 140 */ 141 union ody_cpc_ccp_boot_rom_limit { 142 uint32_t u; 143 struct ody_cpc_ccp_boot_rom_limit_s { 144 uint32_t reserved_0_2 : 3; 145 uint32_t addr : 14; 146 uint32_t reserved_17_31 : 15; 147 } s; 148 /* struct ody_cpc_ccp_boot_rom_limit_s cn; */ 149 }; 150 typedef union ody_cpc_ccp_boot_rom_limit ody_cpc_ccp_boot_rom_limit_t; 151 152 #define ODY_CPC_CCP_BOOT_ROM_LIMIT ODY_CPC_CCP_BOOT_ROM_LIMIT_FUNC() 153 static inline uint64_t ODY_CPC_CCP_BOOT_ROM_LIMIT_FUNC(void) __attribute__ ((pure, always_inline)); 154 static inline uint64_t ODY_CPC_CCP_BOOT_ROM_LIMIT_FUNC(void) 155 { 156 return 0x86d000000168ll; 157 } 158 159 #define typedef_ODY_CPC_CCP_BOOT_ROM_LIMIT ody_cpc_ccp_boot_rom_limit_t 160 #define bustype_ODY_CPC_CCP_BOOT_ROM_LIMIT CSR_TYPE_NCB32b 161 #define basename_ODY_CPC_CCP_BOOT_ROM_LIMIT "CPC_CCP_BOOT_ROM_LIMIT" 162 #define device_bar_ODY_CPC_CCP_BOOT_ROM_LIMIT 0x0 /* PF_BAR0 */ 163 #define busnum_ODY_CPC_CCP_BOOT_ROM_LIMIT 0 164 #define arguments_ODY_CPC_CCP_BOOT_ROM_LIMIT -1, -1, -1, -1 165 166 /** 167 * Register (NCB32b) cpc_clken 168 * 169 * CPC Clock Enable Register 170 * This register is only accessible to the requestor(s) permitted with CPC_PERMIT. 171 * 172 * This register is reset on chip reset. 173 */ 174 union ody_cpc_clken { 175 uint32_t u; 176 struct ody_cpc_clken_s { 177 uint32_t clken : 1; 178 uint32_t force_ncbi_clken : 1; 179 uint32_t reserved_2_31 : 30; 180 } s; 181 /* struct ody_cpc_clken_s cn; */ 182 }; 183 typedef union ody_cpc_clken ody_cpc_clken_t; 184 185 #define ODY_CPC_CLKEN ODY_CPC_CLKEN_FUNC() 186 static inline uint64_t ODY_CPC_CLKEN_FUNC(void) __attribute__ ((pure, always_inline)); 187 static inline uint64_t ODY_CPC_CLKEN_FUNC(void) 188 { 189 return 0x86d000000118ll; 190 } 191 192 #define typedef_ODY_CPC_CLKEN ody_cpc_clken_t 193 #define bustype_ODY_CPC_CLKEN CSR_TYPE_NCB32b 194 #define basename_ODY_CPC_CLKEN "CPC_CLKEN" 195 #define device_bar_ODY_CPC_CLKEN 0x0 /* PF_BAR0 */ 196 #define busnum_ODY_CPC_CLKEN 0 197 #define arguments_ODY_CPC_CLKEN -1, -1, -1, -1 198 199 /** 200 * Register (NCB32b) cpc_const 201 * 202 * CPC Constants Register 203 * This register is reset on chip reset. 204 */ 205 union ody_cpc_const { 206 uint32_t u; 207 struct ody_cpc_const_s { 208 uint32_t cores : 8; 209 uint32_t mem_regions : 8; 210 uint32_t reserved_16_31 : 16; 211 } s; 212 /* struct ody_cpc_const_s cn; */ 213 }; 214 typedef union ody_cpc_const ody_cpc_const_t; 215 216 #define ODY_CPC_CONST ODY_CPC_CONST_FUNC() 217 static inline uint64_t ODY_CPC_CONST_FUNC(void) __attribute__ ((pure, always_inline)); 218 static inline uint64_t ODY_CPC_CONST_FUNC(void) 219 { 220 return 0x86d000000000ll; 221 } 222 223 #define typedef_ODY_CPC_CONST ody_cpc_const_t 224 #define bustype_ODY_CPC_CONST CSR_TYPE_NCB32b 225 #define basename_ODY_CPC_CONST "CPC_CONST" 226 #define device_bar_ODY_CPC_CONST 0x0 /* PF_BAR0 */ 227 #define busnum_ODY_CPC_CONST 0 228 #define arguments_ODY_CPC_CONST -1, -1, -1, -1 229 230 /** 231 * Register (NCB) cpc_csclk_active_pc 232 * 233 * CPC Conditional Coprocessor Clock Counter Register 234 * This register counts conditional clocks for power management. 235 * 236 * This register is writable for diagnostic use only. 237 * 238 * This register is reset on chip reset. 239 */ 240 union ody_cpc_csclk_active_pc { 241 uint64_t u; 242 struct ody_cpc_csclk_active_pc_s { 243 uint64_t count : 64; 244 } s; 245 /* struct ody_cpc_csclk_active_pc_s cn; */ 246 }; 247 typedef union ody_cpc_csclk_active_pc ody_cpc_csclk_active_pc_t; 248 249 #define ODY_CPC_CSCLK_ACTIVE_PC ODY_CPC_CSCLK_ACTIVE_PC_FUNC() 250 static inline uint64_t ODY_CPC_CSCLK_ACTIVE_PC_FUNC(void) __attribute__ ((pure, always_inline)); 251 static inline uint64_t ODY_CPC_CSCLK_ACTIVE_PC_FUNC(void) 252 { 253 return 0x86d000000010ll; 254 } 255 256 #define typedef_ODY_CPC_CSCLK_ACTIVE_PC ody_cpc_csclk_active_pc_t 257 #define bustype_ODY_CPC_CSCLK_ACTIVE_PC CSR_TYPE_NCB 258 #define basename_ODY_CPC_CSCLK_ACTIVE_PC "CPC_CSCLK_ACTIVE_PC" 259 #define device_bar_ODY_CPC_CSCLK_ACTIVE_PC 0x0 /* PF_BAR0 */ 260 #define busnum_ODY_CPC_CSCLK_ACTIVE_PC 0 261 #define arguments_ODY_CPC_CSCLK_ACTIVE_PC -1, -1, -1, -1 262 263 /** 264 * Register (NCB32b) cpc_mcp_boot_rom_limit 265 * 266 * CPC MCP Boot ROM Limit Register 267 * This register contains the address limit in the internal boot ROM that MCP can access. 268 * 269 * This register is only accessible to the requestor(s) permitted with CPC_PERMIT. 270 * 271 * This register is reset on chip reset and mcp_reset. 272 */ 273 union ody_cpc_mcp_boot_rom_limit { 274 uint32_t u; 275 struct ody_cpc_mcp_boot_rom_limit_s { 276 uint32_t reserved_0_2 : 3; 277 uint32_t addr : 14; 278 uint32_t reserved_17_31 : 15; 279 } s; 280 /* struct ody_cpc_mcp_boot_rom_limit_s cn; */ 281 }; 282 typedef union ody_cpc_mcp_boot_rom_limit ody_cpc_mcp_boot_rom_limit_t; 283 284 #define ODY_CPC_MCP_BOOT_ROM_LIMIT ODY_CPC_MCP_BOOT_ROM_LIMIT_FUNC() 285 static inline uint64_t ODY_CPC_MCP_BOOT_ROM_LIMIT_FUNC(void) __attribute__ ((pure, always_inline)); 286 static inline uint64_t ODY_CPC_MCP_BOOT_ROM_LIMIT_FUNC(void) 287 { 288 return 0x86d000000160ll; 289 } 290 291 #define typedef_ODY_CPC_MCP_BOOT_ROM_LIMIT ody_cpc_mcp_boot_rom_limit_t 292 #define bustype_ODY_CPC_MCP_BOOT_ROM_LIMIT CSR_TYPE_NCB32b 293 #define basename_ODY_CPC_MCP_BOOT_ROM_LIMIT "CPC_MCP_BOOT_ROM_LIMIT" 294 #define device_bar_ODY_CPC_MCP_BOOT_ROM_LIMIT 0x0 /* PF_BAR0 */ 295 #define busnum_ODY_CPC_MCP_BOOT_ROM_LIMIT 0 296 #define arguments_ODY_CPC_MCP_BOOT_ROM_LIMIT -1, -1, -1, -1 297 298 /** 299 * Register (NCB32b) cpc_permit 300 * 301 * CPC Register Permit Registers 302 * This register is used to control CPC register permissions. 303 * 304 * This register is only accessible to the requestor(s) permitted with CPC_PERMIT. 305 * 306 * This register is reset on chip reset. 307 */ 308 union ody_cpc_permit { 309 uint32_t u; 310 struct ody_cpc_permit_s { 311 uint32_t permitdis : 5; 312 uint32_t reserved_5_30 : 26; 313 uint32_t lock : 1; 314 } s; 315 /* struct ody_cpc_permit_s cn; */ 316 }; 317 typedef union ody_cpc_permit ody_cpc_permit_t; 318 319 #define ODY_CPC_PERMIT ODY_CPC_PERMIT_FUNC() 320 static inline uint64_t ODY_CPC_PERMIT_FUNC(void) __attribute__ ((pure, always_inline)); 321 static inline uint64_t ODY_CPC_PERMIT_FUNC(void) 322 { 323 return 0x86d000000120ll; 324 } 325 326 #define typedef_ODY_CPC_PERMIT ody_cpc_permit_t 327 #define bustype_ODY_CPC_PERMIT CSR_TYPE_NCB32b 328 #define basename_ODY_CPC_PERMIT "CPC_PERMIT" 329 #define device_bar_ODY_CPC_PERMIT 0x0 /* PF_BAR0 */ 330 #define busnum_ODY_CPC_PERMIT 0 331 #define arguments_ODY_CPC_PERMIT -1, -1, -1, -1 332 333 /** 334 * Register (NCB) cpc_ram_mem# 335 * 336 * CPC RAM Memory Registers 337 * These registers access the CPC RAM memory space. The size of the RAM is discoverable 338 * with CPC_CONST[MEM_REGIONS]. 339 * 340 * This register is only accessible to the requestor(s) permitted with CPC_RAM_PERMIT(). 341 * 342 * This register is reset on chip reset. 343 */ 344 union ody_cpc_ram_memx { 345 uint64_t u; 346 struct ody_cpc_ram_memx_s { 347 uint64_t dat : 64; 348 } s; 349 /* struct ody_cpc_ram_memx_s cn; */ 350 }; 351 typedef union ody_cpc_ram_memx ody_cpc_ram_memx_t; 352 353 static inline uint64_t ODY_CPC_RAM_MEMX(uint64_t a) __attribute__ ((pure, always_inline)); 354 static inline uint64_t ODY_CPC_RAM_MEMX(uint64_t a) 355 { 356 if (a <= 524287) 357 return 0x86d000400000ll + 8ll * ((a) & 0x7ffff); 358 __ody_csr_fatal("CPC_RAM_MEMX", 1, a, 0, 0, 0, 0, 0); 359 } 360 361 #define typedef_ODY_CPC_RAM_MEMX(a) ody_cpc_ram_memx_t 362 #define bustype_ODY_CPC_RAM_MEMX(a) CSR_TYPE_NCB 363 #define basename_ODY_CPC_RAM_MEMX(a) "CPC_RAM_MEMX" 364 #define device_bar_ODY_CPC_RAM_MEMX(a) 0x0 /* PF_BAR0 */ 365 #define busnum_ODY_CPC_RAM_MEMX(a) (a) 366 #define arguments_ODY_CPC_RAM_MEMX(a) (a), -1, -1, -1 367 368 /** 369 * Register (NCB32b) cpc_ram_permit# 370 * 371 * CPC RAM Permit Registers 372 * These registers are used to control the RAM space access permissions of 373 * the SCP, MCP, CCP, EHSM and AP processors 374 * The RAM is split into 64 secure regions. 375 * 376 * This register is only accessible to the requestor(s) permitted with CPC_PERMIT. 377 * 378 * This register is reset on chip reset. 379 */ 380 union ody_cpc_ram_permitx { 381 uint32_t u; 382 struct ody_cpc_ram_permitx_s { 383 uint32_t rddis : 6; 384 uint32_t reserved_6_9 : 4; 385 uint32_t lock : 1; 386 uint32_t reserved_11_15 : 5; 387 uint32_t wrdis : 6; 388 uint32_t reserved_22_23 : 2; 389 uint32_t pci_dis : 4; 390 uint32_t exedis : 4; 391 } s; 392 /* struct ody_cpc_ram_permitx_s cn; */ 393 }; 394 typedef union ody_cpc_ram_permitx ody_cpc_ram_permitx_t; 395 396 static inline uint64_t ODY_CPC_RAM_PERMITX(uint64_t a) __attribute__ ((pure, always_inline)); 397 static inline uint64_t ODY_CPC_RAM_PERMITX(uint64_t a) 398 { 399 if (a <= 63) 400 return 0x86d000008000ll + 8ll * ((a) & 0x3f); 401 __ody_csr_fatal("CPC_RAM_PERMITX", 1, a, 0, 0, 0, 0, 0); 402 } 403 404 #define typedef_ODY_CPC_RAM_PERMITX(a) ody_cpc_ram_permitx_t 405 #define bustype_ODY_CPC_RAM_PERMITX(a) CSR_TYPE_NCB32b 406 #define basename_ODY_CPC_RAM_PERMITX(a) "CPC_RAM_PERMITX" 407 #define device_bar_ODY_CPC_RAM_PERMITX(a) 0x0 /* PF_BAR0 */ 408 #define busnum_ODY_CPC_RAM_PERMITX(a) (a) 409 #define arguments_ODY_CPC_RAM_PERMITX(a) (a), -1, -1, -1 410 411 /** 412 * Register (NCB) cpc_rom_mem# 413 * 414 * CPC ROM Memory Registers 415 * These registers access the CPC ROM memory space. 416 * 417 * This register is only accessible to the requestor(s) permitted with CPC_BOOT_ROM_LIMIT. 418 * 419 * This register is reset on chip reset. 420 */ 421 union ody_cpc_rom_memx { 422 uint64_t u; 423 struct ody_cpc_rom_memx_s { 424 uint64_t dat : 64; 425 } s; 426 /* struct ody_cpc_rom_memx_s cn; */ 427 }; 428 typedef union ody_cpc_rom_memx ody_cpc_rom_memx_t; 429 430 static inline uint64_t ODY_CPC_ROM_MEMX(uint64_t a) __attribute__ ((pure, always_inline)); 431 static inline uint64_t ODY_CPC_ROM_MEMX(uint64_t a) 432 { 433 if (a <= 8191) 434 return 0x86d000010000ll + 8ll * ((a) & 0x1fff); 435 __ody_csr_fatal("CPC_ROM_MEMX", 1, a, 0, 0, 0, 0, 0); 436 } 437 438 #define typedef_ODY_CPC_ROM_MEMX(a) ody_cpc_rom_memx_t 439 #define bustype_ODY_CPC_ROM_MEMX(a) CSR_TYPE_NCB 440 #define basename_ODY_CPC_ROM_MEMX(a) "CPC_ROM_MEMX" 441 #define device_bar_ODY_CPC_ROM_MEMX(a) 0x0 /* PF_BAR0 */ 442 #define busnum_ODY_CPC_ROM_MEMX(a) (a) 443 #define arguments_ODY_CPC_ROM_MEMX(a) (a), -1, -1, -1 444 445 /** 446 * Register (NCB32b) cpc_scp_boot_rom_limit 447 * 448 * CPC SCP Boot ROM Limit Register 449 * This register contains the address limit in the internal boot ROM that SCP can access. 450 * 451 * This register is only accessible to the requestor(s) permitted with CPC_PERMIT. 452 * 453 * This register is reset on chip reset and scp_reset. 454 */ 455 union ody_cpc_scp_boot_rom_limit { 456 uint32_t u; 457 struct ody_cpc_scp_boot_rom_limit_s { 458 uint32_t reserved_0_2 : 3; 459 uint32_t addr : 14; 460 uint32_t reserved_17_31 : 15; 461 } s; 462 /* struct ody_cpc_scp_boot_rom_limit_s cn; */ 463 }; 464 typedef union ody_cpc_scp_boot_rom_limit ody_cpc_scp_boot_rom_limit_t; 465 466 #define ODY_CPC_SCP_BOOT_ROM_LIMIT ODY_CPC_SCP_BOOT_ROM_LIMIT_FUNC() 467 static inline uint64_t ODY_CPC_SCP_BOOT_ROM_LIMIT_FUNC(void) __attribute__ ((pure, always_inline)); 468 static inline uint64_t ODY_CPC_SCP_BOOT_ROM_LIMIT_FUNC(void) 469 { 470 return 0x86d000000150ll; 471 } 472 473 #define typedef_ODY_CPC_SCP_BOOT_ROM_LIMIT ody_cpc_scp_boot_rom_limit_t 474 #define bustype_ODY_CPC_SCP_BOOT_ROM_LIMIT CSR_TYPE_NCB32b 475 #define basename_ODY_CPC_SCP_BOOT_ROM_LIMIT "CPC_SCP_BOOT_ROM_LIMIT" 476 #define device_bar_ODY_CPC_SCP_BOOT_ROM_LIMIT 0x0 /* PF_BAR0 */ 477 #define busnum_ODY_CPC_SCP_BOOT_ROM_LIMIT 0 478 #define arguments_ODY_CPC_SCP_BOOT_ROM_LIMIT -1, -1, -1, -1 479 480 /** 481 * Register (NCB) cpc_timer100 482 * 483 * CPC Timer 100 MHz Register 484 * This register contains the common 100 MHz timer register for the XCP cores. 485 * 486 * This register is only accessible to the requestor(s) permitted with CPC_PERMIT. 487 * This register is writable for diagnostic use only. 488 * 489 * This register is reset on chip reset. 490 */ 491 union ody_cpc_timer100 { 492 uint64_t u; 493 struct ody_cpc_timer100_s { 494 uint64_t tmr : 64; 495 } s; 496 /* struct ody_cpc_timer100_s cn; */ 497 }; 498 typedef union ody_cpc_timer100 ody_cpc_timer100_t; 499 500 #define ODY_CPC_TIMER100 ODY_CPC_TIMER100_FUNC() 501 static inline uint64_t ODY_CPC_TIMER100_FUNC(void) __attribute__ ((pure, always_inline)); 502 static inline uint64_t ODY_CPC_TIMER100_FUNC(void) 503 { 504 return 0x86d000000110ll; 505 } 506 507 #define typedef_ODY_CPC_TIMER100 ody_cpc_timer100_t 508 #define bustype_ODY_CPC_TIMER100 CSR_TYPE_NCB 509 #define basename_ODY_CPC_TIMER100 "CPC_TIMER100" 510 #define device_bar_ODY_CPC_TIMER100 0x0 /* PF_BAR0 */ 511 #define busnum_ODY_CPC_TIMER100 0 512 #define arguments_ODY_CPC_TIMER100 -1, -1, -1, -1 513 514 /** 515 * Register (NCB32b) cpc_xcp#_gib#_lint_permit 516 * 517 * CPC Register GIB Lint Permit Registers 518 * These registers are used to control the XCP GIB LINT W1S/W1C register permissions. 519 * 520 * This register is only accessible to the requestor(s) permitted with CPC_PERMIT. 521 * 522 * This register is reset on chip reset. 523 */ 524 union ody_cpc_xcpx_gibx_lint_permit { 525 uint32_t u; 526 struct ody_cpc_xcpx_gibx_lint_permit_s { 527 uint32_t permitdis : 5; 528 uint32_t reserved_5_23 : 19; 529 uint32_t pci_dis : 4; 530 uint32_t reserved_28_30 : 3; 531 uint32_t lock : 1; 532 } s; 533 /* struct ody_cpc_xcpx_gibx_lint_permit_s cn; */ 534 }; 535 typedef union ody_cpc_xcpx_gibx_lint_permit ody_cpc_xcpx_gibx_lint_permit_t; 536 537 static inline uint64_t ODY_CPC_XCPX_GIBX_LINT_PERMIT(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 538 static inline uint64_t ODY_CPC_XCPX_GIBX_LINT_PERMIT(uint64_t a, uint64_t b) 539 { 540 if ((a <= 2) && (b <= 2)) 541 return 0x86d000000200ll + 0x20ll * ((a) & 0x3) + 8ll * ((b) & 0x3); 542 __ody_csr_fatal("CPC_XCPX_GIBX_LINT_PERMIT", 2, a, b, 0, 0, 0, 0); 543 } 544 545 #define typedef_ODY_CPC_XCPX_GIBX_LINT_PERMIT(a, b) ody_cpc_xcpx_gibx_lint_permit_t 546 #define bustype_ODY_CPC_XCPX_GIBX_LINT_PERMIT(a, b) CSR_TYPE_NCB32b 547 #define basename_ODY_CPC_XCPX_GIBX_LINT_PERMIT(a, b) "CPC_XCPX_GIBX_LINT_PERMIT" 548 #define device_bar_ODY_CPC_XCPX_GIBX_LINT_PERMIT(a, b) 0x0 /* PF_BAR0 */ 549 #define busnum_ODY_CPC_XCPX_GIBX_LINT_PERMIT(a, b) (a) 550 #define arguments_ODY_CPC_XCPX_GIBX_LINT_PERMIT(a, b) (a), (b), -1, -1 551 552 /** 553 * Register (NCB32b) cpc_xcp#_permit 554 * 555 * CPC Register Permit Registers 556 * These registers are used to control the XCP register permissions. 557 * 558 * This register is only accessible to the requestor(s) permitted with CPC_PERMIT. 559 * 560 * This register is reset on chip reset. 561 */ 562 union ody_cpc_xcpx_permit { 563 uint32_t u; 564 struct ody_cpc_xcpx_permit_s { 565 uint32_t permitdis : 5; 566 uint32_t reserved_5_30 : 26; 567 uint32_t lock : 1; 568 } s; 569 /* struct ody_cpc_xcpx_permit_s cn; */ 570 }; 571 typedef union ody_cpc_xcpx_permit ody_cpc_xcpx_permit_t; 572 573 static inline uint64_t ODY_CPC_XCPX_PERMIT(uint64_t a) __attribute__ ((pure, always_inline)); 574 static inline uint64_t ODY_CPC_XCPX_PERMIT(uint64_t a) 575 { 576 if (a <= 2) 577 return 0x86d0000001a0ll + 8ll * ((a) & 0x3); 578 __ody_csr_fatal("CPC_XCPX_PERMIT", 1, a, 0, 0, 0, 0, 0); 579 } 580 581 #define typedef_ODY_CPC_XCPX_PERMIT(a) ody_cpc_xcpx_permit_t 582 #define bustype_ODY_CPC_XCPX_PERMIT(a) CSR_TYPE_NCB32b 583 #define basename_ODY_CPC_XCPX_PERMIT(a) "CPC_XCPX_PERMIT" 584 #define device_bar_ODY_CPC_XCPX_PERMIT(a) 0x0 /* PF_BAR0 */ 585 #define busnum_ODY_CPC_XCPX_PERMIT(a) (a) 586 #define arguments_ODY_CPC_XCPX_PERMIT(a) (a), -1, -1, -1 587 588 #endif /* __ODY_CSRS_CPC_H__ */ 589