1 #ifndef __ODY_CSRS_APA_H__ 2 #define __ODY_CSRS_APA_H__ 3 /* This file is auto-generated. Do not edit */ 4 5 /***********************license start*********************************** 6 * Copyright (C) 2021-2026 Marvell. 7 * SPDX-License-Identifier: BSD-3-Clause 8 * https://spdx.org/licenses 9 ***********************license end**************************************/ 10 11 12 /** 13 * @file 14 * 15 * Configuration and status register (CSR) address and type definitions for 16 * APA. 17 * 18 * This file is auto generated. Do not edit. 19 * 20 */ 21 22 /** 23 * Enumeration apa_bar_e 24 * 25 * APA Base Address Register Enumeration 26 * Enumerates the base address registers. 27 */ 28 #define ODY_APA_BAR_E_APAX_PF_BAR0(a) (0x87e349000000ll + 0x1000000ll * (a)) 29 #define ODY_APA_BAR_E_APAX_PF_BAR0_SIZE 0x100000ull 30 #define ODY_APA_BAR_E_APAX_PF_BAR4(a) (0x87e349100000ll + 0x1000000ll * (a)) 31 #define ODY_APA_BAR_E_APAX_PF_BAR4_SIZE 0x100000ull 32 33 /** 34 * Enumeration apa_int_vec_e 35 * 36 * APA MSI-X Vector Enumeration 37 * Enumerates the MSI-X interrupt vectors. 38 */ 39 #define ODY_APA_INT_VEC_E_APA_APAT_INT (5) 40 #define ODY_APA_INT_VEC_E_APA_CLUSTER_PPU_INT_CLEAR (1) 41 #define ODY_APA_INT_VEC_E_APA_CLUSTER_PPU_INT_SET (0) 42 #define ODY_APA_INT_VEC_E_APA_CORE_ECC_INT (7) 43 #define ODY_APA_INT_VEC_E_APA_CORE_PPU_INT_CLEAR (3) 44 #define ODY_APA_INT_VEC_E_APA_CORE_PPU_INT_SET (2) 45 #define ODY_APA_INT_VEC_E_APA_ECC_INT (6) 46 #define ODY_APA_INT_VEC_E_APA_WDOG_INT (4) 47 48 /** 49 * Enumeration apa_pll_sel_e 50 * 51 * APA PLL Selection Enumeration 52 * Enumerates the values of APA_PLL[NEXT_PLL_SEL] and APA_PLL[CUR_PLL_SEL]. 53 */ 54 #define ODY_APA_PLL_SEL_E_ARO (6) 55 #define ODY_APA_PLL_SEL_E_BYPASS (2) 56 #define ODY_APA_PLL_SEL_E_OFF (3) 57 #define ODY_APA_PLL_SEL_E_PLL0 (4) 58 #define ODY_APA_PLL_SEL_E_PLL1 (5) 59 #define ODY_APA_PLL_SEL_E_REFCLK (1) 60 #define ODY_APA_PLL_SEL_E_RSVD (7) 61 #define ODY_APA_PLL_SEL_E_RUNT (0) 62 63 /** 64 * Register (RSL) apa#_apat_int_ena_w1c 65 * 66 * APA APAT Interrupt Enable Clear Registers 67 * This register clears interrupt enable bits. 68 */ 69 union ody_apax_apat_int_ena_w1c { 70 uint64_t u; 71 struct ody_apax_apat_int_ena_w1c_s { 72 uint64_t apat : 1; 73 uint64_t reserved_1_63 : 63; 74 } s; 75 /* struct ody_apax_apat_int_ena_w1c_s cn; */ 76 }; 77 typedef union ody_apax_apat_int_ena_w1c ody_apax_apat_int_ena_w1c_t; 78 79 static inline uint64_t ODY_APAX_APAT_INT_ENA_W1C(uint64_t a) __attribute__ ((pure, always_inline)); 80 static inline uint64_t ODY_APAX_APAT_INT_ENA_W1C(uint64_t a) 81 { 82 if (a <= 89) 83 return 0x87e349001e10ll + 0x1000000ll * ((a) & 0x7f); 84 __ody_csr_fatal("APAX_APAT_INT_ENA_W1C", 1, a, 0, 0, 0, 0, 0); 85 } 86 87 #define typedef_ODY_APAX_APAT_INT_ENA_W1C(a) ody_apax_apat_int_ena_w1c_t 88 #define bustype_ODY_APAX_APAT_INT_ENA_W1C(a) CSR_TYPE_RSL 89 #define basename_ODY_APAX_APAT_INT_ENA_W1C(a) "APAX_APAT_INT_ENA_W1C" 90 #define device_bar_ODY_APAX_APAT_INT_ENA_W1C(a) 0x0 /* PF_BAR0 */ 91 #define busnum_ODY_APAX_APAT_INT_ENA_W1C(a) (a) 92 #define arguments_ODY_APAX_APAT_INT_ENA_W1C(a) (a), -1, -1, -1 93 94 /** 95 * Register (RSL) apa#_apat_int_ena_w1s 96 * 97 * APA APAT Interrupt Enable Set Registers 98 * This register sets interrupt enable bits. 99 */ 100 union ody_apax_apat_int_ena_w1s { 101 uint64_t u; 102 struct ody_apax_apat_int_ena_w1s_s { 103 uint64_t apat : 1; 104 uint64_t reserved_1_63 : 63; 105 } s; 106 /* struct ody_apax_apat_int_ena_w1s_s cn; */ 107 }; 108 typedef union ody_apax_apat_int_ena_w1s ody_apax_apat_int_ena_w1s_t; 109 110 static inline uint64_t ODY_APAX_APAT_INT_ENA_W1S(uint64_t a) __attribute__ ((pure, always_inline)); 111 static inline uint64_t ODY_APAX_APAT_INT_ENA_W1S(uint64_t a) 112 { 113 if (a <= 89) 114 return 0x87e349001e18ll + 0x1000000ll * ((a) & 0x7f); 115 __ody_csr_fatal("APAX_APAT_INT_ENA_W1S", 1, a, 0, 0, 0, 0, 0); 116 } 117 118 #define typedef_ODY_APAX_APAT_INT_ENA_W1S(a) ody_apax_apat_int_ena_w1s_t 119 #define bustype_ODY_APAX_APAT_INT_ENA_W1S(a) CSR_TYPE_RSL 120 #define basename_ODY_APAX_APAT_INT_ENA_W1S(a) "APAX_APAT_INT_ENA_W1S" 121 #define device_bar_ODY_APAX_APAT_INT_ENA_W1S(a) 0x0 /* PF_BAR0 */ 122 #define busnum_ODY_APAX_APAT_INT_ENA_W1S(a) (a) 123 #define arguments_ODY_APAX_APAT_INT_ENA_W1S(a) (a), -1, -1, -1 124 125 /** 126 * Register (RSL) apa#_apat_int_w1c 127 * 128 * APA APAT Interrupt Register 129 * This register is reports interrupt status. 130 */ 131 union ody_apax_apat_int_w1c { 132 uint64_t u; 133 struct ody_apax_apat_int_w1c_s { 134 uint64_t apat : 1; 135 uint64_t reserved_1_63 : 63; 136 } s; 137 /* struct ody_apax_apat_int_w1c_s cn; */ 138 }; 139 typedef union ody_apax_apat_int_w1c ody_apax_apat_int_w1c_t; 140 141 static inline uint64_t ODY_APAX_APAT_INT_W1C(uint64_t a) __attribute__ ((pure, always_inline)); 142 static inline uint64_t ODY_APAX_APAT_INT_W1C(uint64_t a) 143 { 144 if (a <= 89) 145 return 0x87e349001e00ll + 0x1000000ll * ((a) & 0x7f); 146 __ody_csr_fatal("APAX_APAT_INT_W1C", 1, a, 0, 0, 0, 0, 0); 147 } 148 149 #define typedef_ODY_APAX_APAT_INT_W1C(a) ody_apax_apat_int_w1c_t 150 #define bustype_ODY_APAX_APAT_INT_W1C(a) CSR_TYPE_RSL 151 #define basename_ODY_APAX_APAT_INT_W1C(a) "APAX_APAT_INT_W1C" 152 #define device_bar_ODY_APAX_APAT_INT_W1C(a) 0x0 /* PF_BAR0 */ 153 #define busnum_ODY_APAX_APAT_INT_W1C(a) (a) 154 #define arguments_ODY_APAX_APAT_INT_W1C(a) (a), -1, -1, -1 155 156 /** 157 * Register (RSL) apa#_apat_int_w1s 158 * 159 * APA APAT Interrupt Set Registers 160 * This register sets interrupt bits. 161 */ 162 union ody_apax_apat_int_w1s { 163 uint64_t u; 164 struct ody_apax_apat_int_w1s_s { 165 uint64_t apat : 1; 166 uint64_t reserved_1_63 : 63; 167 } s; 168 /* struct ody_apax_apat_int_w1s_s cn; */ 169 }; 170 typedef union ody_apax_apat_int_w1s ody_apax_apat_int_w1s_t; 171 172 static inline uint64_t ODY_APAX_APAT_INT_W1S(uint64_t a) __attribute__ ((pure, always_inline)); 173 static inline uint64_t ODY_APAX_APAT_INT_W1S(uint64_t a) 174 { 175 if (a <= 89) 176 return 0x87e349001e08ll + 0x1000000ll * ((a) & 0x7f); 177 __ody_csr_fatal("APAX_APAT_INT_W1S", 1, a, 0, 0, 0, 0, 0); 178 } 179 180 #define typedef_ODY_APAX_APAT_INT_W1S(a) ody_apax_apat_int_w1s_t 181 #define bustype_ODY_APAX_APAT_INT_W1S(a) CSR_TYPE_RSL 182 #define basename_ODY_APAX_APAT_INT_W1S(a) "APAX_APAT_INT_W1S" 183 #define device_bar_ODY_APAX_APAT_INT_W1S(a) 0x0 /* PF_BAR0 */ 184 #define busnum_ODY_APAX_APAT_INT_W1S(a) (a) 185 #define arguments_ODY_APAX_APAT_INT_W1S(a) (a), -1, -1, -1 186 187 /** 188 * Register (RSL) apa#_apat_rdat# 189 * 190 * APA APAT Read Data Register 191 */ 192 union ody_apax_apat_rdatx { 193 uint64_t u; 194 struct ody_apax_apat_rdatx_s { 195 uint64_t dat : 64; 196 } s; 197 /* struct ody_apax_apat_rdatx_s cn; */ 198 }; 199 typedef union ody_apax_apat_rdatx ody_apax_apat_rdatx_t; 200 201 static inline uint64_t ODY_APAX_APAT_RDATX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 202 static inline uint64_t ODY_APAX_APAT_RDATX(uint64_t a, uint64_t b) 203 { 204 if ((a <= 89) && (b <= 3)) 205 return 0x87e349001240ll + 0x1000000ll * ((a) & 0x7f) + 8ll * ((b) & 0x3); 206 __ody_csr_fatal("APAX_APAT_RDATX", 2, a, b, 0, 0, 0, 0); 207 } 208 209 #define typedef_ODY_APAX_APAT_RDATX(a, b) ody_apax_apat_rdatx_t 210 #define bustype_ODY_APAX_APAT_RDATX(a, b) CSR_TYPE_RSL 211 #define basename_ODY_APAX_APAT_RDATX(a, b) "APAX_APAT_RDATX" 212 #define device_bar_ODY_APAX_APAT_RDATX(a, b) 0x0 /* PF_BAR0 */ 213 #define busnum_ODY_APAX_APAT_RDATX(a, b) (a) 214 #define arguments_ODY_APAX_APAT_RDATX(a, b) (a), (b), -1, -1 215 216 /** 217 * Register (RSL) apa#_apat_req 218 * 219 * APA APAT Request Register 220 * This register records information about an APAT trapped request. See CHI-D 221 * specifications for more information. 222 */ 223 union ody_apax_apat_req { 224 uint64_t u; 225 struct ody_apax_apat_req_s { 226 uint64_t txnid : 12; 227 uint64_t size : 3; 228 uint64_t tracetag : 1; 229 uint64_t opcode : 7; 230 uint64_t endian : 1; 231 uint64_t device : 1; 232 uint64_t reserved_25_55 : 31; 233 uint64_t index : 5; 234 uint64_t reserved_61 : 1; 235 uint64_t has_apat_ext : 1; 236 uint64_t valid : 1; 237 } s; 238 /* struct ody_apax_apat_req_s cn; */ 239 }; 240 typedef union ody_apax_apat_req ody_apax_apat_req_t; 241 242 static inline uint64_t ODY_APAX_APAT_REQ(uint64_t a) __attribute__ ((pure, always_inline)); 243 static inline uint64_t ODY_APAX_APAT_REQ(uint64_t a) 244 { 245 if (a <= 89) 246 return 0x87e349001200ll + 0x1000000ll * ((a) & 0x7f); 247 __ody_csr_fatal("APAX_APAT_REQ", 1, a, 0, 0, 0, 0, 0); 248 } 249 250 #define typedef_ODY_APAX_APAT_REQ(a) ody_apax_apat_req_t 251 #define bustype_ODY_APAX_APAT_REQ(a) CSR_TYPE_RSL 252 #define basename_ODY_APAX_APAT_REQ(a) "APAX_APAT_REQ" 253 #define device_bar_ODY_APAX_APAT_REQ(a) 0x0 /* PF_BAR0 */ 254 #define busnum_ODY_APAX_APAT_REQ(a) (a) 255 #define arguments_ODY_APAX_APAT_REQ(a) (a), -1, -1, -1 256 257 /** 258 * Register (RSL) apa#_apat_req_addr 259 * 260 * APA APAT Request Address Register 261 * This register records the physical address of the trapped request. 262 */ 263 union ody_apax_apat_req_addr { 264 uint64_t u; 265 struct ody_apax_apat_req_addr_s { 266 uint64_t addr : 48; 267 uint64_t reserved_48_61 : 14; 268 uint64_t ns : 1; 269 uint64_t reserved_63 : 1; 270 } s; 271 /* struct ody_apax_apat_req_addr_s cn; */ 272 }; 273 typedef union ody_apax_apat_req_addr ody_apax_apat_req_addr_t; 274 275 static inline uint64_t ODY_APAX_APAT_REQ_ADDR(uint64_t a) __attribute__ ((pure, always_inline)); 276 static inline uint64_t ODY_APAX_APAT_REQ_ADDR(uint64_t a) 277 { 278 if (a <= 89) 279 return 0x87e349001208ll + 0x1000000ll * ((a) & 0x7f); 280 __ody_csr_fatal("APAX_APAT_REQ_ADDR", 1, a, 0, 0, 0, 0, 0); 281 } 282 283 #define typedef_ODY_APAX_APAT_REQ_ADDR(a) ody_apax_apat_req_addr_t 284 #define bustype_ODY_APAX_APAT_REQ_ADDR(a) CSR_TYPE_RSL 285 #define basename_ODY_APAX_APAT_REQ_ADDR(a) "APAX_APAT_REQ_ADDR" 286 #define device_bar_ODY_APAX_APAT_REQ_ADDR(a) 0x0 /* PF_BAR0 */ 287 #define busnum_ODY_APAX_APAT_REQ_ADDR(a) (a) 288 #define arguments_ODY_APAX_APAT_REQ_ADDR(a) (a), -1, -1, -1 289 290 /** 291 * Register (RSL) apa#_apat_rsp 292 * 293 * APA APAT Response Register 294 */ 295 union ody_apax_apat_rsp { 296 uint64_t u; 297 struct ody_apax_apat_rsp_s { 298 uint64_t resperr : 2; 299 uint64_t reserved_2_63 : 62; 300 } s; 301 /* struct ody_apax_apat_rsp_s cn; */ 302 }; 303 typedef union ody_apax_apat_rsp ody_apax_apat_rsp_t; 304 305 static inline uint64_t ODY_APAX_APAT_RSP(uint64_t a) __attribute__ ((pure, always_inline)); 306 static inline uint64_t ODY_APAX_APAT_RSP(uint64_t a) 307 { 308 if (a <= 89) 309 return 0x87e349001210ll + 0x1000000ll * ((a) & 0x7f); 310 __ody_csr_fatal("APAX_APAT_RSP", 1, a, 0, 0, 0, 0, 0); 311 } 312 313 #define typedef_ODY_APAX_APAT_RSP(a) ody_apax_apat_rsp_t 314 #define bustype_ODY_APAX_APAT_RSP(a) CSR_TYPE_RSL 315 #define basename_ODY_APAX_APAT_RSP(a) "APAX_APAT_RSP" 316 #define device_bar_ODY_APAX_APAT_RSP(a) 0x0 /* PF_BAR0 */ 317 #define busnum_ODY_APAX_APAT_RSP(a) (a) 318 #define arguments_ODY_APAX_APAT_RSP(a) (a), -1, -1, -1 319 320 /** 321 * Register (RSL) apa#_apat_vec#_addr 322 * 323 * APA APAT Vector Address Register 324 * This register configures the address trapper. 325 */ 326 union ody_apax_apat_vecx_addr { 327 uint64_t u; 328 struct ody_apax_apat_vecx_addr_s { 329 uint64_t addr : 48; 330 uint64_t reserved_48_61 : 14; 331 uint64_t ns : 1; 332 uint64_t valid : 1; 333 } s; 334 /* struct ody_apax_apat_vecx_addr_s cn; */ 335 }; 336 typedef union ody_apax_apat_vecx_addr ody_apax_apat_vecx_addr_t; 337 338 static inline uint64_t ODY_APAX_APAT_VECX_ADDR(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 339 static inline uint64_t ODY_APAX_APAT_VECX_ADDR(uint64_t a, uint64_t b) 340 { 341 if ((a <= 89) && (b <= 31)) 342 return 0x87e349001000ll + 0x1000000ll * ((a) & 0x7f) + 0x10ll * ((b) & 0x1f); 343 __ody_csr_fatal("APAX_APAT_VECX_ADDR", 2, a, b, 0, 0, 0, 0); 344 } 345 346 #define typedef_ODY_APAX_APAT_VECX_ADDR(a, b) ody_apax_apat_vecx_addr_t 347 #define bustype_ODY_APAX_APAT_VECX_ADDR(a, b) CSR_TYPE_RSL 348 #define basename_ODY_APAX_APAT_VECX_ADDR(a, b) "APAX_APAT_VECX_ADDR" 349 #define device_bar_ODY_APAX_APAT_VECX_ADDR(a, b) 0x0 /* PF_BAR0 */ 350 #define busnum_ODY_APAX_APAT_VECX_ADDR(a, b) (a) 351 #define arguments_ODY_APAX_APAT_VECX_ADDR(a, b) (a), (b), -1, -1 352 353 /** 354 * Register (RSL) apa#_apat_vec#_mask 355 * 356 * APA APAT_VEC_MASK Register 357 * Mask bits. 1 means corresponding NS/ADDR bits must match in the request. 358 */ 359 union ody_apax_apat_vecx_mask { 360 uint64_t u; 361 struct ody_apax_apat_vecx_mask_s { 362 uint64_t addr : 48; 363 uint64_t reserved_48_61 : 14; 364 uint64_t ns : 1; 365 uint64_t reserved_63 : 1; 366 } s; 367 /* struct ody_apax_apat_vecx_mask_s cn; */ 368 }; 369 typedef union ody_apax_apat_vecx_mask ody_apax_apat_vecx_mask_t; 370 371 static inline uint64_t ODY_APAX_APAT_VECX_MASK(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 372 static inline uint64_t ODY_APAX_APAT_VECX_MASK(uint64_t a, uint64_t b) 373 { 374 if ((a <= 89) && (b <= 31)) 375 return 0x87e349001008ll + 0x1000000ll * ((a) & 0x7f) + 0x10ll * ((b) & 0x1f); 376 __ody_csr_fatal("APAX_APAT_VECX_MASK", 2, a, b, 0, 0, 0, 0); 377 } 378 379 #define typedef_ODY_APAX_APAT_VECX_MASK(a, b) ody_apax_apat_vecx_mask_t 380 #define bustype_ODY_APAX_APAT_VECX_MASK(a, b) CSR_TYPE_RSL 381 #define basename_ODY_APAX_APAT_VECX_MASK(a, b) "APAX_APAT_VECX_MASK" 382 #define device_bar_ODY_APAX_APAT_VECX_MASK(a, b) 0x0 /* PF_BAR0 */ 383 #define busnum_ODY_APAX_APAT_VECX_MASK(a, b) (a) 384 #define arguments_ODY_APAX_APAT_VECX_MASK(a, b) (a), (b), -1, -1 385 386 /** 387 * Register (RSL) apa#_apat_wdat# 388 * 389 * APA APAT Write Data Register 390 */ 391 union ody_apax_apat_wdatx { 392 uint64_t u; 393 struct ody_apax_apat_wdatx_s { 394 uint64_t dat : 64; 395 } s; 396 /* struct ody_apax_apat_wdatx_s cn; */ 397 }; 398 typedef union ody_apax_apat_wdatx ody_apax_apat_wdatx_t; 399 400 static inline uint64_t ODY_APAX_APAT_WDATX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 401 static inline uint64_t ODY_APAX_APAT_WDATX(uint64_t a, uint64_t b) 402 { 403 if ((a <= 89) && (b <= 3)) 404 return 0x87e349001220ll + 0x1000000ll * ((a) & 0x7f) + 8ll * ((b) & 0x3); 405 __ody_csr_fatal("APAX_APAT_WDATX", 2, a, b, 0, 0, 0, 0); 406 } 407 408 #define typedef_ODY_APAX_APAT_WDATX(a, b) ody_apax_apat_wdatx_t 409 #define bustype_ODY_APAX_APAT_WDATX(a, b) CSR_TYPE_RSL 410 #define basename_ODY_APAX_APAT_WDATX(a, b) "APAX_APAT_WDATX" 411 #define device_bar_ODY_APAX_APAT_WDATX(a, b) 0x0 /* PF_BAR0 */ 412 #define busnum_ODY_APAX_APAT_WDATX(a, b) (a) 413 #define arguments_ODY_APAX_APAT_WDATX(a, b) (a), (b), -1, -1 414 415 /** 416 * Register (RSL) apa#_apat_wdat_be 417 * 418 * APA APAT Write Data Byte Enable Register 419 */ 420 union ody_apax_apat_wdat_be { 421 uint64_t u; 422 struct ody_apax_apat_wdat_be_s { 423 uint64_t byte_en : 32; 424 uint64_t reserved_32_63 : 32; 425 } s; 426 /* struct ody_apax_apat_wdat_be_s cn; */ 427 }; 428 typedef union ody_apax_apat_wdat_be ody_apax_apat_wdat_be_t; 429 430 static inline uint64_t ODY_APAX_APAT_WDAT_BE(uint64_t a) __attribute__ ((pure, always_inline)); 431 static inline uint64_t ODY_APAX_APAT_WDAT_BE(uint64_t a) 432 { 433 if (a <= 89) 434 return 0x87e349001218ll + 0x1000000ll * ((a) & 0x7f); 435 __ody_csr_fatal("APAX_APAT_WDAT_BE", 1, a, 0, 0, 0, 0, 0); 436 } 437 438 #define typedef_ODY_APAX_APAT_WDAT_BE(a) ody_apax_apat_wdat_be_t 439 #define bustype_ODY_APAX_APAT_WDAT_BE(a) CSR_TYPE_RSL 440 #define basename_ODY_APAX_APAT_WDAT_BE(a) "APAX_APAT_WDAT_BE" 441 #define device_bar_ODY_APAX_APAT_WDAT_BE(a) 0x0 /* PF_BAR0 */ 442 #define busnum_ODY_APAX_APAT_WDAT_BE(a) (a) 443 #define arguments_ODY_APAX_APAT_WDAT_BE(a) (a), -1, -1, -1 444 445 /** 446 * Register (RSL) apa#_core_ecc_int_ena_w1c 447 * 448 * APA Core ECC Interrupt Enable Clear Registers 449 * This register clears interrupt enable bits. 450 */ 451 union ody_apax_core_ecc_int_ena_w1c { 452 uint64_t u; 453 struct ody_apax_core_ecc_int_ena_w1c_s { 454 uint64_t core_err : 1; 455 uint64_t core_fault : 1; 456 uint64_t reserved_2_63 : 62; 457 } s; 458 /* struct ody_apax_core_ecc_int_ena_w1c_s cn; */ 459 }; 460 typedef union ody_apax_core_ecc_int_ena_w1c ody_apax_core_ecc_int_ena_w1c_t; 461 462 static inline uint64_t ODY_APAX_CORE_ECC_INT_ENA_W1C(uint64_t a) __attribute__ ((pure, always_inline)); 463 static inline uint64_t ODY_APAX_CORE_ECC_INT_ENA_W1C(uint64_t a) 464 { 465 if (a <= 89) 466 return 0x87e349001e70ll + 0x1000000ll * ((a) & 0x7f); 467 __ody_csr_fatal("APAX_CORE_ECC_INT_ENA_W1C", 1, a, 0, 0, 0, 0, 0); 468 } 469 470 #define typedef_ODY_APAX_CORE_ECC_INT_ENA_W1C(a) ody_apax_core_ecc_int_ena_w1c_t 471 #define bustype_ODY_APAX_CORE_ECC_INT_ENA_W1C(a) CSR_TYPE_RSL 472 #define basename_ODY_APAX_CORE_ECC_INT_ENA_W1C(a) "APAX_CORE_ECC_INT_ENA_W1C" 473 #define device_bar_ODY_APAX_CORE_ECC_INT_ENA_W1C(a) 0x0 /* PF_BAR0 */ 474 #define busnum_ODY_APAX_CORE_ECC_INT_ENA_W1C(a) (a) 475 #define arguments_ODY_APAX_CORE_ECC_INT_ENA_W1C(a) (a), -1, -1, -1 476 477 /** 478 * Register (RSL) apa#_core_ecc_int_ena_w1s 479 * 480 * APA Core ECC Interrupt Enable Set Registers 481 * This register sets interrupt enable bits. 482 */ 483 union ody_apax_core_ecc_int_ena_w1s { 484 uint64_t u; 485 struct ody_apax_core_ecc_int_ena_w1s_s { 486 uint64_t core_err : 1; 487 uint64_t core_fault : 1; 488 uint64_t reserved_2_63 : 62; 489 } s; 490 /* struct ody_apax_core_ecc_int_ena_w1s_s cn; */ 491 }; 492 typedef union ody_apax_core_ecc_int_ena_w1s ody_apax_core_ecc_int_ena_w1s_t; 493 494 static inline uint64_t ODY_APAX_CORE_ECC_INT_ENA_W1S(uint64_t a) __attribute__ ((pure, always_inline)); 495 static inline uint64_t ODY_APAX_CORE_ECC_INT_ENA_W1S(uint64_t a) 496 { 497 if (a <= 89) 498 return 0x87e349001e78ll + 0x1000000ll * ((a) & 0x7f); 499 __ody_csr_fatal("APAX_CORE_ECC_INT_ENA_W1S", 1, a, 0, 0, 0, 0, 0); 500 } 501 502 #define typedef_ODY_APAX_CORE_ECC_INT_ENA_W1S(a) ody_apax_core_ecc_int_ena_w1s_t 503 #define bustype_ODY_APAX_CORE_ECC_INT_ENA_W1S(a) CSR_TYPE_RSL 504 #define basename_ODY_APAX_CORE_ECC_INT_ENA_W1S(a) "APAX_CORE_ECC_INT_ENA_W1S" 505 #define device_bar_ODY_APAX_CORE_ECC_INT_ENA_W1S(a) 0x0 /* PF_BAR0 */ 506 #define busnum_ODY_APAX_CORE_ECC_INT_ENA_W1S(a) (a) 507 #define arguments_ODY_APAX_CORE_ECC_INT_ENA_W1S(a) (a), -1, -1, -1 508 509 /** 510 * Register (RSL) apa#_core_ecc_int_w1c 511 * 512 * APA Core ECC Interrupt Register 513 * This register reports interrupt status for the Cluster/Core ECC. 514 */ 515 union ody_apax_core_ecc_int_w1c { 516 uint64_t u; 517 struct ody_apax_core_ecc_int_w1c_s { 518 uint64_t core_err : 1; 519 uint64_t core_fault : 1; 520 uint64_t reserved_2_63 : 62; 521 } s; 522 /* struct ody_apax_core_ecc_int_w1c_s cn; */ 523 }; 524 typedef union ody_apax_core_ecc_int_w1c ody_apax_core_ecc_int_w1c_t; 525 526 static inline uint64_t ODY_APAX_CORE_ECC_INT_W1C(uint64_t a) __attribute__ ((pure, always_inline)); 527 static inline uint64_t ODY_APAX_CORE_ECC_INT_W1C(uint64_t a) 528 { 529 if (a <= 89) 530 return 0x87e349001e60ll + 0x1000000ll * ((a) & 0x7f); 531 __ody_csr_fatal("APAX_CORE_ECC_INT_W1C", 1, a, 0, 0, 0, 0, 0); 532 } 533 534 #define typedef_ODY_APAX_CORE_ECC_INT_W1C(a) ody_apax_core_ecc_int_w1c_t 535 #define bustype_ODY_APAX_CORE_ECC_INT_W1C(a) CSR_TYPE_RSL 536 #define basename_ODY_APAX_CORE_ECC_INT_W1C(a) "APAX_CORE_ECC_INT_W1C" 537 #define device_bar_ODY_APAX_CORE_ECC_INT_W1C(a) 0x0 /* PF_BAR0 */ 538 #define busnum_ODY_APAX_CORE_ECC_INT_W1C(a) (a) 539 #define arguments_ODY_APAX_CORE_ECC_INT_W1C(a) (a), -1, -1, -1 540 541 /** 542 * Register (RSL) apa#_core_ecc_int_w1s 543 * 544 * APA Core ECC Interrupt Set Registers 545 * This register sets interrupt bits. 546 */ 547 union ody_apax_core_ecc_int_w1s { 548 uint64_t u; 549 struct ody_apax_core_ecc_int_w1s_s { 550 uint64_t core_err : 1; 551 uint64_t core_fault : 1; 552 uint64_t reserved_2_63 : 62; 553 } s; 554 /* struct ody_apax_core_ecc_int_w1s_s cn; */ 555 }; 556 typedef union ody_apax_core_ecc_int_w1s ody_apax_core_ecc_int_w1s_t; 557 558 static inline uint64_t ODY_APAX_CORE_ECC_INT_W1S(uint64_t a) __attribute__ ((pure, always_inline)); 559 static inline uint64_t ODY_APAX_CORE_ECC_INT_W1S(uint64_t a) 560 { 561 if (a <= 89) 562 return 0x87e349001e68ll + 0x1000000ll * ((a) & 0x7f); 563 __ody_csr_fatal("APAX_CORE_ECC_INT_W1S", 1, a, 0, 0, 0, 0, 0); 564 } 565 566 #define typedef_ODY_APAX_CORE_ECC_INT_W1S(a) ody_apax_core_ecc_int_w1s_t 567 #define bustype_ODY_APAX_CORE_ECC_INT_W1S(a) CSR_TYPE_RSL 568 #define basename_ODY_APAX_CORE_ECC_INT_W1S(a) "APAX_CORE_ECC_INT_W1S" 569 #define device_bar_ODY_APAX_CORE_ECC_INT_W1S(a) 0x0 /* PF_BAR0 */ 570 #define busnum_ODY_APAX_CORE_ECC_INT_W1S(a) (a) 571 #define arguments_ODY_APAX_CORE_ECC_INT_W1S(a) (a), -1, -1, -1 572 573 /** 574 * Register (RSL) apa#_ctl 575 * 576 * APA Control Register 577 * This register contains miscellaneous APA control fields. 578 */ 579 union ody_apax_ctl { 580 uint64_t u; 581 struct ody_apax_ctl_s { 582 uint64_t dis_accel : 1; 583 uint64_t dis_lmtst : 1; 584 uint64_t dis_gwc : 1; 585 uint64_t dis_wdog_core_clean : 1; 586 uint64_t dis_wdog_struct_dat_clean : 1; 587 uint64_t dis_wdog_struct_rqb_clean : 1; 588 uint64_t dis_wdog_struct_txnid_clean : 1; 589 uint64_t dis_wdog_struct_crd_clean : 1; 590 uint64_t dvm_filter : 2; 591 uint64_t dis_wdog_during_apat : 1; 592 uint64_t cbusy_override_value : 1; 593 uint64_t dis_cbusy_override : 1; 594 uint64_t pfc_ns_access : 1; 595 uint64_t reserved_14_31 : 18; 596 uint64_t apa_crclk_force_on : 1; 597 uint64_t lsa_crclk_force_on : 1; 598 uint64_t reserved_34_63 : 30; 599 } s; 600 /* struct ody_apax_ctl_s cn; */ 601 }; 602 typedef union ody_apax_ctl ody_apax_ctl_t; 603 604 static inline uint64_t ODY_APAX_CTL(uint64_t a) __attribute__ ((pure, always_inline)); 605 static inline uint64_t ODY_APAX_CTL(uint64_t a) 606 { 607 if (a <= 89) 608 return 0x87e349001500ll + 0x1000000ll * ((a) & 0x7f); 609 __ody_csr_fatal("APAX_CTL", 1, a, 0, 0, 0, 0, 0); 610 } 611 612 #define typedef_ODY_APAX_CTL(a) ody_apax_ctl_t 613 #define bustype_ODY_APAX_CTL(a) CSR_TYPE_RSL 614 #define basename_ODY_APAX_CTL(a) "APAX_CTL" 615 #define device_bar_ODY_APAX_CTL(a) 0x0 /* PF_BAR0 */ 616 #define busnum_ODY_APAX_CTL(a) (a) 617 #define arguments_ODY_APAX_CTL(a) (a), -1, -1, -1 618 619 /** 620 * Register (RSL) apa#_derr_info 621 * 622 * APA Data Error Info Register 623 * This register records error information for Data Error interrupts occurring in data 624 * incoming from the mesh. The first [DATMBE] error will lock the 625 * register until the logged error type is cleared; [DATSBE] errors 626 * lock the register until either the logged error type is cleared or a [DATMBE] 627 * error is logged. Only one of [DATMBE, DATSBE] should be set at a time. In the 628 * event the register is read with all [*MBE] and [*SBE] equal to 0 during 629 * interrupt handling that is an indication that, due to a register set/clear race, 630 * information about one or more errors was lost while processing an earlier 631 * error. 632 */ 633 union ody_apax_derr_info { 634 uint64_t u; 635 struct ody_apax_derr_info_s { 636 uint64_t srcid : 11; 637 uint64_t opcode : 7; 638 uint64_t reserved_18_61 : 44; 639 uint64_t dat_mbe : 1; 640 uint64_t dat_sbe : 1; 641 } s; 642 /* struct ody_apax_derr_info_s cn; */ 643 }; 644 typedef union ody_apax_derr_info ody_apax_derr_info_t; 645 646 static inline uint64_t ODY_APAX_DERR_INFO(uint64_t a) __attribute__ ((pure, always_inline)); 647 static inline uint64_t ODY_APAX_DERR_INFO(uint64_t a) 648 { 649 if (a <= 89) 650 return 0x87e349001530ll + 0x1000000ll * ((a) & 0x7f); 651 __ody_csr_fatal("APAX_DERR_INFO", 1, a, 0, 0, 0, 0, 0); 652 } 653 654 #define typedef_ODY_APAX_DERR_INFO(a) ody_apax_derr_info_t 655 #define bustype_ODY_APAX_DERR_INFO(a) CSR_TYPE_RSL 656 #define basename_ODY_APAX_DERR_INFO(a) "APAX_DERR_INFO" 657 #define device_bar_ODY_APAX_DERR_INFO(a) 0x0 /* PF_BAR0 */ 658 #define busnum_ODY_APAX_DERR_INFO(a) (a) 659 #define arguments_ODY_APAX_DERR_INFO(a) (a), -1, -1, -1 660 661 /** 662 * Register (RSL) apa#_dispblk 663 * 664 * APA Dispatch Block Register 665 * This register throttles the core instruction dispatch. This is meant to be used by 666 * the SCP to mitigate overheat cases. 667 */ 668 union ody_apax_dispblk { 669 uint64_t u; 670 struct ody_apax_dispblk_s { 671 uint64_t count : 8; 672 uint64_t reserved_8_14 : 7; 673 uint64_t en : 1; 674 uint64_t reserved_16_63 : 48; 675 } s; 676 /* struct ody_apax_dispblk_s cn; */ 677 }; 678 typedef union ody_apax_dispblk ody_apax_dispblk_t; 679 680 static inline uint64_t ODY_APAX_DISPBLK(uint64_t a) __attribute__ ((pure, always_inline)); 681 static inline uint64_t ODY_APAX_DISPBLK(uint64_t a) 682 { 683 if (a <= 89) 684 return 0x87e349001700ll + 0x1000000ll * ((a) & 0x7f); 685 __ody_csr_fatal("APAX_DISPBLK", 1, a, 0, 0, 0, 0, 0); 686 } 687 688 #define typedef_ODY_APAX_DISPBLK(a) ody_apax_dispblk_t 689 #define bustype_ODY_APAX_DISPBLK(a) CSR_TYPE_RSL 690 #define basename_ODY_APAX_DISPBLK(a) "APAX_DISPBLK" 691 #define device_bar_ODY_APAX_DISPBLK(a) 0x0 /* PF_BAR0 */ 692 #define busnum_ODY_APAX_DISPBLK(a) (a) 693 #define arguments_ODY_APAX_DISPBLK(a) (a), -1, -1, -1 694 695 /** 696 * Register (RSL) apa#_ecc_ctl 697 * 698 * APA ECC Generation/Checking Control Register 699 * Controls ECC Generation/Checking. 700 */ 701 union ody_apax_ecc_ctl { 702 uint64_t u; 703 struct ody_apax_ecc_ctl_s { 704 uint64_t flip_datacheck_0 : 1; 705 uint64_t flip_datacheck_1 : 1; 706 uint64_t flip_datacheck_9 : 1; 707 uint64_t flip_datacheck_10 : 1; 708 uint64_t psn_dis : 1; 709 uint64_t cor_dis : 1; 710 uint64_t reserved_6_63 : 58; 711 } s; 712 /* struct ody_apax_ecc_ctl_s cn; */ 713 }; 714 typedef union ody_apax_ecc_ctl ody_apax_ecc_ctl_t; 715 716 static inline uint64_t ODY_APAX_ECC_CTL(uint64_t a) __attribute__ ((pure, always_inline)); 717 static inline uint64_t ODY_APAX_ECC_CTL(uint64_t a) 718 { 719 if (a <= 89) 720 return 0x87e349001508ll + 0x1000000ll * ((a) & 0x7f); 721 __ody_csr_fatal("APAX_ECC_CTL", 1, a, 0, 0, 0, 0, 0); 722 } 723 724 #define typedef_ODY_APAX_ECC_CTL(a) ody_apax_ecc_ctl_t 725 #define bustype_ODY_APAX_ECC_CTL(a) CSR_TYPE_RSL 726 #define basename_ODY_APAX_ECC_CTL(a) "APAX_ECC_CTL" 727 #define device_bar_ODY_APAX_ECC_CTL(a) 0x0 /* PF_BAR0 */ 728 #define busnum_ODY_APAX_ECC_CTL(a) (a) 729 #define arguments_ODY_APAX_ECC_CTL(a) (a), -1, -1, -1 730 731 /** 732 * Register (RSL) apa#_ecc_int_ena_w1c 733 * 734 * APA ECC Interrupt Enable Clear Registers 735 * This register clears interrupt enable bits. 736 */ 737 union ody_apax_ecc_int_ena_w1c { 738 uint64_t u; 739 struct ody_apax_ecc_int_ena_w1c_s { 740 uint64_t rsp_perr : 1; 741 uint64_t snp_perr : 1; 742 uint64_t dat_perr : 1; 743 uint64_t dat_mbe : 1; 744 uint64_t dat_sbe : 1; 745 uint64_t reserved_5_63 : 59; 746 } s; 747 /* struct ody_apax_ecc_int_ena_w1c_s cn; */ 748 }; 749 typedef union ody_apax_ecc_int_ena_w1c ody_apax_ecc_int_ena_w1c_t; 750 751 static inline uint64_t ODY_APAX_ECC_INT_ENA_W1C(uint64_t a) __attribute__ ((pure, always_inline)); 752 static inline uint64_t ODY_APAX_ECC_INT_ENA_W1C(uint64_t a) 753 { 754 if (a <= 89) 755 return 0x87e349001e50ll + 0x1000000ll * ((a) & 0x7f); 756 __ody_csr_fatal("APAX_ECC_INT_ENA_W1C", 1, a, 0, 0, 0, 0, 0); 757 } 758 759 #define typedef_ODY_APAX_ECC_INT_ENA_W1C(a) ody_apax_ecc_int_ena_w1c_t 760 #define bustype_ODY_APAX_ECC_INT_ENA_W1C(a) CSR_TYPE_RSL 761 #define basename_ODY_APAX_ECC_INT_ENA_W1C(a) "APAX_ECC_INT_ENA_W1C" 762 #define device_bar_ODY_APAX_ECC_INT_ENA_W1C(a) 0x0 /* PF_BAR0 */ 763 #define busnum_ODY_APAX_ECC_INT_ENA_W1C(a) (a) 764 #define arguments_ODY_APAX_ECC_INT_ENA_W1C(a) (a), -1, -1, -1 765 766 /** 767 * Register (RSL) apa#_ecc_int_ena_w1s 768 * 769 * APA ECC Interrupt Enable Set Registers 770 * This register sets interrupt enable bits. 771 */ 772 union ody_apax_ecc_int_ena_w1s { 773 uint64_t u; 774 struct ody_apax_ecc_int_ena_w1s_s { 775 uint64_t rsp_perr : 1; 776 uint64_t snp_perr : 1; 777 uint64_t dat_perr : 1; 778 uint64_t dat_mbe : 1; 779 uint64_t dat_sbe : 1; 780 uint64_t reserved_5_63 : 59; 781 } s; 782 /* struct ody_apax_ecc_int_ena_w1s_s cn; */ 783 }; 784 typedef union ody_apax_ecc_int_ena_w1s ody_apax_ecc_int_ena_w1s_t; 785 786 static inline uint64_t ODY_APAX_ECC_INT_ENA_W1S(uint64_t a) __attribute__ ((pure, always_inline)); 787 static inline uint64_t ODY_APAX_ECC_INT_ENA_W1S(uint64_t a) 788 { 789 if (a <= 89) 790 return 0x87e349001e58ll + 0x1000000ll * ((a) & 0x7f); 791 __ody_csr_fatal("APAX_ECC_INT_ENA_W1S", 1, a, 0, 0, 0, 0, 0); 792 } 793 794 #define typedef_ODY_APAX_ECC_INT_ENA_W1S(a) ody_apax_ecc_int_ena_w1s_t 795 #define bustype_ODY_APAX_ECC_INT_ENA_W1S(a) CSR_TYPE_RSL 796 #define basename_ODY_APAX_ECC_INT_ENA_W1S(a) "APAX_ECC_INT_ENA_W1S" 797 #define device_bar_ODY_APAX_ECC_INT_ENA_W1S(a) 0x0 /* PF_BAR0 */ 798 #define busnum_ODY_APAX_ECC_INT_ENA_W1S(a) (a) 799 #define arguments_ODY_APAX_ECC_INT_ENA_W1S(a) (a), -1, -1, -1 800 801 /** 802 * Register (RSL) apa#_ecc_int_w1c 803 * 804 * APA ECC Interrupt Register 805 * This register is reports interrupt status. 806 */ 807 union ody_apax_ecc_int_w1c { 808 uint64_t u; 809 struct ody_apax_ecc_int_w1c_s { 810 uint64_t rsp_perr : 1; 811 uint64_t snp_perr : 1; 812 uint64_t dat_perr : 1; 813 uint64_t dat_mbe : 1; 814 uint64_t dat_sbe : 1; 815 uint64_t reserved_5_63 : 59; 816 } s; 817 /* struct ody_apax_ecc_int_w1c_s cn; */ 818 }; 819 typedef union ody_apax_ecc_int_w1c ody_apax_ecc_int_w1c_t; 820 821 static inline uint64_t ODY_APAX_ECC_INT_W1C(uint64_t a) __attribute__ ((pure, always_inline)); 822 static inline uint64_t ODY_APAX_ECC_INT_W1C(uint64_t a) 823 { 824 if (a <= 89) 825 return 0x87e349001e40ll + 0x1000000ll * ((a) & 0x7f); 826 __ody_csr_fatal("APAX_ECC_INT_W1C", 1, a, 0, 0, 0, 0, 0); 827 } 828 829 #define typedef_ODY_APAX_ECC_INT_W1C(a) ody_apax_ecc_int_w1c_t 830 #define bustype_ODY_APAX_ECC_INT_W1C(a) CSR_TYPE_RSL 831 #define basename_ODY_APAX_ECC_INT_W1C(a) "APAX_ECC_INT_W1C" 832 #define device_bar_ODY_APAX_ECC_INT_W1C(a) 0x0 /* PF_BAR0 */ 833 #define busnum_ODY_APAX_ECC_INT_W1C(a) (a) 834 #define arguments_ODY_APAX_ECC_INT_W1C(a) (a), -1, -1, -1 835 836 /** 837 * Register (RSL) apa#_ecc_int_w1s 838 * 839 * APA ECC Interrupt Set Registers 840 * This register sets interrupt bits. 841 */ 842 union ody_apax_ecc_int_w1s { 843 uint64_t u; 844 struct ody_apax_ecc_int_w1s_s { 845 uint64_t rsp_perr : 1; 846 uint64_t snp_perr : 1; 847 uint64_t dat_perr : 1; 848 uint64_t dat_mbe : 1; 849 uint64_t dat_sbe : 1; 850 uint64_t reserved_5_63 : 59; 851 } s; 852 /* struct ody_apax_ecc_int_w1s_s cn; */ 853 }; 854 typedef union ody_apax_ecc_int_w1s ody_apax_ecc_int_w1s_t; 855 856 static inline uint64_t ODY_APAX_ECC_INT_W1S(uint64_t a) __attribute__ ((pure, always_inline)); 857 static inline uint64_t ODY_APAX_ECC_INT_W1S(uint64_t a) 858 { 859 if (a <= 89) 860 return 0x87e349001e48ll + 0x1000000ll * ((a) & 0x7f); 861 __ody_csr_fatal("APAX_ECC_INT_W1S", 1, a, 0, 0, 0, 0, 0); 862 } 863 864 #define typedef_ODY_APAX_ECC_INT_W1S(a) ody_apax_ecc_int_w1s_t 865 #define bustype_ODY_APAX_ECC_INT_W1S(a) CSR_TYPE_RSL 866 #define basename_ODY_APAX_ECC_INT_W1S(a) "APAX_ECC_INT_W1S" 867 #define device_bar_ODY_APAX_ECC_INT_W1S(a) 0x0 /* PF_BAR0 */ 868 #define busnum_ODY_APAX_ECC_INT_W1S(a) (a) 869 #define arguments_ODY_APAX_ECC_INT_W1S(a) (a), -1, -1, -1 870 871 /** 872 * Register (RSL) apa#_gti_offset 873 * 874 * APA Global Timestamp Offset Register 875 * The amount to add to the global timestamp, in whatever units the timestamp uses 876 * (generally 1ns). This is used to compensate for the propagation latency of the 877 * global timstamp bus to all the cores. 878 */ 879 union ody_apax_gti_offset { 880 uint64_t u; 881 struct ody_apax_gti_offset_s { 882 uint64_t offset : 8; 883 uint64_t reserved_8_63 : 56; 884 } s; 885 /* struct ody_apax_gti_offset_s cn; */ 886 }; 887 typedef union ody_apax_gti_offset ody_apax_gti_offset_t; 888 889 static inline uint64_t ODY_APAX_GTI_OFFSET(uint64_t a) __attribute__ ((pure, always_inline)); 890 static inline uint64_t ODY_APAX_GTI_OFFSET(uint64_t a) 891 { 892 if (a <= 89) 893 return 0x87e349001708ll + 0x1000000ll * ((a) & 0x7f); 894 __ody_csr_fatal("APAX_GTI_OFFSET", 1, a, 0, 0, 0, 0, 0); 895 } 896 897 #define typedef_ODY_APAX_GTI_OFFSET(a) ody_apax_gti_offset_t 898 #define bustype_ODY_APAX_GTI_OFFSET(a) CSR_TYPE_RSL 899 #define basename_ODY_APAX_GTI_OFFSET(a) "APAX_GTI_OFFSET" 900 #define device_bar_ODY_APAX_GTI_OFFSET(a) 0x0 /* PF_BAR0 */ 901 #define busnum_ODY_APAX_GTI_OFFSET(a) (a) 902 #define arguments_ODY_APAX_GTI_OFFSET(a) (a), -1, -1, -1 903 904 /** 905 * Register (RSL) apa#_man_pll 906 * 907 * APA Manual PLL Control Register 908 * These registers are used in conjunction with the APA_PLL registers when 909 * the APA_PLL[NEXT_MAN] field is set. Indexed by APA_PLL_E. 910 * These register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR]. 911 * 912 * The logic associated with the PLL functions can only process one operation at a time. 913 * Writes to this register should only occur when both the APA_PLL[NEXT_PGM] and 914 * APA_PLL[NEXT_SWITCH] fields are zero. 915 * 916 * This register is always reset on a chip domain reset. 917 */ 918 union ody_apax_man_pll { 919 uint64_t u; 920 struct ody_apax_man_pll_s { 921 uint64_t update_rate : 10; 922 uint64_t dlf_ki : 5; 923 uint64_t dlf_kp : 5; 924 uint64_t icp : 4; 925 uint64_t vco_fract : 10; 926 uint64_t vco_mul : 10; 927 uint64_t bw : 2; 928 uint64_t post_div : 9; 929 uint64_t reserved_55 : 1; 930 uint64_t ref_div : 4; 931 uint64_t power_down : 3; 932 uint64_t reserved_63 : 1; 933 } s; 934 /* struct ody_apax_man_pll_s cn; */ 935 }; 936 typedef union ody_apax_man_pll ody_apax_man_pll_t; 937 938 static inline uint64_t ODY_APAX_MAN_PLL(uint64_t a) __attribute__ ((pure, always_inline)); 939 static inline uint64_t ODY_APAX_MAN_PLL(uint64_t a) 940 { 941 if (a <= 89) 942 return 0x87e349004008ll + 0x1000000ll * ((a) & 0x7f); 943 __ody_csr_fatal("APAX_MAN_PLL", 1, a, 0, 0, 0, 0, 0); 944 } 945 946 #define typedef_ODY_APAX_MAN_PLL(a) ody_apax_man_pll_t 947 #define bustype_ODY_APAX_MAN_PLL(a) CSR_TYPE_RSL 948 #define basename_ODY_APAX_MAN_PLL(a) "APAX_MAN_PLL" 949 #define device_bar_ODY_APAX_MAN_PLL(a) 0x0 /* PF_BAR0 */ 950 #define busnum_ODY_APAX_MAN_PLL(a) (a) 951 #define arguments_ODY_APAX_MAN_PLL(a) (a), -1, -1, -1 952 953 /** 954 * Register (RSL) apa#_msix_pba# 955 * 956 * APA MSI-X Pending Bit Array Registers 957 * This register is the MSI-X PBA table, the bit number is indexed by the APA_INT_VEC_E enumeration. 958 */ 959 union ody_apax_msix_pbax { 960 uint64_t u; 961 struct ody_apax_msix_pbax_s { 962 uint64_t pend : 64; 963 } s; 964 /* struct ody_apax_msix_pbax_s cn; */ 965 }; 966 typedef union ody_apax_msix_pbax ody_apax_msix_pbax_t; 967 968 static inline uint64_t ODY_APAX_MSIX_PBAX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 969 static inline uint64_t ODY_APAX_MSIX_PBAX(uint64_t a, uint64_t b) 970 { 971 if ((a <= 89) && (b == 0)) 972 return 0x87e3491f0000ll + 0x1000000ll * ((a) & 0x7f); 973 __ody_csr_fatal("APAX_MSIX_PBAX", 2, a, b, 0, 0, 0, 0); 974 } 975 976 #define typedef_ODY_APAX_MSIX_PBAX(a, b) ody_apax_msix_pbax_t 977 #define bustype_ODY_APAX_MSIX_PBAX(a, b) CSR_TYPE_RSL 978 #define basename_ODY_APAX_MSIX_PBAX(a, b) "APAX_MSIX_PBAX" 979 #define device_bar_ODY_APAX_MSIX_PBAX(a, b) 0x4 /* PF_BAR4 */ 980 #define busnum_ODY_APAX_MSIX_PBAX(a, b) (a) 981 #define arguments_ODY_APAX_MSIX_PBAX(a, b) (a), (b), -1, -1 982 983 /** 984 * Register (RSL) apa#_msix_vec#_addr 985 * 986 * APA MSI-X Vector Table Address Registers 987 * This register is the MSI-X vector table, indexed by the APA_INT_VEC_E enumeration. 988 */ 989 union ody_apax_msix_vecx_addr { 990 uint64_t u; 991 struct ody_apax_msix_vecx_addr_s { 992 uint64_t secvec : 1; 993 uint64_t reserved_1 : 1; 994 uint64_t addr : 51; 995 uint64_t reserved_53_63 : 11; 996 } s; 997 /* struct ody_apax_msix_vecx_addr_s cn; */ 998 }; 999 typedef union ody_apax_msix_vecx_addr ody_apax_msix_vecx_addr_t; 1000 1001 static inline uint64_t ODY_APAX_MSIX_VECX_ADDR(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 1002 static inline uint64_t ODY_APAX_MSIX_VECX_ADDR(uint64_t a, uint64_t b) 1003 { 1004 if ((a <= 89) && (b <= 7)) 1005 return 0x87e349100000ll + 0x1000000ll * ((a) & 0x7f) + 0x10ll * ((b) & 0x7); 1006 __ody_csr_fatal("APAX_MSIX_VECX_ADDR", 2, a, b, 0, 0, 0, 0); 1007 } 1008 1009 #define typedef_ODY_APAX_MSIX_VECX_ADDR(a, b) ody_apax_msix_vecx_addr_t 1010 #define bustype_ODY_APAX_MSIX_VECX_ADDR(a, b) CSR_TYPE_RSL 1011 #define basename_ODY_APAX_MSIX_VECX_ADDR(a, b) "APAX_MSIX_VECX_ADDR" 1012 #define device_bar_ODY_APAX_MSIX_VECX_ADDR(a, b) 0x4 /* PF_BAR4 */ 1013 #define busnum_ODY_APAX_MSIX_VECX_ADDR(a, b) (a) 1014 #define arguments_ODY_APAX_MSIX_VECX_ADDR(a, b) (a), (b), -1, -1 1015 1016 /** 1017 * Register (RSL) apa#_msix_vec#_ctl 1018 * 1019 * APA MSI-X Vector Table Control and Data Registers 1020 * This register is the MSI-X vector table, indexed by the APA_INT_VEC_E enumeration. 1021 */ 1022 union ody_apax_msix_vecx_ctl { 1023 uint64_t u; 1024 struct ody_apax_msix_vecx_ctl_s { 1025 uint64_t data : 32; 1026 uint64_t mask : 1; 1027 uint64_t reserved_33_63 : 31; 1028 } s; 1029 /* struct ody_apax_msix_vecx_ctl_s cn; */ 1030 }; 1031 typedef union ody_apax_msix_vecx_ctl ody_apax_msix_vecx_ctl_t; 1032 1033 static inline uint64_t ODY_APAX_MSIX_VECX_CTL(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 1034 static inline uint64_t ODY_APAX_MSIX_VECX_CTL(uint64_t a, uint64_t b) 1035 { 1036 if ((a <= 89) && (b <= 7)) 1037 return 0x87e349100008ll + 0x1000000ll * ((a) & 0x7f) + 0x10ll * ((b) & 0x7); 1038 __ody_csr_fatal("APAX_MSIX_VECX_CTL", 2, a, b, 0, 0, 0, 0); 1039 } 1040 1041 #define typedef_ODY_APAX_MSIX_VECX_CTL(a, b) ody_apax_msix_vecx_ctl_t 1042 #define bustype_ODY_APAX_MSIX_VECX_CTL(a, b) CSR_TYPE_RSL 1043 #define basename_ODY_APAX_MSIX_VECX_CTL(a, b) "APAX_MSIX_VECX_CTL" 1044 #define device_bar_ODY_APAX_MSIX_VECX_CTL(a, b) 0x4 /* PF_BAR4 */ 1045 #define busnum_ODY_APAX_MSIX_VECX_CTL(a, b) (a) 1046 #define arguments_ODY_APAX_MSIX_VECX_CTL(a, b) (a), (b), -1, -1 1047 1048 /** 1049 * Register (RSL) apa#_nderr_info 1050 * 1051 * APA Non-Data Error Info Register 1052 * This register records error information for Non-Data Error interrupts 1053 * [RSP_PERR, DAT_PERR, SNP_PERR]. The first [RSP_PERR, DAT_PERR, SNP_PERR] error 1054 * will lock the register until the logged error type is cleared. 1055 */ 1056 union ody_apax_nderr_info { 1057 uint64_t u; 1058 struct ody_apax_nderr_info_s { 1059 uint64_t srcid : 11; 1060 uint64_t opcode : 7; 1061 uint64_t reserved_18_57 : 40; 1062 uint64_t snp_perr : 1; 1063 uint64_t dat_perr : 1; 1064 uint64_t rsp_perr : 1; 1065 uint64_t reserved_61_63 : 3; 1066 } s; 1067 /* struct ody_apax_nderr_info_s cn; */ 1068 }; 1069 typedef union ody_apax_nderr_info ody_apax_nderr_info_t; 1070 1071 static inline uint64_t ODY_APAX_NDERR_INFO(uint64_t a) __attribute__ ((pure, always_inline)); 1072 static inline uint64_t ODY_APAX_NDERR_INFO(uint64_t a) 1073 { 1074 if (a <= 89) 1075 return 0x87e349001528ll + 0x1000000ll * ((a) & 0x7f); 1076 __ody_csr_fatal("APAX_NDERR_INFO", 1, a, 0, 0, 0, 0, 0); 1077 } 1078 1079 #define typedef_ODY_APAX_NDERR_INFO(a) ody_apax_nderr_info_t 1080 #define bustype_ODY_APAX_NDERR_INFO(a) CSR_TYPE_RSL 1081 #define basename_ODY_APAX_NDERR_INFO(a) "APAX_NDERR_INFO" 1082 #define device_bar_ODY_APAX_NDERR_INFO(a) 0x0 /* PF_BAR0 */ 1083 #define busnum_ODY_APAX_NDERR_INFO(a) (a) 1084 #define arguments_ODY_APAX_NDERR_INFO(a) (a), -1, -1, -1 1085 1086 /** 1087 * Register (RSL) apa#_pfc# 1088 * 1089 * APA Performance Counter Registers 1090 */ 1091 union ody_apax_pfcx { 1092 uint64_t u; 1093 struct ody_apax_pfcx_s { 1094 uint64_t count : 64; 1095 } s; 1096 /* struct ody_apax_pfcx_s cn; */ 1097 }; 1098 typedef union ody_apax_pfcx ody_apax_pfcx_t; 1099 1100 static inline uint64_t ODY_APAX_PFCX(uint64_t a, uint64_t b) __attribute__ ((pure, always_inline)); 1101 static inline uint64_t ODY_APAX_PFCX(uint64_t a, uint64_t b) 1102 { 1103 if ((a <= 89) && (b <= 5)) 1104 return 0x87e349010000ll + 0x1000000ll * ((a) & 0x7f) + 8ll * ((b) & 0x7); 1105 __ody_csr_fatal("APAX_PFCX", 2, a, b, 0, 0, 0, 0); 1106 } 1107 1108 #define typedef_ODY_APAX_PFCX(a, b) ody_apax_pfcx_t 1109 #define bustype_ODY_APAX_PFCX(a, b) CSR_TYPE_RSL 1110 #define basename_ODY_APAX_PFCX(a, b) "APAX_PFCX" 1111 #define device_bar_ODY_APAX_PFCX(a, b) 0x0 /* PF_BAR0 */ 1112 #define busnum_ODY_APAX_PFCX(a, b) (a) 1113 #define arguments_ODY_APAX_PFCX(a, b) (a), (b), -1, -1 1114 1115 /** 1116 * Register (RSL) apa#_pll 1117 * 1118 * APA PLL Control Register 1119 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR]. 1120 * Each index of this register controls a PLL on the chip. The register is used for 1121 * typical programming operations and is supplemented with the APA_MAN_PLL 1122 * register when selected. Indexed by APA_PLL_E. 1123 * 1124 * The logic associated with the PLL functions can only process one operation at a time. 1125 * Writes to this register and to both APA_MAN_PLL and APA_TEST_PLL should only occur 1126 * when both the NEXT_PGM and NEXT_SWITCH fields are zero. It is typically necessary 1127 * to poll this register to confirm this. 1128 * 1129 * The register fields are returned to reset values on a chip domain reset unless 1130 * specifically noted. 1131 */ 1132 union ody_apax_pll { 1133 uint64_t u; 1134 struct ody_apax_pll_s { 1135 uint64_t next_switch : 16; 1136 uint64_t next_pgm : 1; 1137 uint64_t next_man : 1; 1138 uint64_t reserved_18_20 : 3; 1139 uint64_t next_pll_sel : 3; 1140 uint64_t next_mul : 7; 1141 uint64_t reserved_31 : 1; 1142 uint64_t init_mul : 7; 1143 uint64_t reserved_39 : 1; 1144 uint64_t max_mul : 7; 1145 uint64_t reserved_47 : 1; 1146 uint64_t cur_mul : 7; 1147 uint64_t no_rst_chip : 1; 1148 uint64_t no_auto_pgm : 1; 1149 uint64_t cur_pll_sel : 3; 1150 uint64_t reserved_60 : 1; 1151 uint64_t alt_ref : 1; 1152 uint64_t pll1_present : 1; 1153 uint64_t aro_present : 1; 1154 } s; 1155 /* struct ody_apax_pll_s cn; */ 1156 }; 1157 typedef union ody_apax_pll ody_apax_pll_t; 1158 1159 static inline uint64_t ODY_APAX_PLL(uint64_t a) __attribute__ ((pure, always_inline)); 1160 static inline uint64_t ODY_APAX_PLL(uint64_t a) 1161 { 1162 if (a <= 89) 1163 return 0x87e349004000ll + 0x1000000ll * ((a) & 0x7f); 1164 __ody_csr_fatal("APAX_PLL", 1, a, 0, 0, 0, 0, 0); 1165 } 1166 1167 #define typedef_ODY_APAX_PLL(a) ody_apax_pll_t 1168 #define bustype_ODY_APAX_PLL(a) CSR_TYPE_RSL 1169 #define basename_ODY_APAX_PLL(a) "APAX_PLL" 1170 #define device_bar_ODY_APAX_PLL(a) 0x0 /* PF_BAR0 */ 1171 #define busnum_ODY_APAX_PLL(a) (a) 1172 #define arguments_ODY_APAX_PLL(a) (a), -1, -1, -1 1173 1174 /** 1175 * Register (RSL) apa#_pllro_status 1176 * 1177 * APA PLLRO Status Register 1178 */ 1179 union ody_apax_pllro_status { 1180 uint64_t u; 1181 struct ody_apax_pllro_status_s { 1182 uint64_t status : 32; 1183 uint64_t droop : 1; 1184 uint64_t reserved_33_63 : 31; 1185 } s; 1186 /* struct ody_apax_pllro_status_s cn; */ 1187 }; 1188 typedef union ody_apax_pllro_status ody_apax_pllro_status_t; 1189 1190 static inline uint64_t ODY_APAX_PLLRO_STATUS(uint64_t a) __attribute__ ((pure, always_inline)); 1191 static inline uint64_t ODY_APAX_PLLRO_STATUS(uint64_t a) 1192 { 1193 if (a <= 89) 1194 return 0x87e349001f00ll + 0x1000000ll * ((a) & 0x7f); 1195 __ody_csr_fatal("APAX_PLLRO_STATUS", 1, a, 0, 0, 0, 0, 0); 1196 } 1197 1198 #define typedef_ODY_APAX_PLLRO_STATUS(a) ody_apax_pllro_status_t 1199 #define bustype_ODY_APAX_PLLRO_STATUS(a) CSR_TYPE_RSL 1200 #define basename_ODY_APAX_PLLRO_STATUS(a) "APAX_PLLRO_STATUS" 1201 #define device_bar_ODY_APAX_PLLRO_STATUS(a) 0x0 /* PF_BAR0 */ 1202 #define busnum_ODY_APAX_PLLRO_STATUS(a) (a) 1203 #define arguments_ODY_APAX_PLLRO_STATUS(a) (a), -1, -1, -1 1204 1205 /** 1206 * Register (RSL) apa#_prf 1207 * 1208 * APA Performance Counter Control Register 1209 * This register controls measurement of the number of sent/received flits from APA 1210 * to/from the Xcalibur mesh. 1211 */ 1212 union ody_apax_prf { 1213 uint64_t u; 1214 struct ody_apax_prf_s { 1215 uint64_t tx_req_en : 1; 1216 uint64_t tx_rsp_en : 1; 1217 uint64_t tx_dat_en : 1; 1218 uint64_t rx_rsp_en : 1; 1219 uint64_t rx_snp_en : 1; 1220 uint64_t rx_dat_en : 1; 1221 uint64_t reserved_6_63 : 58; 1222 } s; 1223 /* struct ody_apax_prf_s cn; */ 1224 }; 1225 typedef union ody_apax_prf ody_apax_prf_t; 1226 1227 static inline uint64_t ODY_APAX_PRF(uint64_t a) __attribute__ ((pure, always_inline)); 1228 static inline uint64_t ODY_APAX_PRF(uint64_t a) 1229 { 1230 if (a <= 89) 1231 return 0x87e349010100ll + 0x1000000ll * ((a) & 0x7f); 1232 __ody_csr_fatal("APAX_PRF", 1, a, 0, 0, 0, 0, 0); 1233 } 1234 1235 #define typedef_ODY_APAX_PRF(a) ody_apax_prf_t 1236 #define bustype_ODY_APAX_PRF(a) CSR_TYPE_RSL 1237 #define basename_ODY_APAX_PRF(a) "APAX_PRF" 1238 #define device_bar_ODY_APAX_PRF(a) 0x0 /* PF_BAR0 */ 1239 #define busnum_ODY_APAX_PRF(a) (a) 1240 #define arguments_ODY_APAX_PRF(a) (a), -1, -1, -1 1241 1242 /** 1243 * Register (RSL) apa#_rvbaraddr 1244 * 1245 * APA Reset Base Address Register 1246 */ 1247 union ody_apax_rvbaraddr { 1248 uint64_t u; 1249 struct ody_apax_rvbaraddr_s { 1250 uint64_t reserved_0_1 : 2; 1251 uint64_t addr : 46; 1252 uint64_t reserved_48_63 : 16; 1253 } s; 1254 /* struct ody_apax_rvbaraddr_s cn; */ 1255 }; 1256 typedef union ody_apax_rvbaraddr ody_apax_rvbaraddr_t; 1257 1258 static inline uint64_t ODY_APAX_RVBARADDR(uint64_t a) __attribute__ ((pure, always_inline)); 1259 static inline uint64_t ODY_APAX_RVBARADDR(uint64_t a) 1260 { 1261 if (a <= 89) 1262 return 0x87e349001400ll + 0x1000000ll * ((a) & 0x7f); 1263 __ody_csr_fatal("APAX_RVBARADDR", 1, a, 0, 0, 0, 0, 0); 1264 } 1265 1266 #define typedef_ODY_APAX_RVBARADDR(a) ody_apax_rvbaraddr_t 1267 #define bustype_ODY_APAX_RVBARADDR(a) CSR_TYPE_RSL 1268 #define basename_ODY_APAX_RVBARADDR(a) "APAX_RVBARADDR" 1269 #define device_bar_ODY_APAX_RVBARADDR(a) 0x0 /* PF_BAR0 */ 1270 #define busnum_ODY_APAX_RVBARADDR(a) (a) 1271 #define arguments_ODY_APAX_RVBARADDR(a) (a), -1, -1, -1 1272 1273 /** 1274 * Register (RSL) apa#_test_pll 1275 * 1276 * APA PLL Test Register 1277 * This register controls manual ARO programming and Test features. 1278 * 1279 * The logic associated with the PLL functions can only process one operation at a time. 1280 * Writes to this register should only occur when both the APA_PLL[NEXT_PGM] and 1281 * APA_PLL[NEXT_SWITCH] fields are zero. Additionally a read operation should occur 1282 * between writes to this register to allow time for the test setting to be transmitted 1283 * successfully before new setting are applied. 1284 */ 1285 union ody_apax_test_pll { 1286 uint64_t u; 1287 struct ody_apax_test_pll_s { 1288 uint64_t stop_cnt : 32; 1289 uint64_t stop_clk : 1; 1290 uint64_t msc_enable : 1; 1291 uint64_t testclk_pll1 : 1; 1292 uint64_t reserved_35_39 : 5; 1293 uint64_t test_ana : 5; 1294 uint64_t test_rsvd : 3; 1295 uint64_t reserved_48_63 : 16; 1296 } s; 1297 /* struct ody_apax_test_pll_s cn; */ 1298 }; 1299 typedef union ody_apax_test_pll ody_apax_test_pll_t; 1300 1301 static inline uint64_t ODY_APAX_TEST_PLL(uint64_t a) __attribute__ ((pure, always_inline)); 1302 static inline uint64_t ODY_APAX_TEST_PLL(uint64_t a) 1303 { 1304 if (a <= 89) 1305 return 0x87e349004010ll + 0x1000000ll * ((a) & 0x7f); 1306 __ody_csr_fatal("APAX_TEST_PLL", 1, a, 0, 0, 0, 0, 0); 1307 } 1308 1309 #define typedef_ODY_APAX_TEST_PLL(a) ody_apax_test_pll_t 1310 #define bustype_ODY_APAX_TEST_PLL(a) CSR_TYPE_RSL 1311 #define basename_ODY_APAX_TEST_PLL(a) "APAX_TEST_PLL" 1312 #define device_bar_ODY_APAX_TEST_PLL(a) 0x0 /* PF_BAR0 */ 1313 #define busnum_ODY_APAX_TEST_PLL(a) (a) 1314 #define arguments_ODY_APAX_TEST_PLL(a) (a), -1, -1, -1 1315 1316 /** 1317 * Register (RSL) apa#_wdog_core 1318 * 1319 * APA Watchdog Core Register 1320 * This register configures the timeouts for a core to receive responses. 1321 */ 1322 union ody_apax_wdog_core { 1323 uint64_t u; 1324 struct ody_apax_wdog_core_s { 1325 uint64_t timeout : 31; 1326 uint64_t enable : 1; 1327 uint64_t reserved_32_63 : 32; 1328 } s; 1329 /* struct ody_apax_wdog_core_s cn; */ 1330 }; 1331 typedef union ody_apax_wdog_core ody_apax_wdog_core_t; 1332 1333 static inline uint64_t ODY_APAX_WDOG_CORE(uint64_t a) __attribute__ ((pure, always_inline)); 1334 static inline uint64_t ODY_APAX_WDOG_CORE(uint64_t a) 1335 { 1336 if (a <= 89) 1337 return 0x87e349001300ll + 0x1000000ll * ((a) & 0x7f); 1338 __ody_csr_fatal("APAX_WDOG_CORE", 1, a, 0, 0, 0, 0, 0); 1339 } 1340 1341 #define typedef_ODY_APAX_WDOG_CORE(a) ody_apax_wdog_core_t 1342 #define bustype_ODY_APAX_WDOG_CORE(a) CSR_TYPE_RSL 1343 #define basename_ODY_APAX_WDOG_CORE(a) "APAX_WDOG_CORE" 1344 #define device_bar_ODY_APAX_WDOG_CORE(a) 0x0 /* PF_BAR0 */ 1345 #define busnum_ODY_APAX_WDOG_CORE(a) (a) 1346 #define arguments_ODY_APAX_WDOG_CORE(a) (a), -1, -1, -1 1347 1348 /** 1349 * Register (RSL) apa#_wdog_core_diag 1350 * 1351 * APA Watchdog Core Diagnostic Register 1352 * This register reports and captures wdog timeouts for core. Timeouts indicate that 1353 * the core did not receive all the expected responses. 1354 */ 1355 union ody_apax_wdog_core_diag { 1356 uint64_t u; 1357 struct ody_apax_wdog_core_diag_s { 1358 uint64_t txnid : 12; 1359 uint64_t reqt : 3; 1360 uint64_t epoch : 1; 1361 uint64_t state : 4; 1362 uint64_t reserved_20_29 : 10; 1363 uint64_t stale : 1; 1364 uint64_t multi : 1; 1365 uint64_t reserved_32_63 : 32; 1366 } s; 1367 /* struct ody_apax_wdog_core_diag_s cn; */ 1368 }; 1369 typedef union ody_apax_wdog_core_diag ody_apax_wdog_core_diag_t; 1370 1371 static inline uint64_t ODY_APAX_WDOG_CORE_DIAG(uint64_t a) __attribute__ ((pure, always_inline)); 1372 static inline uint64_t ODY_APAX_WDOG_CORE_DIAG(uint64_t a) 1373 { 1374 if (a <= 89) 1375 return 0x87e349001310ll + 0x1000000ll * ((a) & 0x7f); 1376 __ody_csr_fatal("APAX_WDOG_CORE_DIAG", 1, a, 0, 0, 0, 0, 0); 1377 } 1378 1379 #define typedef_ODY_APAX_WDOG_CORE_DIAG(a) ody_apax_wdog_core_diag_t 1380 #define bustype_ODY_APAX_WDOG_CORE_DIAG(a) CSR_TYPE_RSL 1381 #define basename_ODY_APAX_WDOG_CORE_DIAG(a) "APAX_WDOG_CORE_DIAG" 1382 #define device_bar_ODY_APAX_WDOG_CORE_DIAG(a) 0x0 /* PF_BAR0 */ 1383 #define busnum_ODY_APAX_WDOG_CORE_DIAG(a) (a) 1384 #define arguments_ODY_APAX_WDOG_CORE_DIAG(a) (a), -1, -1, -1 1385 1386 /** 1387 * Register (RSL) apa#_wdog_int_ena_w1c 1388 * 1389 * APA Watchdog Interrupt Enable Clear Registers 1390 * This register clears interrupt enable bits. 1391 */ 1392 union ody_apax_wdog_int_ena_w1c { 1393 uint64_t u; 1394 struct ody_apax_wdog_int_ena_w1c_s { 1395 uint64_t wdog_core : 1; 1396 uint64_t wdog_struct_crd : 1; 1397 uint64_t wdog_struct_dat : 1; 1398 uint64_t wdog_struct_rqb : 1; 1399 uint64_t wdog_struct_txnid : 1; 1400 uint64_t reserved_5_63 : 59; 1401 } s; 1402 /* struct ody_apax_wdog_int_ena_w1c_s cn; */ 1403 }; 1404 typedef union ody_apax_wdog_int_ena_w1c ody_apax_wdog_int_ena_w1c_t; 1405 1406 static inline uint64_t ODY_APAX_WDOG_INT_ENA_W1C(uint64_t a) __attribute__ ((pure, always_inline)); 1407 static inline uint64_t ODY_APAX_WDOG_INT_ENA_W1C(uint64_t a) 1408 { 1409 if (a <= 89) 1410 return 0x87e349001e30ll + 0x1000000ll * ((a) & 0x7f); 1411 __ody_csr_fatal("APAX_WDOG_INT_ENA_W1C", 1, a, 0, 0, 0, 0, 0); 1412 } 1413 1414 #define typedef_ODY_APAX_WDOG_INT_ENA_W1C(a) ody_apax_wdog_int_ena_w1c_t 1415 #define bustype_ODY_APAX_WDOG_INT_ENA_W1C(a) CSR_TYPE_RSL 1416 #define basename_ODY_APAX_WDOG_INT_ENA_W1C(a) "APAX_WDOG_INT_ENA_W1C" 1417 #define device_bar_ODY_APAX_WDOG_INT_ENA_W1C(a) 0x0 /* PF_BAR0 */ 1418 #define busnum_ODY_APAX_WDOG_INT_ENA_W1C(a) (a) 1419 #define arguments_ODY_APAX_WDOG_INT_ENA_W1C(a) (a), -1, -1, -1 1420 1421 /** 1422 * Register (RSL) apa#_wdog_int_ena_w1s 1423 * 1424 * APA Watchdog Interrupt Enable Set Registers 1425 * This register sets interrupt enable bits. 1426 */ 1427 union ody_apax_wdog_int_ena_w1s { 1428 uint64_t u; 1429 struct ody_apax_wdog_int_ena_w1s_s { 1430 uint64_t wdog_core : 1; 1431 uint64_t wdog_struct_crd : 1; 1432 uint64_t wdog_struct_dat : 1; 1433 uint64_t wdog_struct_rqb : 1; 1434 uint64_t wdog_struct_txnid : 1; 1435 uint64_t reserved_5_63 : 59; 1436 } s; 1437 /* struct ody_apax_wdog_int_ena_w1s_s cn; */ 1438 }; 1439 typedef union ody_apax_wdog_int_ena_w1s ody_apax_wdog_int_ena_w1s_t; 1440 1441 static inline uint64_t ODY_APAX_WDOG_INT_ENA_W1S(uint64_t a) __attribute__ ((pure, always_inline)); 1442 static inline uint64_t ODY_APAX_WDOG_INT_ENA_W1S(uint64_t a) 1443 { 1444 if (a <= 89) 1445 return 0x87e349001e38ll + 0x1000000ll * ((a) & 0x7f); 1446 __ody_csr_fatal("APAX_WDOG_INT_ENA_W1S", 1, a, 0, 0, 0, 0, 0); 1447 } 1448 1449 #define typedef_ODY_APAX_WDOG_INT_ENA_W1S(a) ody_apax_wdog_int_ena_w1s_t 1450 #define bustype_ODY_APAX_WDOG_INT_ENA_W1S(a) CSR_TYPE_RSL 1451 #define basename_ODY_APAX_WDOG_INT_ENA_W1S(a) "APAX_WDOG_INT_ENA_W1S" 1452 #define device_bar_ODY_APAX_WDOG_INT_ENA_W1S(a) 0x0 /* PF_BAR0 */ 1453 #define busnum_ODY_APAX_WDOG_INT_ENA_W1S(a) (a) 1454 #define arguments_ODY_APAX_WDOG_INT_ENA_W1S(a) (a), -1, -1, -1 1455 1456 /** 1457 * Register (RSL) apa#_wdog_int_w1c 1458 * 1459 * APA Watchdog Interrupt Register 1460 * This register reports watchdog interrupt status. 1461 */ 1462 union ody_apax_wdog_int_w1c { 1463 uint64_t u; 1464 struct ody_apax_wdog_int_w1c_s { 1465 uint64_t wdog_core : 1; 1466 uint64_t wdog_struct_crd : 1; 1467 uint64_t wdog_struct_dat : 1; 1468 uint64_t wdog_struct_rqb : 1; 1469 uint64_t wdog_struct_txnid : 1; 1470 uint64_t reserved_5_63 : 59; 1471 } s; 1472 /* struct ody_apax_wdog_int_w1c_s cn; */ 1473 }; 1474 typedef union ody_apax_wdog_int_w1c ody_apax_wdog_int_w1c_t; 1475 1476 static inline uint64_t ODY_APAX_WDOG_INT_W1C(uint64_t a) __attribute__ ((pure, always_inline)); 1477 static inline uint64_t ODY_APAX_WDOG_INT_W1C(uint64_t a) 1478 { 1479 if (a <= 89) 1480 return 0x87e349001e20ll + 0x1000000ll * ((a) & 0x7f); 1481 __ody_csr_fatal("APAX_WDOG_INT_W1C", 1, a, 0, 0, 0, 0, 0); 1482 } 1483 1484 #define typedef_ODY_APAX_WDOG_INT_W1C(a) ody_apax_wdog_int_w1c_t 1485 #define bustype_ODY_APAX_WDOG_INT_W1C(a) CSR_TYPE_RSL 1486 #define basename_ODY_APAX_WDOG_INT_W1C(a) "APAX_WDOG_INT_W1C" 1487 #define device_bar_ODY_APAX_WDOG_INT_W1C(a) 0x0 /* PF_BAR0 */ 1488 #define busnum_ODY_APAX_WDOG_INT_W1C(a) (a) 1489 #define arguments_ODY_APAX_WDOG_INT_W1C(a) (a), -1, -1, -1 1490 1491 /** 1492 * Register (RSL) apa#_wdog_int_w1s 1493 * 1494 * APA Watchdog Interrupt Set Registers 1495 * This register sets interrupt bits. 1496 */ 1497 union ody_apax_wdog_int_w1s { 1498 uint64_t u; 1499 struct ody_apax_wdog_int_w1s_s { 1500 uint64_t wdog_core : 1; 1501 uint64_t wdog_struct_crd : 1; 1502 uint64_t wdog_struct_dat : 1; 1503 uint64_t wdog_struct_rqb : 1; 1504 uint64_t wdog_struct_txnid : 1; 1505 uint64_t reserved_5_63 : 59; 1506 } s; 1507 /* struct ody_apax_wdog_int_w1s_s cn; */ 1508 }; 1509 typedef union ody_apax_wdog_int_w1s ody_apax_wdog_int_w1s_t; 1510 1511 static inline uint64_t ODY_APAX_WDOG_INT_W1S(uint64_t a) __attribute__ ((pure, always_inline)); 1512 static inline uint64_t ODY_APAX_WDOG_INT_W1S(uint64_t a) 1513 { 1514 if (a <= 89) 1515 return 0x87e349001e28ll + 0x1000000ll * ((a) & 0x7f); 1516 __ody_csr_fatal("APAX_WDOG_INT_W1S", 1, a, 0, 0, 0, 0, 0); 1517 } 1518 1519 #define typedef_ODY_APAX_WDOG_INT_W1S(a) ody_apax_wdog_int_w1s_t 1520 #define bustype_ODY_APAX_WDOG_INT_W1S(a) CSR_TYPE_RSL 1521 #define basename_ODY_APAX_WDOG_INT_W1S(a) "APAX_WDOG_INT_W1S" 1522 #define device_bar_ODY_APAX_WDOG_INT_W1S(a) 0x0 /* PF_BAR0 */ 1523 #define busnum_ODY_APAX_WDOG_INT_W1S(a) (a) 1524 #define arguments_ODY_APAX_WDOG_INT_W1S(a) (a), -1, -1, -1 1525 1526 /** 1527 * Register (RSL) apa#_wdog_struct 1528 * 1529 * APA Watchdog Structure Register 1530 * This register configures the timeouts for APA internal structures to clear. 1531 */ 1532 union ody_apax_wdog_struct { 1533 uint64_t u; 1534 struct ody_apax_wdog_struct_s { 1535 uint64_t timeout : 31; 1536 uint64_t enable : 1; 1537 uint64_t reserved_32_63 : 32; 1538 } s; 1539 /* struct ody_apax_wdog_struct_s cn; */ 1540 }; 1541 typedef union ody_apax_wdog_struct ody_apax_wdog_struct_t; 1542 1543 static inline uint64_t ODY_APAX_WDOG_STRUCT(uint64_t a) __attribute__ ((pure, always_inline)); 1544 static inline uint64_t ODY_APAX_WDOG_STRUCT(uint64_t a) 1545 { 1546 if (a <= 89) 1547 return 0x87e349001308ll + 0x1000000ll * ((a) & 0x7f); 1548 __ody_csr_fatal("APAX_WDOG_STRUCT", 1, a, 0, 0, 0, 0, 0); 1549 } 1550 1551 #define typedef_ODY_APAX_WDOG_STRUCT(a) ody_apax_wdog_struct_t 1552 #define bustype_ODY_APAX_WDOG_STRUCT(a) CSR_TYPE_RSL 1553 #define basename_ODY_APAX_WDOG_STRUCT(a) "APAX_WDOG_STRUCT" 1554 #define device_bar_ODY_APAX_WDOG_STRUCT(a) 0x0 /* PF_BAR0 */ 1555 #define busnum_ODY_APAX_WDOG_STRUCT(a) (a) 1556 #define arguments_ODY_APAX_WDOG_STRUCT(a) (a), -1, -1, -1 1557 1558 /** 1559 * Register (RSL) apa#_wdog_struct_crd_diag 1560 * 1561 * APA Watchdog Structure Credit Diagnostic Register 1562 * This register reports and captures watchdog timeouts for CRD, which indicates that 1563 * an unexpected CHI protocol credit was received. 1564 */ 1565 union ody_apax_wdog_struct_crd_diag { 1566 uint64_t u; 1567 struct ody_apax_wdog_struct_crd_diag_s { 1568 uint64_t pcrdtype : 4; 1569 uint64_t tgtid : 11; 1570 uint64_t reserved_15_29 : 15; 1571 uint64_t stale : 1; 1572 uint64_t multi : 1; 1573 uint64_t reserved_32_63 : 32; 1574 } s; 1575 /* struct ody_apax_wdog_struct_crd_diag_s cn; */ 1576 }; 1577 typedef union ody_apax_wdog_struct_crd_diag ody_apax_wdog_struct_crd_diag_t; 1578 1579 static inline uint64_t ODY_APAX_WDOG_STRUCT_CRD_DIAG(uint64_t a) __attribute__ ((pure, always_inline)); 1580 static inline uint64_t ODY_APAX_WDOG_STRUCT_CRD_DIAG(uint64_t a) 1581 { 1582 if (a <= 89) 1583 return 0x87e349001318ll + 0x1000000ll * ((a) & 0x7f); 1584 __ody_csr_fatal("APAX_WDOG_STRUCT_CRD_DIAG", 1, a, 0, 0, 0, 0, 0); 1585 } 1586 1587 #define typedef_ODY_APAX_WDOG_STRUCT_CRD_DIAG(a) ody_apax_wdog_struct_crd_diag_t 1588 #define bustype_ODY_APAX_WDOG_STRUCT_CRD_DIAG(a) CSR_TYPE_RSL 1589 #define basename_ODY_APAX_WDOG_STRUCT_CRD_DIAG(a) "APAX_WDOG_STRUCT_CRD_DIAG" 1590 #define device_bar_ODY_APAX_WDOG_STRUCT_CRD_DIAG(a) 0x0 /* PF_BAR0 */ 1591 #define busnum_ODY_APAX_WDOG_STRUCT_CRD_DIAG(a) (a) 1592 #define arguments_ODY_APAX_WDOG_STRUCT_CRD_DIAG(a) (a), -1, -1, -1 1593 1594 /** 1595 * Register (RSL) apa#_wdog_struct_dat_diag 1596 * 1597 * APA WDOG STRUCT DAT DIAG Register 1598 * This register reports and captures watchdog timeouts for DAT, which indicates that 1599 * write data for a store did not get sent. 1600 */ 1601 union ody_apax_wdog_struct_dat_diag { 1602 uint64_t u; 1603 struct ody_apax_wdog_struct_dat_diag_s { 1604 uint64_t dbid : 12; 1605 uint64_t tgtid : 11; 1606 uint64_t has_dbid : 1; 1607 uint64_t datst0 : 3; 1608 uint64_t datst1 : 3; 1609 uint64_t datst2 : 3; 1610 uint64_t datst3 : 3; 1611 uint64_t has_lsw_idx : 1; 1612 uint64_t reserved_37_61 : 25; 1613 uint64_t stale : 1; 1614 uint64_t multi : 1; 1615 } s; 1616 /* struct ody_apax_wdog_struct_dat_diag_s cn; */ 1617 }; 1618 typedef union ody_apax_wdog_struct_dat_diag ody_apax_wdog_struct_dat_diag_t; 1619 1620 static inline uint64_t ODY_APAX_WDOG_STRUCT_DAT_DIAG(uint64_t a) __attribute__ ((pure, always_inline)); 1621 static inline uint64_t ODY_APAX_WDOG_STRUCT_DAT_DIAG(uint64_t a) 1622 { 1623 if (a <= 89) 1624 return 0x87e349001330ll + 0x1000000ll * ((a) & 0x7f); 1625 __ody_csr_fatal("APAX_WDOG_STRUCT_DAT_DIAG", 1, a, 0, 0, 0, 0, 0); 1626 } 1627 1628 #define typedef_ODY_APAX_WDOG_STRUCT_DAT_DIAG(a) ody_apax_wdog_struct_dat_diag_t 1629 #define bustype_ODY_APAX_WDOG_STRUCT_DAT_DIAG(a) CSR_TYPE_RSL 1630 #define basename_ODY_APAX_WDOG_STRUCT_DAT_DIAG(a) "APAX_WDOG_STRUCT_DAT_DIAG" 1631 #define device_bar_ODY_APAX_WDOG_STRUCT_DAT_DIAG(a) 0x0 /* PF_BAR0 */ 1632 #define busnum_ODY_APAX_WDOG_STRUCT_DAT_DIAG(a) (a) 1633 #define arguments_ODY_APAX_WDOG_STRUCT_DAT_DIAG(a) (a), -1, -1, -1 1634 1635 /** 1636 * Register (RSL) apa#_wdog_struct_rqb_diag 1637 * 1638 * APA WDOG STRUCT RQB DIAG Register 1639 * This register reports and captures watchdog timeouts for RQB, which indicates that a 1640 * request has not been acknowledged. 1641 */ 1642 union ody_apax_wdog_struct_rqb_diag { 1643 uint64_t u; 1644 struct ody_apax_wdog_struct_rqb_diag_s { 1645 uint64_t reserved_0_11 : 12; 1646 uint64_t txnid_new : 12; 1647 uint64_t pcrdtype : 4; 1648 uint64_t tgtid : 11; 1649 uint64_t reserved_39 : 1; 1650 uint64_t state : 3; 1651 uint64_t reserved_43_61 : 19; 1652 uint64_t stale : 1; 1653 uint64_t multi : 1; 1654 } s; 1655 /* struct ody_apax_wdog_struct_rqb_diag_s cn; */ 1656 }; 1657 typedef union ody_apax_wdog_struct_rqb_diag ody_apax_wdog_struct_rqb_diag_t; 1658 1659 static inline uint64_t ODY_APAX_WDOG_STRUCT_RQB_DIAG(uint64_t a) __attribute__ ((pure, always_inline)); 1660 static inline uint64_t ODY_APAX_WDOG_STRUCT_RQB_DIAG(uint64_t a) 1661 { 1662 if (a <= 89) 1663 return 0x87e349001328ll + 0x1000000ll * ((a) & 0x7f); 1664 __ody_csr_fatal("APAX_WDOG_STRUCT_RQB_DIAG", 1, a, 0, 0, 0, 0, 0); 1665 } 1666 1667 #define typedef_ODY_APAX_WDOG_STRUCT_RQB_DIAG(a) ody_apax_wdog_struct_rqb_diag_t 1668 #define bustype_ODY_APAX_WDOG_STRUCT_RQB_DIAG(a) CSR_TYPE_RSL 1669 #define basename_ODY_APAX_WDOG_STRUCT_RQB_DIAG(a) "APAX_WDOG_STRUCT_RQB_DIAG" 1670 #define device_bar_ODY_APAX_WDOG_STRUCT_RQB_DIAG(a) 0x0 /* PF_BAR0 */ 1671 #define busnum_ODY_APAX_WDOG_STRUCT_RQB_DIAG(a) (a) 1672 #define arguments_ODY_APAX_WDOG_STRUCT_RQB_DIAG(a) (a), -1, -1, -1 1673 1674 /** 1675 * Register (RSL) apa#_wdog_struct_txnid_diag 1676 * 1677 * APA WDOG STRUCT TXNID DIAG Register 1678 * This register reports and captures watchdog timeouts for TXNID, which indicates that 1679 * a completion was not received. 1680 */ 1681 union ody_apax_wdog_struct_txnid_diag { 1682 uint64_t u; 1683 struct ody_apax_wdog_struct_txnid_diag_s { 1684 uint64_t txnid_orig : 12; 1685 uint64_t txnid_new : 8; 1686 uint64_t reserved_20_29 : 10; 1687 uint64_t stale : 1; 1688 uint64_t multi : 1; 1689 uint64_t reserved_32_63 : 32; 1690 } s; 1691 /* struct ody_apax_wdog_struct_txnid_diag_s cn; */ 1692 }; 1693 typedef union ody_apax_wdog_struct_txnid_diag ody_apax_wdog_struct_txnid_diag_t; 1694 1695 static inline uint64_t ODY_APAX_WDOG_STRUCT_TXNID_DIAG(uint64_t a) __attribute__ ((pure, always_inline)); 1696 static inline uint64_t ODY_APAX_WDOG_STRUCT_TXNID_DIAG(uint64_t a) 1697 { 1698 if (a <= 89) 1699 return 0x87e349001320ll + 0x1000000ll * ((a) & 0x7f); 1700 __ody_csr_fatal("APAX_WDOG_STRUCT_TXNID_DIAG", 1, a, 0, 0, 0, 0, 0); 1701 } 1702 1703 #define typedef_ODY_APAX_WDOG_STRUCT_TXNID_DIAG(a) ody_apax_wdog_struct_txnid_diag_t 1704 #define bustype_ODY_APAX_WDOG_STRUCT_TXNID_DIAG(a) CSR_TYPE_RSL 1705 #define basename_ODY_APAX_WDOG_STRUCT_TXNID_DIAG(a) "APAX_WDOG_STRUCT_TXNID_DIAG" 1706 #define device_bar_ODY_APAX_WDOG_STRUCT_TXNID_DIAG(a) 0x0 /* PF_BAR0 */ 1707 #define busnum_ODY_APAX_WDOG_STRUCT_TXNID_DIAG(a) (a) 1708 #define arguments_ODY_APAX_WDOG_STRUCT_TXNID_DIAG(a) (a), -1, -1, -1 1709 1710 #endif /* __ODY_CSRS_APA_H__ */ 1711