1 /***********************license start*********************************** 2 * Copyright (C) 2021-2026 Marvell. 3 * SPDX-License-Identifier: BSD-3-Clause 4 * https://spdx.org/licenses 5 ***********************license end**************************************/ 6 7 /** 8 * @file 9 * 10 * This is file defines ASM primitives for the executive. 11 12 * <hr>$Revision: 53373 $<hr> 13 * 14 * @defgroup __asm__ Assembly support 15 * @{ 16 */ 17 18 /* This header file can be included from a .S file. Keep non-preprocessor 19 things under !__ASSEMBLER__. */ 20 #ifndef __ASSEMBLER__ 21 22 /* turn the variable name into a string */ 23 #define __TMP_STR(x) __TMP_STR2(x) 24 #define __TMP_STR2(x) #x 25 #define __VASTR(...) #__VA_ARGS__ 26 27 #define MRS_NV(reg, val) __asm__ ("mrs %x[rd]," #reg : [rd] "=r" (val)) 28 #define MRS(reg, val) __asm__ volatile ("mrs %x[rd]," #reg : [rd] "=r" (val)) 29 #define MSR(reg, val) __asm__ volatile ("msr " #reg ",%x[rd]" : : [rd] "r" (val)) 30 31 /* Barriers: The ODY uses non-shared memory (not inner or outer shared 32 in ARM speak). Inner or Outer shared instructions won't work */ 33 #define MB __asm__ volatile ("dmb sy" : : : "memory") /* Full memory barrier, like MIPS SYNC */ 34 #define WMB __asm__ volatile ("dmb st" : : : "memory") /* Write memory barrier, like MIPS SYNCW */ 35 #define RMB __asm__ volatile ("dmb ld" : : : "memory") /* Read memory barrier, only necessary on OcteonTX2 */ 36 #define DSB __asm__ volatile ("dsb sy" : : : "memory") /* Core data synchonization barrier */ 37 #define ISB __asm__ volatile ("isb" : : : "memory") /* Instruction synchronization barrier */ 38 39 /* other useful stuff */ 40 #define WFE __asm__ volatile ("wfe" : : : "memory") /* Wait for event */ 41 #define SEV __asm__ volatile ("sev" : : : "memory") /* Send global event */ 42 43 // prefetch helper 44 #define PREFETCH_PREFX(type, address, offset) \ 45 __asm__ volatile ("PRFUM " type ", [%[rbase],%[off]]" : : [rbase] "r" (address), [off] "I" (offset)) 46 47 // normal prefetch 48 #define PREFETCH(address, offset) PREFETCH_PREFX("PLDL1KEEP", address, offset) 49 50 #define ICACHE_INVALIDATE { __asm__ volatile ("ic iallu" : : ); } // invalidate entire icache 51 52 // Do not push to memory, just invalidate 53 #define CACHE_I_L2(address) \ 54 { __asm__ volatile ("dc ivac, %0" : : "r" (address)); } 55 56 // Push to memory, invalidate 57 #define CACHE_WBI_L2(address) \ 58 { __asm__ volatile ("dc civac, %0" : : "r" (address)); } 59 60 // Push to memory, do not invalidate 61 #define CACHE_WB_L2(address) \ 62 { __asm__ volatile ("dc cvac, %0" : : "r" (address)); } 63 64 #define STORE_PAIR(ptr, data1, data2) { __asm__ volatile ("stp %x[d1], %x[d2], [%[b]]" : [mem] "+m" (*(__uint128_t *)ptr) : [b] "r" (ptr), [d1] "r" (data1), [d2] "r" (data2)); } 65 66 #endif /* __ASSEMBLER__ */ 67 68 /** @} */ 69