1*b5c850d4SMarcin Wojtas /* 2*b5c850d4SMarcin Wojtas * Copyright (C) 2018 Marvell International Ltd. 3*b5c850d4SMarcin Wojtas * 4*b5c850d4SMarcin Wojtas * SPDX-License-Identifier: BSD-3-Clause 5*b5c850d4SMarcin Wojtas * https://spdx.org/licenses 6*b5c850d4SMarcin Wojtas */ 7*b5c850d4SMarcin Wojtas 8*b5c850d4SMarcin Wojtas #ifndef BOARD_MARVELL_DEF_H 9*b5c850d4SMarcin Wojtas #define BOARD_MARVELL_DEF_H 10*b5c850d4SMarcin Wojtas 11*b5c850d4SMarcin Wojtas /* 12*b5c850d4SMarcin Wojtas * Required platform porting definitions common to all ARM 13*b5c850d4SMarcin Wojtas * development platforms 14*b5c850d4SMarcin Wojtas */ 15*b5c850d4SMarcin Wojtas 16*b5c850d4SMarcin Wojtas /* Size of cacheable stacks */ 17*b5c850d4SMarcin Wojtas #if IMAGE_BL1 18*b5c850d4SMarcin Wojtas #if TRUSTED_BOARD_BOOT 19*b5c850d4SMarcin Wojtas # define PLATFORM_STACK_SIZE 0x1000 20*b5c850d4SMarcin Wojtas #else 21*b5c850d4SMarcin Wojtas # define PLATFORM_STACK_SIZE 0x440 22*b5c850d4SMarcin Wojtas #endif 23*b5c850d4SMarcin Wojtas #elif IMAGE_BL2 24*b5c850d4SMarcin Wojtas # if TRUSTED_BOARD_BOOT 25*b5c850d4SMarcin Wojtas # define PLATFORM_STACK_SIZE 0x1000 26*b5c850d4SMarcin Wojtas # else 27*b5c850d4SMarcin Wojtas # define PLATFORM_STACK_SIZE 0x400 28*b5c850d4SMarcin Wojtas # endif 29*b5c850d4SMarcin Wojtas #elif IMAGE_BL31 30*b5c850d4SMarcin Wojtas # define PLATFORM_STACK_SIZE 0x400 31*b5c850d4SMarcin Wojtas #elif IMAGE_BL32 32*b5c850d4SMarcin Wojtas # define PLATFORM_STACK_SIZE 0x440 33*b5c850d4SMarcin Wojtas #endif 34*b5c850d4SMarcin Wojtas 35*b5c850d4SMarcin Wojtas /* 36*b5c850d4SMarcin Wojtas * PLAT_MARVELL_MMAP_ENTRIES depends on the number of entries in the 37*b5c850d4SMarcin Wojtas * plat_arm_mmap array defined for each BL stage. 38*b5c850d4SMarcin Wojtas */ 39*b5c850d4SMarcin Wojtas #if IMAGE_BLE 40*b5c850d4SMarcin Wojtas # define PLAT_MARVELL_MMAP_ENTRIES 3 41*b5c850d4SMarcin Wojtas #endif 42*b5c850d4SMarcin Wojtas #if IMAGE_BL1 43*b5c850d4SMarcin Wojtas # if TRUSTED_BOARD_BOOT 44*b5c850d4SMarcin Wojtas # define PLAT_MARVELL_MMAP_ENTRIES 7 45*b5c850d4SMarcin Wojtas # else 46*b5c850d4SMarcin Wojtas # define PLAT_MARVELL_MMAP_ENTRIES 6 47*b5c850d4SMarcin Wojtas # endif /* TRUSTED_BOARD_BOOT */ 48*b5c850d4SMarcin Wojtas #endif 49*b5c850d4SMarcin Wojtas #if IMAGE_BL2 50*b5c850d4SMarcin Wojtas # define PLAT_MARVELL_MMAP_ENTRIES 8 51*b5c850d4SMarcin Wojtas #endif 52*b5c850d4SMarcin Wojtas #if IMAGE_BL31 53*b5c850d4SMarcin Wojtas #define PLAT_MARVELL_MMAP_ENTRIES 5 54*b5c850d4SMarcin Wojtas #endif 55*b5c850d4SMarcin Wojtas 56*b5c850d4SMarcin Wojtas /* 57*b5c850d4SMarcin Wojtas * Platform specific page table and MMU setup constants 58*b5c850d4SMarcin Wojtas */ 59*b5c850d4SMarcin Wojtas #if IMAGE_BL1 60*b5c850d4SMarcin Wojtas #define MAX_XLAT_TABLES 4 61*b5c850d4SMarcin Wojtas #elif IMAGE_BLE 62*b5c850d4SMarcin Wojtas # define MAX_XLAT_TABLES 4 63*b5c850d4SMarcin Wojtas #elif IMAGE_BL2 64*b5c850d4SMarcin Wojtas # define MAX_XLAT_TABLES 4 65*b5c850d4SMarcin Wojtas #elif IMAGE_BL31 66*b5c850d4SMarcin Wojtas # define MAX_XLAT_TABLES 4 67*b5c850d4SMarcin Wojtas #elif IMAGE_BL32 68*b5c850d4SMarcin Wojtas # define MAX_XLAT_TABLES 4 69*b5c850d4SMarcin Wojtas #endif 70*b5c850d4SMarcin Wojtas 71*b5c850d4SMarcin Wojtas #define MAX_IO_DEVICES 3 72*b5c850d4SMarcin Wojtas #define MAX_IO_HANDLES 4 73*b5c850d4SMarcin Wojtas 74*b5c850d4SMarcin Wojtas #endif /* BOARD_MARVELL_DEF_H */ 75