1d72c486bSLucian Paul-Trifu /* 2d72c486bSLucian Paul-Trifu * Copyright (c) 2022, Arm Limited. All rights reserved. 3d72c486bSLucian Paul-Trifu * 4d72c486bSLucian Paul-Trifu * SPDX-License-Identifier: BSD-3-Clause 5d72c486bSLucian Paul-Trifu */ 6d72c486bSLucian Paul-Trifu 7d72c486bSLucian Paul-Trifu #ifndef PLAT_DRTM_H 8d72c486bSLucian Paul-Trifu #define PLAT_DRTM_H 9d72c486bSLucian Paul-Trifu 102a1cdee4Sjohpow01 #include <stdint.h> 112a1cdee4Sjohpow01 #include <lib/xlat_tables/xlat_tables_compat.h> 122a1cdee4Sjohpow01 132a1cdee4Sjohpow01 typedef struct { 142a1cdee4Sjohpow01 uint8_t max_num_mem_prot_regions; 152a1cdee4Sjohpow01 uint8_t dma_protection_support; 162a1cdee4Sjohpow01 } plat_drtm_dma_prot_features_t; 172a1cdee4Sjohpow01 182a1cdee4Sjohpow01 typedef struct { 192a1cdee4Sjohpow01 bool tpm_based_hash_support; 202a1cdee4Sjohpow01 uint32_t firmware_hash_algorithm; 212a1cdee4Sjohpow01 } plat_drtm_tpm_features_t; 222a1cdee4Sjohpow01 232a1cdee4Sjohpow01 typedef struct { 242a1cdee4Sjohpow01 uint64_t region_address; 252a1cdee4Sjohpow01 uint64_t region_size_type; 262a1cdee4Sjohpow01 } __attribute__((packed)) drtm_mem_region_t; 272a1cdee4Sjohpow01 282a1cdee4Sjohpow01 /* 292a1cdee4Sjohpow01 * Memory region descriptor table structure as per DRTM beta0 section 3.13 302a1cdee4Sjohpow01 * Table 11 MEMORY_REGION_DESCRIPTOR_TABLE 312a1cdee4Sjohpow01 */ 322a1cdee4Sjohpow01 typedef struct { 332a1cdee4Sjohpow01 uint16_t revision; 342a1cdee4Sjohpow01 uint16_t reserved; 352a1cdee4Sjohpow01 uint32_t num_regions; 362a1cdee4Sjohpow01 drtm_mem_region_t region[]; 372a1cdee4Sjohpow01 } __attribute__((packed)) drtm_memory_region_descriptor_table_t; 382a1cdee4Sjohpow01 392a1cdee4Sjohpow01 /* platform specific address map functions */ 402a1cdee4Sjohpow01 const mmap_region_t *plat_get_addr_mmap(void); 412a1cdee4Sjohpow01 42d72c486bSLucian Paul-Trifu /* platform-specific DMA protection functions */ 43d72c486bSLucian Paul-Trifu bool plat_has_non_host_platforms(void); 44d72c486bSLucian Paul-Trifu bool plat_has_unmanaged_dma_peripherals(void); 45d72c486bSLucian Paul-Trifu unsigned int plat_get_total_smmus(void); 46d72c486bSLucian Paul-Trifu void plat_enumerate_smmus(const uintptr_t **smmus_out, 47d72c486bSLucian Paul-Trifu size_t *smmu_count_out); 482a1cdee4Sjohpow01 const plat_drtm_dma_prot_features_t *plat_drtm_get_dma_prot_features(void); 492a1cdee4Sjohpow01 uint64_t plat_drtm_dma_prot_get_max_table_bytes(void); 502a1cdee4Sjohpow01 512a1cdee4Sjohpow01 /* platform-specific TPM functions */ 522a1cdee4Sjohpow01 const plat_drtm_tpm_features_t *plat_drtm_get_tpm_features(void); 532a1cdee4Sjohpow01 542a1cdee4Sjohpow01 /* 552a1cdee4Sjohpow01 * TODO: Implement these functions as per the platform use case, 562a1cdee4Sjohpow01 * as of now none of the platform uses these functions 572a1cdee4Sjohpow01 */ 582a1cdee4Sjohpow01 uint64_t plat_drtm_get_min_size_normal_world_dce(void); 592a1cdee4Sjohpow01 uint64_t plat_drtm_get_tcb_hash_table_size(void); 602a1cdee4Sjohpow01 uint64_t plat_drtm_get_imp_def_dlme_region_size(void); 612a1cdee4Sjohpow01 uint64_t plat_drtm_get_tcb_hash_features(void); 62d72c486bSLucian Paul-Trifu 63586f60ccSManish V Badarkhe /* DRTM error handling functions */ 64586f60ccSManish V Badarkhe int plat_set_drtm_error(uint64_t error_code); 65586f60ccSManish V Badarkhe int plat_get_drtm_error(uint64_t *error_code); 66586f60ccSManish V Badarkhe 67*d5f225d9SManish V Badarkhe /* 68*d5f225d9SManish V Badarkhe * Platform-specific function to ensure passed region lies within 69*d5f225d9SManish V Badarkhe * Non-Secure region of DRAM 70*d5f225d9SManish V Badarkhe */ 71*d5f225d9SManish V Badarkhe int plat_drtm_validate_ns_region(uintptr_t region_start, 72*d5f225d9SManish V Badarkhe size_t region_size); 73*d5f225d9SManish V Badarkhe 74d72c486bSLucian Paul-Trifu #endif /* PLAT_DRTM_H */ 75