1d72c486bSLucian Paul-Trifu /* 2d72c486bSLucian Paul-Trifu * Copyright (c) 2022, Arm Limited. All rights reserved. 3d72c486bSLucian Paul-Trifu * 4d72c486bSLucian Paul-Trifu * SPDX-License-Identifier: BSD-3-Clause 5d72c486bSLucian Paul-Trifu */ 6d72c486bSLucian Paul-Trifu 7d72c486bSLucian Paul-Trifu #ifndef PLAT_DRTM_H 8d72c486bSLucian Paul-Trifu #define PLAT_DRTM_H 9d72c486bSLucian Paul-Trifu 10*2a1cdee4Sjohpow01 #include <stdint.h> 11*2a1cdee4Sjohpow01 #include <lib/xlat_tables/xlat_tables_compat.h> 12*2a1cdee4Sjohpow01 13*2a1cdee4Sjohpow01 typedef struct { 14*2a1cdee4Sjohpow01 uint8_t max_num_mem_prot_regions; 15*2a1cdee4Sjohpow01 uint8_t dma_protection_support; 16*2a1cdee4Sjohpow01 } plat_drtm_dma_prot_features_t; 17*2a1cdee4Sjohpow01 18*2a1cdee4Sjohpow01 typedef struct { 19*2a1cdee4Sjohpow01 bool tpm_based_hash_support; 20*2a1cdee4Sjohpow01 uint32_t firmware_hash_algorithm; 21*2a1cdee4Sjohpow01 } plat_drtm_tpm_features_t; 22*2a1cdee4Sjohpow01 23*2a1cdee4Sjohpow01 typedef struct { 24*2a1cdee4Sjohpow01 uint64_t region_address; 25*2a1cdee4Sjohpow01 uint64_t region_size_type; 26*2a1cdee4Sjohpow01 } __attribute__((packed)) drtm_mem_region_t; 27*2a1cdee4Sjohpow01 28*2a1cdee4Sjohpow01 /* 29*2a1cdee4Sjohpow01 * Memory region descriptor table structure as per DRTM beta0 section 3.13 30*2a1cdee4Sjohpow01 * Table 11 MEMORY_REGION_DESCRIPTOR_TABLE 31*2a1cdee4Sjohpow01 */ 32*2a1cdee4Sjohpow01 typedef struct { 33*2a1cdee4Sjohpow01 uint16_t revision; 34*2a1cdee4Sjohpow01 uint16_t reserved; 35*2a1cdee4Sjohpow01 uint32_t num_regions; 36*2a1cdee4Sjohpow01 drtm_mem_region_t region[]; 37*2a1cdee4Sjohpow01 } __attribute__((packed)) drtm_memory_region_descriptor_table_t; 38*2a1cdee4Sjohpow01 39*2a1cdee4Sjohpow01 /* platform specific address map functions */ 40*2a1cdee4Sjohpow01 const mmap_region_t *plat_get_addr_mmap(void); 41*2a1cdee4Sjohpow01 42d72c486bSLucian Paul-Trifu /* platform-specific DMA protection functions */ 43d72c486bSLucian Paul-Trifu bool plat_has_non_host_platforms(void); 44d72c486bSLucian Paul-Trifu bool plat_has_unmanaged_dma_peripherals(void); 45d72c486bSLucian Paul-Trifu unsigned int plat_get_total_smmus(void); 46d72c486bSLucian Paul-Trifu void plat_enumerate_smmus(const uintptr_t **smmus_out, 47d72c486bSLucian Paul-Trifu size_t *smmu_count_out); 48*2a1cdee4Sjohpow01 const plat_drtm_dma_prot_features_t *plat_drtm_get_dma_prot_features(void); 49*2a1cdee4Sjohpow01 uint64_t plat_drtm_dma_prot_get_max_table_bytes(void); 50*2a1cdee4Sjohpow01 51*2a1cdee4Sjohpow01 /* platform-specific TPM functions */ 52*2a1cdee4Sjohpow01 const plat_drtm_tpm_features_t *plat_drtm_get_tpm_features(void); 53*2a1cdee4Sjohpow01 54*2a1cdee4Sjohpow01 /* 55*2a1cdee4Sjohpow01 * TODO: Implement these functions as per the platform use case, 56*2a1cdee4Sjohpow01 * as of now none of the platform uses these functions 57*2a1cdee4Sjohpow01 */ 58*2a1cdee4Sjohpow01 uint64_t plat_drtm_get_min_size_normal_world_dce(void); 59*2a1cdee4Sjohpow01 uint64_t plat_drtm_get_tcb_hash_table_size(void); 60*2a1cdee4Sjohpow01 uint64_t plat_drtm_get_imp_def_dlme_region_size(void); 61*2a1cdee4Sjohpow01 uint64_t plat_drtm_get_tcb_hash_features(void); 62d72c486bSLucian Paul-Trifu 63d72c486bSLucian Paul-Trifu #endif /* PLAT_DRTM_H */ 64