xref: /rk3399_ARM-atf/include/plat/brcm/common/brcm_def.h (revision 926cd70a0cc3a0cbf209a87765a8dc0b869798e3)
1*717448d6SSheetal Tigadoli /*
2*717448d6SSheetal Tigadoli  * Copyright (c) 2016 - 2020, Broadcom
3*717448d6SSheetal Tigadoli  *
4*717448d6SSheetal Tigadoli  * SPDX-License-Identifier: BSD-3-Clause
5*717448d6SSheetal Tigadoli  */
6*717448d6SSheetal Tigadoli 
7*717448d6SSheetal Tigadoli #ifndef BRCM_DEF_H
8*717448d6SSheetal Tigadoli #define BRCM_DEF_H
9*717448d6SSheetal Tigadoli 
10*717448d6SSheetal Tigadoli #include <arch.h>
11*717448d6SSheetal Tigadoli #include <common/tbbr/tbbr_img_def.h>
12*717448d6SSheetal Tigadoli #include <lib/utils_def.h>
13*717448d6SSheetal Tigadoli #include <lib/xlat_tables/xlat_tables.h>
14*717448d6SSheetal Tigadoli #include <plat/common/common_def.h>
15*717448d6SSheetal Tigadoli 
16*717448d6SSheetal Tigadoli #include <platform_def.h>
17*717448d6SSheetal Tigadoli 
18*717448d6SSheetal Tigadoli #define PLAT_PHY_ADDR_SPACE_SIZE	BIT_64(32)
19*717448d6SSheetal Tigadoli #define PLAT_VIRT_ADDR_SPACE_SIZE	BIT_64(32)
20*717448d6SSheetal Tigadoli 
21*717448d6SSheetal Tigadoli #define BL11_DAUTH_ID			0x796C51ab
22*717448d6SSheetal Tigadoli #define BL11_DAUTH_BASE			BL11_RW_BASE
23*717448d6SSheetal Tigadoli 
24*717448d6SSheetal Tigadoli /* We keep a table at the end of ROM for function pointers */
25*717448d6SSheetal Tigadoli #define ROM_TABLE_SIZE			32
26*717448d6SSheetal Tigadoli #define BL1_ROM_TABLE			(BL1_RO_LIMIT - ROM_TABLE_SIZE)
27*717448d6SSheetal Tigadoli 
28*717448d6SSheetal Tigadoli /*
29*717448d6SSheetal Tigadoli  * The top 16MB of DRAM1 is configured as secure access only using the TZC
30*717448d6SSheetal Tigadoli  *   - SCP TZC DRAM: If present, DRAM reserved for SCP use
31*717448d6SSheetal Tigadoli  *   - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use
32*717448d6SSheetal Tigadoli  */
33*717448d6SSheetal Tigadoli #define BRCM_TZC_DRAM1_SIZE		ULL(0x01000000)
34*717448d6SSheetal Tigadoli 
35*717448d6SSheetal Tigadoli #define BRCM_SCP_TZC_DRAM1_BASE		(BRCM_DRAM1_BASE +		\
36*717448d6SSheetal Tigadoli 					 BRCM_DRAM1_SIZE -		\
37*717448d6SSheetal Tigadoli 					 BRCM_SCP_TZC_DRAM1_SIZE)
38*717448d6SSheetal Tigadoli #define BRCM_SCP_TZC_DRAM1_SIZE		PLAT_BRCM_SCP_TZC_DRAM1_SIZE
39*717448d6SSheetal Tigadoli 
40*717448d6SSheetal Tigadoli #define BRCM_AP_TZC_DRAM1_BASE		(BRCM_DRAM1_BASE +		\
41*717448d6SSheetal Tigadoli 					 BRCM_DRAM1_SIZE -		\
42*717448d6SSheetal Tigadoli 					 BRCM_TZC_DRAM1_SIZE)
43*717448d6SSheetal Tigadoli #define BRCM_AP_TZC_DRAM1_SIZE		(BRCM_TZC_DRAM1_SIZE -		\
44*717448d6SSheetal Tigadoli 					 BRCM_SCP_TZC_DRAM1_SIZE)
45*717448d6SSheetal Tigadoli 
46*717448d6SSheetal Tigadoli #define BRCM_NS_DRAM1_BASE		BRCM_DRAM1_BASE
47*717448d6SSheetal Tigadoli #define BRCM_NS_DRAM1_SIZE		(BRCM_DRAM1_SIZE -		\
48*717448d6SSheetal Tigadoli 					 BRCM_TZC_DRAM1_SIZE)
49*717448d6SSheetal Tigadoli 
50*717448d6SSheetal Tigadoli #ifdef BRCM_SHARED_DRAM_BASE
51*717448d6SSheetal Tigadoli #define BRCM_NS_SHARED_DRAM_BASE	BRCM_SHARED_DRAM_BASE
52*717448d6SSheetal Tigadoli #define BRCM_NS_SHARED_DRAM_SIZE	BRCM_SHARED_DRAM_SIZE
53*717448d6SSheetal Tigadoli #endif
54*717448d6SSheetal Tigadoli 
55*717448d6SSheetal Tigadoli #define BRCM_MAP_SHARED_RAM		MAP_REGION_FLAT(		\
56*717448d6SSheetal Tigadoli 						BRCM_SHARED_RAM_BASE,	\
57*717448d6SSheetal Tigadoli 						BRCM_SHARED_RAM_SIZE,	\
58*717448d6SSheetal Tigadoli 						MT_DEVICE | MT_RW | MT_SECURE)
59*717448d6SSheetal Tigadoli 
60*717448d6SSheetal Tigadoli #define BRCM_MAP_NS_DRAM1		MAP_REGION_FLAT(		\
61*717448d6SSheetal Tigadoli 						BRCM_NS_DRAM1_BASE,	\
62*717448d6SSheetal Tigadoli 						BRCM_NS_DRAM1_SIZE,	\
63*717448d6SSheetal Tigadoli 						MT_MEMORY | MT_RW | MT_NS)
64*717448d6SSheetal Tigadoli 
65*717448d6SSheetal Tigadoli #ifdef BRCM_SHARED_DRAM_BASE
66*717448d6SSheetal Tigadoli #define BRCM_MAP_NS_SHARED_DRAM		MAP_REGION_FLAT(		 \
67*717448d6SSheetal Tigadoli 						BRCM_NS_SHARED_DRAM_BASE, \
68*717448d6SSheetal Tigadoli 						BRCM_NS_SHARED_DRAM_SIZE, \
69*717448d6SSheetal Tigadoli 						MT_MEMORY | MT_RW | MT_NS)
70*717448d6SSheetal Tigadoli #endif
71*717448d6SSheetal Tigadoli 
72*717448d6SSheetal Tigadoli #ifdef BRCM_EXT_SRAM_BASE
73*717448d6SSheetal Tigadoli #define BRCM_MAP_EXT_SRAM		MAP_REGION_FLAT(		\
74*717448d6SSheetal Tigadoli 						BRCM_EXT_SRAM_BASE,	\
75*717448d6SSheetal Tigadoli 						BRCM_EXT_SRAM_SIZE,	\
76*717448d6SSheetal Tigadoli 						MT_DEVICE | MT_RW | MT_SECURE)
77*717448d6SSheetal Tigadoli #endif
78*717448d6SSheetal Tigadoli 
79*717448d6SSheetal Tigadoli #define BRCM_MAP_NAND_RO		MAP_REGION_FLAT(NAND_BASE_ADDR,\
80*717448d6SSheetal Tigadoli 						NAND_SIZE,	\
81*717448d6SSheetal Tigadoli 						MT_MEMORY | MT_RO | MT_SECURE)
82*717448d6SSheetal Tigadoli 
83*717448d6SSheetal Tigadoli #define BRCM_MAP_QSPI_RO		MAP_REGION_FLAT(QSPI_BASE_ADDR,\
84*717448d6SSheetal Tigadoli 						QSPI_SIZE,	\
85*717448d6SSheetal Tigadoli 						MT_MEMORY | MT_RO | MT_SECURE)
86*717448d6SSheetal Tigadoli 
87*717448d6SSheetal Tigadoli #define HSLS_REGION	MAP_REGION_FLAT(HSLS_BASE_ADDR, \
88*717448d6SSheetal Tigadoli 					HSLS_SIZE, \
89*717448d6SSheetal Tigadoli 					MT_DEVICE | MT_RW | MT_SECURE)
90*717448d6SSheetal Tigadoli 
91*717448d6SSheetal Tigadoli #define CCN_REGION	MAP_REGION_FLAT(PLAT_BRCM_CCN_BASE, \
92*717448d6SSheetal Tigadoli 					CCN_SIZE, \
93*717448d6SSheetal Tigadoli 					MT_DEVICE | MT_RW | MT_SECURE)
94*717448d6SSheetal Tigadoli 
95*717448d6SSheetal Tigadoli #define GIC500_REGION	MAP_REGION_FLAT(GIC500_BASE, \
96*717448d6SSheetal Tigadoli 					GIC500_SIZE, \
97*717448d6SSheetal Tigadoli 					MT_DEVICE | MT_RW | MT_SECURE)
98*717448d6SSheetal Tigadoli #ifdef PERIPH0_BASE
99*717448d6SSheetal Tigadoli #define PERIPH0_REGION	MAP_REGION_FLAT(PERIPH0_BASE, \
100*717448d6SSheetal Tigadoli 					PERIPH0_SIZE, \
101*717448d6SSheetal Tigadoli 					MT_DEVICE | MT_RW | MT_SECURE)
102*717448d6SSheetal Tigadoli #endif
103*717448d6SSheetal Tigadoli 
104*717448d6SSheetal Tigadoli #ifdef PERIPH1_BASE
105*717448d6SSheetal Tigadoli #define PERIPH1_REGION	MAP_REGION_FLAT(PERIPH1_BASE, \
106*717448d6SSheetal Tigadoli 					PERIPH1_SIZE, \
107*717448d6SSheetal Tigadoli 					MT_DEVICE | MT_RW | MT_SECURE)
108*717448d6SSheetal Tigadoli #endif
109*717448d6SSheetal Tigadoli 
110*717448d6SSheetal Tigadoli #ifdef PERIPH2_BASE
111*717448d6SSheetal Tigadoli #define PERIPH2_REGION	MAP_REGION_FLAT(PERIPH2_BASE, \
112*717448d6SSheetal Tigadoli 					PERIPH2_SIZE, \
113*717448d6SSheetal Tigadoli 					MT_DEVICE | MT_RW | MT_SECURE)
114*717448d6SSheetal Tigadoli #endif
115*717448d6SSheetal Tigadoli 
116*717448d6SSheetal Tigadoli #if BRCM_BL31_IN_DRAM
117*717448d6SSheetal Tigadoli #if IMAGE_BL2
118*717448d6SSheetal Tigadoli #define BRCM_MAP_BL31_SEC_DRAM		MAP_REGION_FLAT(		\
119*717448d6SSheetal Tigadoli 						BL31_BASE,		\
120*717448d6SSheetal Tigadoli 						PLAT_BRCM_MAX_BL31_SIZE,\
121*717448d6SSheetal Tigadoli 						MT_DEVICE | MT_RW | MT_SECURE)
122*717448d6SSheetal Tigadoli #else
123*717448d6SSheetal Tigadoli #define BRCM_MAP_BL31_SEC_DRAM		MAP_REGION_FLAT(		\
124*717448d6SSheetal Tigadoli 						BL31_BASE,		\
125*717448d6SSheetal Tigadoli 						PLAT_BRCM_MAX_BL31_SIZE,\
126*717448d6SSheetal Tigadoli 						MT_MEMORY | MT_RW | MT_SECURE)
127*717448d6SSheetal Tigadoli #endif
128*717448d6SSheetal Tigadoli #endif
129*717448d6SSheetal Tigadoli 
130*717448d6SSheetal Tigadoli #if defined(USB_BASE) && defined(DRIVER_USB_ENABLE)
131*717448d6SSheetal Tigadoli #define USB_REGION			MAP_REGION_FLAT(  \
132*717448d6SSheetal Tigadoli 						USB_BASE, \
133*717448d6SSheetal Tigadoli 						USB_SIZE, \
134*717448d6SSheetal Tigadoli 						MT_DEVICE | MT_RW | MT_SECURE)
135*717448d6SSheetal Tigadoli #endif
136*717448d6SSheetal Tigadoli 
137*717448d6SSheetal Tigadoli #ifdef USE_CRMU_SRAM
138*717448d6SSheetal Tigadoli #define CRMU_SRAM_REGION		MAP_REGION_FLAT(		\
139*717448d6SSheetal Tigadoli 						CRMU_SRAM_BASE,		\
140*717448d6SSheetal Tigadoli 						CRMU_SRAM_SIZE,		\
141*717448d6SSheetal Tigadoli 						MT_DEVICE | MT_RW | MT_SECURE)
142*717448d6SSheetal Tigadoli #endif
143*717448d6SSheetal Tigadoli /*
144*717448d6SSheetal Tigadoli  * The number of regions like RO(code), coherent and data required by
145*717448d6SSheetal Tigadoli  * different BL stages which need to be mapped in the MMU.
146*717448d6SSheetal Tigadoli  */
147*717448d6SSheetal Tigadoli #if USE_COHERENT_MEM
148*717448d6SSheetal Tigadoli #define BRCM_BL_REGIONS			3
149*717448d6SSheetal Tigadoli #else
150*717448d6SSheetal Tigadoli #define BRCM_BL_REGIONS			2
151*717448d6SSheetal Tigadoli #endif
152*717448d6SSheetal Tigadoli 
153*717448d6SSheetal Tigadoli #endif /* BRCM_DEF_H */
154