1b4315306SDan Handley /* 29edac047SDavid Cunado * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3b4315306SDan Handley * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5b4315306SDan Handley */ 6b4315306SDan Handley 7c3cf06f1SAntonio Nino Diaz #ifndef SOC_CSS_DEF_H 8c3cf06f1SAntonio Nino Diaz #define SOC_CSS_DEF_H 9b4315306SDan Handley 10*09d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 11*09d40e0eSAntonio Nino Diaz #include <plat/common/common_def.h> 12b4315306SDan Handley 13b4315306SDan Handley /* 14b4315306SDan Handley * Definitions common to all ARM CSS SoCs 15b4315306SDan Handley */ 16b4315306SDan Handley 17b4315306SDan Handley /* Following covers ARM CSS SoC Peripherals and PCIe expansion area */ 18b4315306SDan Handley #define SOC_CSS_DEVICE_BASE 0x40000000 19b4315306SDan Handley #define SOC_CSS_DEVICE_SIZE 0x40000000 20b4315306SDan Handley #define SOC_CSS_PCIE_CONTROL_BASE 0x7ff20000 21b4315306SDan Handley 22b4315306SDan Handley /* PL011 UART related constants */ 23b4315306SDan Handley #define SOC_CSS_UART0_BASE 0x7ff80000 24b4315306SDan Handley #define SOC_CSS_UART1_BASE 0x7ff70000 25b4315306SDan Handley 268d34073dSDimitris Papastamos #define SOC_CSS_UART0_CLK_IN_HZ 7372800 278d34073dSDimitris Papastamos #define SOC_CSS_UART1_CLK_IN_HZ 7372800 28b4315306SDan Handley 29b4315306SDan Handley /* SoC NIC-400 Global Programmers View (GPV) */ 30b4315306SDan Handley #define SOC_CSS_NIC400_BASE 0x7fd00000 31b4315306SDan Handley 32b4315306SDan Handley #define SOC_CSS_NIC400_USB_EHCI 0 33b4315306SDan Handley #define SOC_CSS_NIC400_TLX_MASTER 1 34b4315306SDan Handley #define SOC_CSS_NIC400_USB_OHCI 2 35b4315306SDan Handley #define SOC_CSS_NIC400_PL354_SMC 3 36b4315306SDan Handley /* 37b4315306SDan Handley * The apb4_bridge controls access to: 38b4315306SDan Handley * - the PCIe configuration registers 39b4315306SDan Handley * - the MMU units for USB, HDLCD and DMA 40b4315306SDan Handley */ 41b4315306SDan Handley #define SOC_CSS_NIC400_APB4_BRIDGE 4 42b4315306SDan Handley 4348279d52SJuan Castillo /* Non-volatile counters */ 4448279d52SJuan Castillo #define SOC_TRUSTED_NVCTR_BASE 0x7fe70000 4548279d52SJuan Castillo #define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0000) 4648279d52SJuan Castillo #define TFW_NVCTR_SIZE 4 4748279d52SJuan Castillo #define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004) 4848279d52SJuan Castillo #define NTFW_CTR_SIZE 4 4948279d52SJuan Castillo 5095cfd4adSJuan Castillo /* Keys */ 5195cfd4adSJuan Castillo #define SOC_KEYS_BASE 0x7fe80000 5295cfd4adSJuan Castillo #define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000) 5395cfd4adSJuan Castillo #define TZ_PUB_KEY_HASH_SIZE 32 5495cfd4adSJuan Castillo #define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020) 5595cfd4adSJuan Castillo #define HU_KEY_SIZE 16 5695cfd4adSJuan Castillo #define END_KEY_BASE (SOC_KEYS_BASE + 0x0044) 5795cfd4adSJuan Castillo #define END_KEY_SIZE 32 58b4315306SDan Handley 59b4315306SDan Handley #define SOC_CSS_MAP_DEVICE MAP_REGION_FLAT( \ 60b4315306SDan Handley SOC_CSS_DEVICE_BASE, \ 61b4315306SDan Handley SOC_CSS_DEVICE_SIZE, \ 62b4315306SDan Handley MT_DEVICE | MT_RW | MT_SECURE) 63b4315306SDan Handley 64b4315306SDan Handley 65b4315306SDan Handley /* 66b4315306SDan Handley * The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs. 67b4315306SDan Handley */ 68b4315306SDan Handley #define SOC_CSS_NIC400_BOOTSEC_BRIDGE 5 69b4315306SDan Handley #define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1 (1 << 12) 70b4315306SDan Handley 71b4315306SDan Handley /* 72b4315306SDan Handley * Required platform porting definitions common to all ARM CSS SoCs 73b4315306SDan Handley */ 7407570d59SYatharth Kochar #if JUNO_AARCH32_EL3_RUNTIME 7507570d59SYatharth Kochar /* 7607570d59SYatharth Kochar * Following change is required to initialize TZC 7707570d59SYatharth Kochar * for enabling access to the HI_VECTOR (0xFFFF0000) 7807570d59SYatharth Kochar * location needed for JUNO AARCH32 support. 7907570d59SYatharth Kochar */ 8007570d59SYatharth Kochar #define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x8000) 8107570d59SYatharth Kochar #else 82b4315306SDan Handley /* 2MB used for SCP DDR retraining */ 839edac047SDavid Cunado #define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x00200000) 8407570d59SYatharth Kochar #endif 85b4315306SDan Handley 86c3cf06f1SAntonio Nino Diaz #endif /* SOC_CSS_DEF_H */ 87