1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __CSS_DEF_H__ 32 #define __CSS_DEF_H__ 33 34 #include <arm_def.h> 35 #include <tzc400.h> 36 37 /************************************************************************* 38 * Definitions common to all ARM Compute SubSystems (CSS) 39 *************************************************************************/ 40 #define MHU_SECURE_BASE ARM_SHARED_RAM_BASE 41 #define MHU_SECURE_SIZE ARM_SHARED_RAM_SIZE 42 #define MHU_PAYLOAD_CACHED 0 43 44 #define TRUSTED_MAILBOXES_BASE MHU_SECURE_BASE 45 #define TRUSTED_MAILBOX_SHIFT 4 46 47 #define NSROM_BASE 0x1f000000 48 #define NSROM_SIZE 0x00001000 49 50 /* Following covers CSS Peripherals excluding NSROM and NSRAM */ 51 #define CSS_DEVICE_BASE 0x20000000 52 #define CSS_DEVICE_SIZE 0x0e000000 53 #define MHU_BASE 0x2b1f0000 54 55 #define NSRAM_BASE 0x2e000000 56 #define NSRAM_SIZE 0x00008000 57 58 /* The slave_bootsecure controls access to GPU, DMC and CS. */ 59 #define CSS_NIC400_SLAVE_BOOTSECURE 8 60 61 /* Interrupt handling constants */ 62 #define CSS_IRQ_MHU 69 63 #define CSS_IRQ_GPU_SMMU_0 71 64 #define CSS_IRQ_GPU_SMMU_1 73 65 #define CSS_IRQ_ETR_SMMU 75 66 #define CSS_IRQ_TZC 80 67 #define CSS_IRQ_TZ_WDOG 86 68 69 /* 70 * SCP <=> AP boot configuration 71 * 72 * The SCP/AP boot configuration is a 32-bit word located at a known offset from 73 * the start of the Trusted SRAM. Part of this configuration is which CPU is the 74 * primary, according to the shift and mask definitions below. 75 * 76 * Note that the value stored at this address is only valid at boot time, before 77 * the BL3-0 image is transferred to SCP. 78 */ 79 #define SCP_BOOT_CFG_ADDR (ARM_TRUSTED_SRAM_BASE + 0x80) 80 #define PRIMARY_CPU_SHIFT 8 81 #define PRIMARY_CPU_BIT_WIDTH 4 82 83 84 #define CSS_MAP_DEVICE MAP_REGION_FLAT( \ 85 CSS_DEVICE_BASE, \ 86 CSS_DEVICE_SIZE, \ 87 MT_DEVICE | MT_RW | MT_SECURE) 88 89 90 /************************************************************************* 91 * Required platform porting definitions common to all 92 * ARM Compute SubSystems (CSS) 93 ************************************************************************/ 94 95 /* 96 * Load address of BL3-0 in CSS platform ports 97 * BL3-0 is loaded to the same place as BL3-1. Once BL3-0 is transferred to the 98 * SCP, it is discarded and BL3-1 is loaded over the top. 99 */ 100 #define BL30_BASE BL31_BASE 101 102 #define PLAT_ARM_SHARED_RAM_CACHED MHU_PAYLOAD_CACHED 103 104 /* Load address of Non-Secure Image for CSS platform ports */ 105 #define PLAT_ARM_NS_IMAGE_OFFSET 0xE0000000 106 107 /* TZC related constants */ 108 #define PLAT_ARM_TZC_FILTERS REG_ATTR_FILTER_BIT_ALL 109 110 111 #endif /* __CSS_DEF_H__ */ 112